Add parsing and elaboration for chained calls on expression results,
with sv_call_chain_method1 regression.
Split from steveicarus/iverilog#1330 (part 02/6).
Check that nature and discipline declaration names can match visible type
identifiers. Also check `potential` and `flow` references to nature names that
are visible as type identifiers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Verilog-AMS nature and discipline declarations can use names that are also
visible as type identifiers. The `potential` and `flow` discipline items can
likewise reference a nature whose name is returned as `TYPE_IDENTIFIER` by the
lexer. These grammar positions currently only accept `IDENTIFIER`.
Use `identifier_name` for nature and discipline declaration names and for the
`potential` and `flow` nature references.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that a for loop variable declaration can use the same name as a
visible typedef, including references from the loop condition and step
expressions.
Also check that procedural foreach can parse an array expression name that
is initially seen as a type identifier. Declare the array after the loop so
the parser sees the outer typedef while parsing the foreach header, then
elaboration resolves the array declaration as a module item.
Use unsigned variables and omit the foreach iterator because these tests do
not depend on signed values or iteration behavior. This lets both tests run
through the vlog95 backend as normal regressions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows a declaration in an inner scope to use the same name as
a type identifier from an outer scope. The lexer reports such names as
`TYPE_IDENTIFIER` until the new declaration has been installed.
The parser previously created the synthetic loop scope and declared the loop
variable only after parsing the complete `for` header. When the variable name
matches a visible typedef, this is too late: the lexer can continue returning
`TYPE_IDENTIFIER` for references to the variable in the initializer,
condition, and step expressions. Accept `identifier_name` for the declaration
name and create the loop scope and variable in a mid-rule action immediately
after it, so the declaration is visible while the rest of the header is
parsed.
The executable foreach grammar also used to require the array expression name
before the index list to be an `IDENTIFIER`. Use `identifier_name` there as
well, since this position is an expression name followed by `[` and not a type
name.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that a standard attribute name can match a visible typedef. Also check
that the global `$attribute` extension can target a primitive whose name is
visible as a type identifier.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Standard attribute names and target names in both forms of the Icarus
`$attribute` extension are unambiguous identifier positions. When such a name
matches a visible typedef the lexer returns `TYPE_IDENTIFIER`, while the
grammar only accepts `IDENTIFIER`.
Use `identifier_name` for all of these positions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The parameter_omit tests have different expectations depending on whether the
regression is run in the default Verilog mode or with force SystemVerilog.
The old list files modelled this by registering the same tests in both
regress-vlg.list and regress-fsv.list.
Move the tests to JSON descriptors. Use the existing force-sv override for the
forms that are valid SystemVerilog, and keep the implicit type cases as CE in
both modes. This also runs the tests through the additional configurations
supported by vvp_reg.py, providing better coverage in CI.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The LRM allows omitting the `parameter` keyword in a module parameter port
list, but the optional type in that form is a data_type, not an implicit
data type. A parameter port list like this is therefore invalid:
module M #([3:0] P = 1);
The parameter declaration grammar was reusing the general
value_parameter_assign_with_type rule for the omitted-keyword form. That rule
also accepts implicit types so that ordinary `parameter signed P = 1`
declarations work, which made the omitted-keyword form accept implicit types
as well.
Add a separate rule for value parameter assignments without the `parameter`
keyword. The rule still accepts bare identifiers and explicit data types so a
parameter name can shadow a visible typedef name, but it rejects implicit
types.
Fixes: e56c93a2be ("Support shadowing type identifiers in parameter declarations")
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The br_gh1385a, br_gh1385b, and br_gh1385c JSON descriptors mark the vlog95
variants as compile errors. The enum typedefs are translated correctly, so the
compile error expectation causes the tests to fail when compilation succeeds.
Remove the stale overrides and run the translated tests through vlog95.
Fixes: 10349287a0 ("Add regression tests for enum typedefs in nested scopes")
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that a named binding selector can have the same text as a visible typedef
name. Cover named module port connections, named parameter overrides, and named
task, function and constructor arguments.
Also check that a modport simple port selector can shadow a visible typedef
name. Modport simple port aliases share the same parser rule but declare the
modport-visible name rather than binding to an existing formal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
A named binding selector such as `.T(expr)` names an existing formal port,
parameter, task or function argument, or constructor argument. It is not a
declaration of a new identifier. If a visible typedef named `T` exists at the
use site the lexer returns `TYPE_IDENTIFIER`, which made the parser reject the
binding selector.
Modport simple port aliases use the same grammar, but are slightly different:
the selector is the modport-visible port name and can shadow a visible typedef
name in the interface scope.
Use `identifier_name` for the selector name in `named_expression` and
`named_expression_opt`. This covers named parameter overrides, named task and
function arguments, named constructor arguments, and modport simple port
aliases. Also use `identifier_name` in the named module port connection rules,
including implicit named port connections and error recovery.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Fold in Windows VPI routing for vpip_format_pretty, fix queue method
argument elaboration via elaborate_rval_expr, reject class tasks used as
expressions cleanly, and update br1005 now that class queues compile.
Review follow-up: move vpip_format_pretty to vpip_format.cc with
diagnostic return strings, restore NetNet-based queue method elaboration
with a separate property path, drop spurious /devel/ from .gitignore,
and bump copyright years on touched files.
Formatting pass per inline review: brace style for multi-line if bodies,
||/&& at end-of-line continuations, switch/case indentation, single-line
if returns, NetNet-based sys_task_method_ again, and aligned extern decls.
Check that event declarations can use visible type identifiers as event names.
Also check that the resulting named event can be triggered and waited on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows a declaration in an inner scope to use the same name as a
type identifier from an outer scope. This also applies to named event
declarations. The lexer reports such names as `TYPE_IDENTIFIER` before the
event has been installed, which made constructs such as:
typedef int T;
module test;
event T;
endmodule
fail in the event declaration grammar.
Event declarations do not have the local type/name ambiguity that exists for
variable, net, or parameter declarations. The name in `event_variable` is
always the event name. Use `identifier_name` so a `TYPE_IDENTIFIER` token can
be accepted as the event name.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that visible type identifiers can be reused as named block labels. Cover
procedural `begin` blocks, fork blocks, and conditional generate blocks. Also
check matching end labels where the grammar consumes the shared `label_opt`
rule.
The generate test keeps the existing vlog95 compile-error expectation because
named generate scopes are not translated by the vlog95 target.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows a named block label in an inner scope to use the same
name as a visible type identifier from an outer scope. The lexer reports such
names as `TYPE_IDENTIFIER` before the label has been installed, which made
constructs such as:
typedef int T;
module test;
initial begin
begin : T
end : T
end
endmodule
fail in the block label grammar.
The affected grammar positions are label names, not declarations with an
adjacent type/name ambiguity. Use `identifier_name` for `label_opt` and for the
anachronistic named generate begin form so a token returned as `TYPE_IDENTIFIER`
can still be accepted as the label name. With `label_opt` able to handle
`TYPE_IDENTIFIER`, the separate class end-label rule is no longer needed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that a package declaration can use a visible type identifier as its
package name. Also check that the resulting package scope can be selected with
a scope-qualified reference.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows a package declaration to use a name that is also visible
as a type identifier. The lexer reports such names as `TYPE_IDENTIFIER` before
the package has been installed, which made constructs such as:
package p;
typedef int T;
endpackage
import p::*;
package T;
endpackage
fail in the package declaration grammar.
Package declarations do not have the local type/name ambiguity that exists for
variable, net, or parameter declarations. After the optional lifetime the next
token is always the package name. Use `identifier_name` so a
`TYPE_IDENTIFIER` token can be accepted as the package name.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Bison reports shift/reduce and reduce/reduce parser conflicts as warnings by
default. This allows parser changes to introduce new conflicts while the normal
build still succeeds.
Pass the conflict warning classes as errors to Bison when generating the
parsers. This makes the regular build fail if either parser has unresolved
conflicts.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The parameter declaration grammar allows a visible type identifier to be used
as a parameter name. The assignment continuation rule still used
`identifier_name`, which made Bison reduce a `TYPE_IDENTIFIER` before it had
seen whether following dimensions belonged to the parameter name or to an
explicit type identifier.
Match ordinary and type identifiers directly in `parameter_assign` so the
parser can shift dimensions before deciding between a parameter name and an
explicit parameter type.
Fixes: e56c93a2be ("Support shadowing type identifiers in parameter declarations")
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that UDP primitive and port names can shadow visible type identifiers.
Cover old-style UDP declarations, including input and output declarations and
the initial target, as well as ANSI-style UDP port declarations.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows a UDP primitive or UDP port declaration to use the same
name as a visible type identifier from another namespace or outer scope. The
lexer reports such names as `TYPE_IDENTIFIER` before the UDP name has been
installed, which made constructs such as:
typedef int T;
primitive T (Q, A);
output Q;
input A;
table
0 : 0;
endtable
endprimitive
fail in the UDP grammar.
UDP primitive and port names do not have the local type/name ambiguity that
exists for variable, net, or parameter declarations. Use `identifier_name` for
the primitive name, the UDP port list, UDP port declarations, and the UDP
initial target so a `TYPE_IDENTIFIER` token can be accepted as the UDP name.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that UDP initial values on non-registered outputs generate compile
errors for both old-style and ANSI-style UDP declarations. Also check that
conflicting UDP port declarations generate an error and that a valid
ANSI-style `output reg` initializer is accepted.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Malformed UDP declarations can reach `pform_make_udp()` with conflicting
duplicate port declarations or with an initial value on an output that was not
declared as a register. These cases currently trigger internal assertions
instead of reporting normal compile errors.
The ANSI-style UDP output initializer path also treats the initializer
expression as if it was the old-style `initial out = value` assignment
statement. This makes a valid `output reg out = 1'b0` initializer assert as
well.
Report errors for the invalid declarations and read the ANSI-style initializer
value directly from the initializer expression.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that enum item names can shadow visible type identifiers. Cover plain enum
items as well as the counted and ranged enum item sequence forms.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows a declaration in an inner scope to use the same name as a
type identifier from an outer scope. This also applies to enum item names. The
lexer reports such names as `TYPE_IDENTIFIER` before the enum item has been
installed, which made constructs such as:
typedef int T;
module test;
enum { T = 1 } e;
endmodule
fail in the enum item grammar.
Enum item declarations do not have the local type/name ambiguity that exists for
variable, net, or parameter declarations. The name in each `enum_name`
production is always the enum item name, including the sequence forms like
`T[2]` and `T[1:2]`. Use `identifier_name` for these names so they can shadow a
visible type identifier.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that function and task declarations can use a visible type identifier as
the declaration name. Cover both ANSI declarations and the non-ANSI forms where
the name is parsed without a separate return type or port list.
Also check class method declarations where the method name is the same as the
enclosing class name. Add GitHub issue #670 coverage for the `function void`
case using the issue-based regression naming scheme.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows a declaration in an inner scope to use the same name as a
type identifier from an outer scope. This also applies to task and function
names. The lexer reports such names as `TYPE_IDENTIFIER` before the new task or
function has been installed, which made constructs such as:
typedef int T;
module test;
function int T(input int value);
return value;
endfunction
task T;
endtask
endmodule
fail in the task and function declaration grammar. A class method with the same
name as the class itself hits the same problem because the class name is visible
as a type identifier in the class scope.
The task grammar can accept `identifier_name` directly, because a task has no
return type and the token after `task` and the optional lifetime is always the
task name.
Function declarations have a local return-type/name ambiguity. After
`function T` the parser does not know yet whether `T` is the function name with
no explicit return type, or whether a following identifier will make `T` the
explicit return type as in `function T f`. Parse the optional function return
type and function name together. This allows a `TYPE_IDENTIFIER` token to be
interpreted as the function name when no separate function name follows, while
still parsing typed forms and `void` return types correctly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that visible type identifiers can be shadowed by value parameter names
and by type parameter names. Cover ordinary parameter declarations, typed
parameter declarations, and parameter port list declarations separately.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows a visible type identifier to be shadowed by a
parameter declaration name. Parameter declarations still required the
parameter name to be an `IDENTIFIER` token and rejected declarations like:
typedef int P;
module test;
parameter int P = 1;
endmodule
The parameter grammar can not just accept `TYPE_IDENTIFIER` in every name
position. After `parameter P` the parser does not know yet whether `P` is
the parameter name, or whether a following identifier will make `P` the
parameter type.
Parse the optional value parameter type and the first parameter assignment
together. This allows a `TYPE_IDENTIFIER` token to be interpreted as the
parameter name when no explicit type is present, while still parsing a
following identifier as the parameter name for typed parameters.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that a class property can have the same name as a type declared in
an outer scope, or a type imported through a wildcard import. Also check
that a class property can have the same name as the class itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows a class property to have the same name as a visible
type. The lexer reports the visible type name as `TYPE_IDENTIFIER` before
the property has been installed, which made constructs such as
`typedef int T; class C; int T; endclass` fail in the class item grammar.
A class property with the same name as the class itself hits the same
problem. Member references such as `obj.T` or `obj.C` can also hit the
same tokenization problem in hierarchical names.
Parse class properties through the same declaration helper used for
variables so the first type/name pair can be disambiguated. Also let
hierarchical member names use `identifier_name`.
Stop type lookup when a class scope already has a property with the same
name. This makes method body references resolve as properties instead of
visible types, including type names found through wildcard imports.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that automatic variables referenced through an assignment pattern in a
procedural `force` statement are rejected.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Assignment patterns contain child expressions, but currently inherit
`PExpr::has_aa_term()` which always returns false. This means automatic
variables inside a pattern are not caught by checks for procedural `force`
and procedural continuous assignment statements.
Implement `has_aa_term()` for `PEAssignPattern` and recurse into all pattern
elements.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that the repeat count expression of a non-blocking intra-assignment
event control can reference an automatic task argument. The repeat count is
evaluated when the assignment is scheduled, so the automatic variable is not
referenced after the task scope is freed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The repeat expression of an event controlled non-blocking assignment is
evaluated once when the assignment is scheduled. This means there is no
risk of it being referenced when its scope has already been freed. And
hence there is no need to require the repeat expression to only contain
static terms.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that variable and net declaration names can shadow a visible type
identifier. Check this for explicit data type declarations, `var` declarations,
and net declarations.
Check that task and function formal argument names can shadow a visible type
identifier, and that typed arguments still use the visible typedef when an
argument name follows.
Check ambiguous module port declarations where a type identifier can be either
the port name or the port type, with and without dimensions, and that
declaration lists continue to use the type selected by the first ambiguous
declarator. Cover both ANSI and non-ANSI module port declarations.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows a declaration in an inner scope to use the same name as a
type identifier from an outer scope. The lexer reports such names as
`TYPE_IDENTIFIER` before the new declaration has been installed, which made
constructs such as `int T;`, `wire T;`, and `input T` fail when `T` was a
visible typedef.
The affected declaration forms have a local type/name/dimension ambiguity. For
example, after `input T` or `wire T` the parser does not know whether `T` is the
declared name, or whether a following identifier will make `T` the declaration
type in `input T x` or `wire T x`. With dimensions, `input T [1:0]` and
`wire T [1:0]` can be either a declaration named `T` with unpacked dimensions or
a declaration using typedef `T` as a packed type followed by another name.
Parse these declaration forms with productions that decide the first declarator
and carry the selected declaration type across the rest of the list. This covers
variable declarations, net declarations, ANSI and non-ANSI module port
declarations, and task/function port declarations. Other identifier uses still
need separate grammar changes.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that a blocking intra-assignment delay on a real value preserves the
assigned value after the delay.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The vvp parser did not accept the local flag on `.var/real`
declarations. This can happen when elaboration creates a compiler-generated
real temporary, for example when a blocking intra-assignment delay is
rewritten from:
r = #1 1.25;
to assign the right hand side to a temporary before the delay and assign
the temporary to the target after the delay.
Add support for the local flag. Keep a VPI symbol for the variable so
`%load/real` can still resolve the label, but do not attach local real
variables to the current scope.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that visible type identifiers can be shadowed by declarations in
other namespaces or nested scopes. Keep each grammar category in a
separate regression so failures identify the affected rule.
Also check that package import and export items can name a type
identifier.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows an identifier that is visible as a typedef to be
shadowed by a declaration in a nested scope or reused as a declaration
name in another namespace. The lexer can return `TYPE_IDENTIFIER` before
the new name has been installed, so these grammar positions reject
otherwise valid code.
This is not a complete conversion of all identifier grammar sites. Only
handle the trivial conflict-free cases where `IDENTIFIER` can be replaced
by `identifier_name` without any surrounding grammar changes.
Also stop type lookup when the current scope already has a local symbol
with the same name. This makes later references to a shadowing
declaration use the local symbol instead of an outer typedef.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The string substr() method reports an error if it is called with the wrong
number of arguments, but the error was not counted and elaboration continued
with missing function arguments. A call such as `s.substr(0)` could therefore
crash after printing the diagnostic.
Count the arity error and fill missing internal arguments with dummy constants
so elaboration can recover without building an incomplete system function call.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that unary real minus preserves the sign or bit pattern for zero,
NaN, and infinity. Each test starts with the positive value, negates it,
and then negates the result back to the positive value.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the vvp target emits unary real minus as `0.0 - value`.
This is not the same operation for all real values. It loses the
negative zero result for `-(+0.0)` and does not reliably flip the sign
bit for NaN values whose bits are visible through `$realtobits`.
Add `%neg/wr` and use it for unary real minus. This performs a direct
negation of the real stack value, so zero, NaN and infinity all use the
same operation as unary minus instead of a binary subtraction from zero.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that the vvp code generator emits a -0.0 real constant with its
sign bit set, so the compiled value matches the runtime real value. The
sign used to be detected with (value < 0), which is false for IEEE 754
-0.0, and a -0.0 constant was turned into +0.0.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Check that bogus member access on a procedural l-value is rejected with a
normal compile error instead of aborting during elaboration.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that an invalid indexed part select base on a procedural l-value is
reported as a normal compile error instead of crashing after the bind error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the procedural l-value path asserts if symbol lookup leaves a
member tail for a variable that is not a struct or class. For example,
`r.bad = 1'b1;` where `r` is a scalar variable aborts during elaboration
instead of reporting a normal error.
Report an error for the leftover member path before the assertion. This
matches the r-value path behavior for the same kind of invalid member access.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The l-value indexed part select path elaborates the base expression with
`elab_and_eval()`. If the base expression can not be bound this returns a
nullptr, but the l-value path dereferenced it while checking the expression
type. For example, `a[does_not_exist -: 2] = 2'b00;` reported the bind error
and then crashed.
Return early when base elaboration fails. This matches the r-value indexed
part select path and leaves the existing bind error as the reported
elaboration error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently vvp_reg.py uses `returncode >= 256` to distinguish execution
errors from ordinary compile or simulation failures. That matches the encoded
status returned by wait(), but subprocess.run() does not expose that value. Its
returncode is the decoded process exit status, or `-N` if the process was
terminated by signal N. Shell wrappers can also report signal termination as
`128 + N`.
As a result a compiler crash can be reported as `-11` or `139`. Both values
pass the old check and a CE test can be accepted as a normal compiler error.
Treat negative return codes and return codes greater than or equal to 128 as
execution errors before accepting CE and EF results. Also make sure that CE gold
mismatches are reported as failures.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The vlog95 backend currently emits `$unsigned()` when it needs to create a
self-determined unsigned expression context. `$unsigned()` is part of the
optional signed expression support in this backend and is only available when
the signed support flag is enabled.
Concatenation is part of the baseline Verilog-95 output and also creates a
self-determined unsigned expression context. Use `{expr}` for the unsigned case
and keep using `$signed()` when a signed context is needed.
Remove `-pallowsigned=1` from the existing vlog95 regression tests that now
pass without the optional signed support flag.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that synthesized case statement muxes can use array words as inputs.
This used to generate invalid VVP because .array/port statements were emitted
in the middle of .functor statements.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently draw_lpm_mux_nest() calls draw_net_input() while printing a
.functor statement. For array word inputs draw_net_input() emits an
.array/port statement as a side effect, which interleaves the .array/port
text into the middle of the .functor line and generates invalid VVP.
draw_lpm_substitute() has the same pattern. Collect the input labels before
starting to print the consuming statement so any side-effect output appears
as a separate statement first.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that a class declared in a conditional generate block can be used.
Also check that classes declared in a generate loop get separate class scopes
for each generated instance.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows class declarations as module and generate items.
Currently a class declaration in a generate block triggers an assert because
`pform_push_class_scope()` only records classes in `PScopeExtra` scopes.
Add class storage to `PGenerate` and elaborate those classes like module and
package classes. When registering task, function or class declarations, only
use the current `PGenerate` object as the target if it is also the current
lexical scope. This distinction matters for generated classes because
`pform_cur_generate` remains set while the class body is parsed, but the
current lexical scope has changed to the `PClass`. This records the class
declaration in the generate block while leaving methods and constructors in
the class scope.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that using a class task through an object method call in expression
context reports a compile/elaboration error instead of triggering an assert.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Class object method calls in expression context call func_def() without first
checking that the resolved class method is a function. If the method is a task,
func_def() triggers an assert instead of reporting a normal elaboration error.
Check the method scope type before accessing the function definition and report
an error for tasks.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently NetAssignNB::dump() prints a malformed fallback marker when
there is no rval expression. The leading '<' is missing, making it
inconsistent with the blocking assignment dump output.
Print the complete error marker.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The methods for handling up and down part select are nearly identical
and only differ in a hand full of lines.
Consolidate them into a single method to remove the duplicated code.
This makes it easier to maintain the code and add future changes.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The methods for handling up and down part select are nearly identical
and only differ in a hand full of lines.
Consolidate them into a single method to remove the duplicated code.
This makes it easier to maintain the code and add future changes.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that enum literals declared by enum typedefs in generate blocks, named
blocks, tasks and functions can be referenced from the same scope.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Enum types declared inside nested scopes are stored separately from typedefs.
The enum sets need to be elaborated when the `NetScope` is created so enum
literals are available for declarations and statements in the same scope.
Module, package and class scopes already do this. Generate, task, function and
named block scopes can also declare enum typedefs, but did not elaborate their
enum sets. Elaborate them while setting up these scopes.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The VPI label resolver parses word and string labels into a 32 byte
temporary buffer. The scansets used by sscanf() did not specify a width,
so malformed labels could write past the end of the buffer.
Limit the scansets to the size of the buffer.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that an empty old-style UDP table reports the parser error and the
invalid primitive error instead of crashing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
An empty old-style UDP table leaves the parsed table pointer unset after
the parser reports the table error. The old-style UDP creation path still
passed the null pointer to process_udp_table(), which crashes.
Report an invalid UDP table instead and do not register the primitive.
Also keep the new-style invalid-table diagnostic formatting consistent.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that variable selects of a packed array with negative bounds use the
correct index width and can read back assigned elements.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Variable select base normalization extends the base expression to cover
the packed array bounds. The current code compared min_wid against
num_bits() of each bound, but then assigned the bound value itself to
min_wid.
For positive bounds this can make the generated index expression much
wider than required. For negative bounds the effect is much worse since
min_wid is unsigned. Assigning a negative bound converts it to a huge
width, causing elaboration to try to pad the expression to that size and
abort or run out of memory for otherwise valid variable selects.
Use the bit width of the bound instead of the bound value.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that statements that are not allowed in functions or final procedures
are still rejected when they are placed in a named block scope.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently checks for statements that are not allowed in functions or final
procedures only inspect the immediate scope. If the statement is inside a
named block or a block with declarations, the current scope is the block and
the context is lost.
Make `NetScope::in_func()` and `NetScope::in_final()` preserve the context
through begin-end, fork-join and generate block scopes. Other scope types are
treated as context boundaries so function and final state does not leak across
subroutine or definition scopes.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that queue push_back(), push_front() and insert() report errors when
called with too few or too many arguments.
These tests are expected to fail as compile/elaboration errors. They also make
sure the invalid calls do not crash during elaboration while reporting the
argument count error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When a method argument is missing, the error path stores a nullptr in the
argument vector for that missing slot. The vector was sized from the number of
arguments that were present in the source, so calls such as `q.push_back()` or
`q.insert(0)` wrote those nullptr placeholders past the end of the vector.
Size the vector from the number of arguments required by the queue method
instead. This gives the error path slots for the missing arguments while
leaving valid calls unchanged.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that multi-dimensional packed vector class properties can be emitted,
assigned, and read back through a class object.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently multi-dimensional packed vector class properties will cause an
assert and only single dimensional or scalar vectors will pass.
But just as for regular vectors there is nothing special about class
property multi-dimensional vectors as they will be represented in vector
form in vvp.
Removing the asserts allows multi-dimensional packed vectors to be used for
class properties. Indexed access to these properties is not supported yet;
that requires follow-up work to elaborate packed property selects and to
support partial stores to vector class properties.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that assignment patterns are evaluated in the queue element type
context when they are passed to the queue `push_front()`, `push_back()` and
`insert()` methods.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The arguments of the queue `push_front()`, `push_back()` and `insert()`
methods are passed to subroutine input ports. This makes them
assignment-like contexts with the declared argument type as target type.
Use `elaborate_rval_expr()` instead of `elab_and_eval()` for these
arguments. This evaluates the item argument with the queue element type and
the `insert()` index argument with `integer`, so target-type-dependent
expressions such as assignment patterns work and enum compatibility checks
use the queue element type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Extend the non-blocking event control assignment tests to check that a 0 or
negative repeat value is handled correctly. In this case the assignment
should be executed like a regular non-blocking assignment and the event
control should be ignored.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`NetEvWait` deletes the event that is assigned to it when itself
is deleted. But the event is not owned by the `NetEvWait`, it is shared among
all consumers of the event. Deleting it when the `NetEvWait` is deleted can
result in undefined behavior.
This is mainly a problem for non-blocking event control assignments with a
zero or negative immediate valued repeat. In this case the `NetEvWait` will
be deleted as it is not needed.
```
reg x;
event e;
x <= repeat(1) @e 1'b0;
x <= repeat(0) @e 1'b1; // Assert triggered since in-use event is freed
```
Remove the delete to fix this. Events that end up being unused will be
freed by the nodangle functor.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This test was added to verify the new options
in the `iverilog` program, which allow it to
be run from a build directory.
Since `iverilog` is not compatible with the MSYS2
runtime environment used in CI, the added test is
excluded on this platform.
Check that continuous assignments to unpacked net arrays preserve delay and
drive strength on the generated element drivers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Continuous assignments to unpacked arrays are expanded into per-element
BUFZ drivers. Currently this path drops the delay and drive strength from
the original continuous assignment, so `assign #5 a = b` updates the array
immediately and `assign (weak1, weak0) a = b` drives with the default
strength.
Pass the evaluated delay and strength values through the unpacked array
assignment helper and apply them to each generated element driver.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Drive strengths and delays are often handled as a pair of drive values
and a rise/fall/decay triple. Add small helper types to carry these
groups and use them in the continuous assignment and gate/UDP elaboration
paths.
Use the same helper types when propagating drive and delay values through
netlist links.
Also add helpers for dumping the values in debug output. This keeps the
behavior consistent and fixes one small bug where some of the debug
dumps printed the pointer value for the delays, rather than the actual
delay values.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that SystemVerilog net declarations can mix entries with and
without initialization.
Check that in SystemVerilog it is possible to do assignments within net array
declarations.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`pform_set_data_type()` is now only called on wires that already have the
correct wire type set. There is no need to pass the same type to
`pform_set_data_type()` and set it again.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows initialized and uninitialized net declaration entries to
be mixed in the same declaration, e.g. `wire x, y = 1'b1`. In Verilog,
either all nets need to have an initializer or non can have one.
In addition SystemVerilog also allows assignments to arrays of wires during
declaration. E.g. `wire a[3:0] = b;`
Currently there are two different rules for net declarations, one for each
of the Verilog variants. Combine these into a single rule to support
SystemVerilog mixed declarations as well as the assignment to array nets.
When running in Verilog mode still reject mixed initialized and
uninitialized with a check after the parsing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The assignment handling block uses space-based indentation that does not match
the surrounding code.
Fix the indentation before changing the block.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that continuous assignment of an assignment pattern to a single element
unpacked array is accepted. Check that assigning a scalar expression to the
whole unpacked array is rejected for both procedural and continuous
assignments.
Check that a selected element of a single element static unpacked array can be
used in a continuous l-value concatenation.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently single element static unpacked arrays are not always treated as
unpacked arrays when elaborating assignment l-values. The net only has one pin,
so checks using `pin_count() > 1` treat the array as a scalar value and skip
the unpacked array path.
Use `unpacked_dimensions() > 0` instead of `pin_count() > 1` when checking
whether a signal is an unpacked array. This lets single element arrays follow
the same l-value elaboration paths as other unpacked arrays.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that enum, struct, union and class restricted type parameters are
accepted. Check that mismatched default values and overrides are rejected.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog 2023 allows type parameters to be restricted to a
specific kind of type, e.g. `parameter type struct T = T0`.
This is very similar to the type restrictions that can be applied to
forward typedefs.
Factor the support code from the typedefs into a standalone helper and
reuse it for both.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that soft packed unions can have members with different widths.
Check that the `soft` qualifier implies `packed` and that nested soft
packed unions use the same representation recursively.
Also check that member bits are right-justified and that assignments to
narrower members leave the MSBs beyond the member bits unchanged. Check
that soft packed unions reject default member values.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog 2023 adds soft packed unions. They are pretty much the same
as regular packed unions except they remove the restriction that all
elements have to have the same packed width.
The packed with of the union itself is the maximum packed width of any
element.
The bits of each member are right-justified towards the LSBs and this
representation is applied recursively to nested soft packed unions. The
existing packed union member offsets already use that layout. When
accessing a field that is smaller than the union itself upper bits are
ignored for both reading and writing.
The `soft` qualifier implies a packed union so both `union soft U { ... }`
and `union soft packed U { ... }` declare a soft packed union.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that each valid `begin_keywords` selector is accepted. Only check
that the selector itself is accepted, in these tests there is no check if
the correct keywords are actually accepted or rejected since that would get
pretty exhaustive.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add flags to enable IEEE1800-2017 and IEEE1800-2023 languages generations
and also support them in the `begin_keywords macro. Since neither defines
new keywords they'll use the same keyword mask as 2012.
Update the driver, compiler, documentation and regression test harness so
-g2017 and -g2023 are recognized as language generation flags.
There are no specific features from these versions added yet, this is just
the necessary infrastructure to allow gating new features from those
generations when they are added later.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
A few JSON regression test entries reference the wrong source or gold
files. There are also two regress-vvp list entries that reference each
other's JSON file.
Use the matching source and gold files for those entries.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The sv_mixed_assign2 JSON entry accidentally references
sv_mixed_assign1.v. Point it at sv_mixed_assign2.v instead.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that class objects, dynamic arrays, queues, strings and static
unpacked arrays can not be used as l-value concatenation operands. Check
procedural and continuous assignment concatenations, including single
operand concatenations.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
L-value concatenation operands must be packed values. Using an unpacked
array, string, class object or other non-packed value as an operand can
reach later assignment code with an invalid l-value representation.
Check the operand type after l-value elaboration and report an
elaboration error instead.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`%cmp/e` and `%cmp/u` are very similar with `%cmp/e` not setting the lt
flag and being a bit faster due to it. For case comparisons the flag is not
needed so switch to `%cmp/e`. This speeds up simulation time designs which
make use of case comparisons.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The parser union still has a few fields that are not used by any
grammar rule. They do not have matching semantic type tags and no
action references them.
Remove the unused fields.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
It uses a dedicated LIBVVP_SOVERSION specified in onfigure.ac
for the SONAME and full library version.
For linking, a pkg-config file is generated, and when building on
Windows, an import library is created that can be used with both
GCC and MSVC compilers.
On non-Windows platforms, all object files are compiled with -fPIC
to ensure compatibility with shared libraries.
On Windows use 'lib' prefix for library name with MinGW compiler
only. Other compiler like MSVC normally are not using any library
prefix.
With this commit the build rules for the vpp executable has been
cleaned too because the complex structure of the manually created
Makefile.in made it very difficult to extract specific parts of
them.
The `super` keyword refers to the parent class of the current class. If the
class has no parent the lookup still returned the current class handle and left
the `super` path component for l-value elaboration. This triggered the
`tail_path.empty()` assert.
Report an error during symbol lookup instead.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that the compiler reports an error for `posedge`, `negedge` and `edge`
event controls on named events. Edge controls can not be used with named
events.
There is already an existing test that checks both `posedge` and `negedge`.
Split it into separate tests so that each invalid event control is checked
independently.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Using an edge control with a named event is invalid. The existing elaboration
code already reports an error for `posedge` and `negedge`, but the `edge` case
falls through to the default path and triggers an assert.
Handle `PEEvent::EDGE` like the other edge-control cases and report the same
kind of error instead.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
- change documentation theme from `alabaster` to `shibuya`
- add pinned Documentation requirements for `sphinx` and `shibuya`
- update workflows to create `.venv` and install with `requirements.txt`
- ignore common virtual environment directories (`.conda` and `.venv`)
Since this file, just like 'config.h', is generated by autoconf,
it should only be deleted in the `distclean` target.
Also since the project does not currently use automake, manual
maintenance of the timestamp file for 'version_base.h' is required.
Fixup for commit 10b5f70e7 from #1331
Array indices must be integral expressions. Using a real valued expression
as an unpacked array index currently reaches the vvp real expression code
and triggers an assert.
Packed bit and part select indices already report an elaboration error for
real expressions since commit 2249d224de ("Bit/part selects cannot have
real index expressions"). Do the same for unpacked array indices.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
here are two separate paths `PENewArray::elaborate_expr()`, one for
assignment patterns and one for everything else.
But since since commit 5ca058bfb ("Add support for darray initialisation
from another darray"). The two paths have been effectively the same.
Both call `elaborate_expr()` on the init values with the same parameters.
The only difference is the regular path casts the type to `netarray_t`, but
that doesn't really do anything since it gets passed to a function that
takes a `ivl_type_t`, so is immediately cast back to the base type.
The comment on the regular path is also outdated since it still refers to
the tpre 5ca058bfb code.
Remove the branching and route it through the same path.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`PEIdent::test_width_parameter_()` has a special case for
`NetEConstEnum` that queries the enum base type directly. This was needed
when enum constants kept their enum type separately from the `NetExpr`
type.
Commit f63a162329 ("Provide data type for more NetExpr subclasses") made
`NetEConstEnum` attach the enum type to the `NetExpr`. The generic
parameter width path now gets the same type, width and signedness as the
special case.
Remove the redundant special case and use the common path for enum
constants as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that package variables can use explicit static lifetime. Check that
automatic lifetime is rejected for package variables.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The LRM allows to add a lifetime specified for variables declared in
package scope. It is not particular useful since only static lifetime is
allowed. But it is legal syntax, so support it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The vvp reduction operators evaluate their input bit by bit. This is
expensive for wide vectors.
Add word wide reduction helpers to `vvp_vector4_t` and use them for both
reduction functors and vthread reduction opcodes.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that string literals can be assigned to byte arrays. Check that
invalid target array types are reported as errors.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The logic functors combine their input vectors bit by bit.
Use the in-place `vvp_vector4_t` operators for the vector operation and
invert the result once for the inverted functors.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The vthread binary logic opcodes update vectors bit by bit.
Use the in-place `vvp_vector4_t` operators instead. This reuses the word
wide implementation and avoids per-bit `value()` and `set_bit()` calls.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`vvp_vector4_t` has word wide in-place operators for and and or, but not
for xor.
Add `operator ^=` using the same internal word representation.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog defines a special case that allows to assign string literals
to byte arrays. Each character of the string is copied to 1 element of the
byte array.
The size of string literal and the byte array does not have to match. If
the string literal is longer it is truncated. If it is shorter it will be
padded with null-bytes.
The assignment is done left aligned, the first character ends up in the
left most entry of the array. This means the order will differ whether the
array is declared with ascending or descending element order.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Output port expressions must support continuous assignment. Assignment
patterns for unpacked array output ports are currently elaborated as
temporary arrays and the connection is silently discarded.
Report an error instead.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that drive strength can be specified between the net type and the
data type in a net declaration and that vector gate arrays resolve
strengths correctly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The drive strength of a net must be declared between the net type and the data type. E.g.
wire (weak0, strong1) [7:0] x;
The current implementation expects the drive strength after the data type. Update the parser to fix this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This change standardizes the creation of iverilog-vpi-related
targets, which now follow the same pattern as the iverilog targets
in the 'driver' subdirectory.
Replace .github/test.sh with a unified set of targets installed
via `make check-*` in ivtest/, thereby removing CI-specific test
coordination. This avoids duplication in the regression logic and
ensures consistent execution between local and CI environments.
PLI1-dependent tests are now correctly controlled via
`configure --enable-libveriuser`.
Currently, the regression suite still depends on an iverilog package,
which must be installed manually at the location specified with
`configure --prefix=*`. Afterward, the complete regression suite
(VVP, VPI, and Python tests) can be run via `make check-installed`
and individual checks can be run with `check-installed-vpi`,
`check-installed-vvp` and `check-installed-vvp-py`.
When running `make check` on a UNIX-like operating system
with the specified `configure` option, `vvp` was unable to
find the required shared library.
This commit ensures that the runtime linker can locate the library.
This fixes issue #1313.
macro_start_args() inserts a null string for arg 0 at the start of def_buf.
This allows macro_finish_arg() to calculate the length of the first actual
argument (arg 1). But macro_start_args() relied on def_buf having already
been allocated, which isn't the case when all the macros are pre-defined.
This fixes issue #1323.
driver/main.c uses _NSGetExecutablePath in the __APPLE__ code path
but does not include the header that declares it, causing a build
failure on macOS.
Signed-off-by: Huang Rui <vowstar@gmail.com>
The new option allows parameter, net and events to be used before
declaration. With variants
-gno-strict-net-declaration for nets and events,
-gno-strict-parameter-declaration for parameters.
With `-ggno-strict-parameter-declaration` a warning is issued for
parameter use before declaration. This warning suppressed with
the new class `-Wno-declaration-after-use`, instead of `-Wno-anachronisms`.
The standards requires that parameters must be declared
before they are used. Using -gno-strict-parameter-declaration
will allow using a parameter before declaration, e.g., in a port
declaration, with the parameter declared in the body of the
module. Prior to version 13 this was allowed, so there is a large body
of existing code depending on the pre version 13 behaviour.
The vvp/ivl_dlfcn.h and cadpli/ivl_dlfcn.h files are essentially the
same, but have diverged a bit over the years. Merge them into a single
shared file at the top level. Use the static prefix for all inline
functins (currently only used in the cadpli version) as that will fix
issue #1301. We now require the compiler to support at least C99, so
can use "inline", not "__inline__".
Currently, when a constant bit/part select is found in the implicit
sensitivity list for an always_* construct, it is replaced by the
entire signal. If there is more than one bit/part select from the
same signal, that signal gets added to the list multiple times. This
breaks the algorithm used to detect duplicate events in the nodangle
functor, causing it to erroneously merge non-identical events in some
cases.
The proper fix is to support sensitivity at the bit/part level, as
required by IEEE 1800. But for now, just make sure we only include
the entire signal once, regardless of how many different bit/part
selects we find. Enhance the "sorry" message to report which signals
are contributing excessively to the process sensitivity.
Also allow extra configuration options to be passed via the
IVL_CONFIG_OPTIONS environment variable and add some missing
dependencies. Don't include --enable-libveriuser by default.
Update the README accordingly, with sensible line wrapping.
This version works with the native Windows (mingw64 and clang64)
versions of Perl in MSYS2.
Note that warnings are disabled in the Environment.pm module because
Perl fails to notice that OLDOUT and OLDERR are used when restoring
the STDOUT and STDERR file handles.
When the argument is a literal string, tf_getp returns a pointer to
the string. But the return type is a PLI_INT32, so on machines where
pointers are larger than 32 bits, the pointer value may get truncated.
Check for this at run time, and if it occurs, print a warning and
return 0.
PLI 1 was deprecated in 1364-2005, so disable by default and note that
it is deprecated in the help text.
This works round the problem that the clang linker (lld) in MSYS2 does
not support the -r option, so cannot be used to build libveriuser.a.
The clang dlltool is not compatible with the binutils dlltool. However
both the clang and binutils linkers support reading the .def file and
creating the import library directly, so we no longer need to perform
the link in two stages.
When redirection operators are included in a command string passed to
the system() subroutine, it spawns an intermediate shell to handle the
redirection. This is particularly inefficient when running the tests
in MSYS2. Creating our own version of system() based on fork() and
exec() allows us to handle the redirection directly.
We need to build libvvp with a suffix from the outset to ensure that
the vvp binary searches for the correct library file name once it is
installed.
Also Windows DLLs need to be stored in the same directory as the main
program, not in a separate lib directory.
Commit 95810b2f61 mistakenly added the suffix to the output file name
when linking the final vvp.exe binary. 'make check' and 'make install'
assume the suffix is only added when installing.
The tgt-vvp code generatpr outputs identifiers as quoted strings, and
because of this, escapes any " and \ characters (which may appear in
escaped indentifiers). We need to undo this when reading them into
vvp, so that the original name is seen by the VPI routines.
These were implemented as returning nothing (void), and passing an
invalid operation value would trigger an assertion failure. The IEEE
standards define them as returning 1 on success and 0 on failure.
vpi_sim_control() is the name used in Verilog-AMS. Strictly speaking
it should return a bool, but to avoid polluting the namespace by
including stdbool.h, we return a PLI_INT32. As C is a weakly typed
language, this should make no practical difference.
The existing elaboration code only allowed assignments from/to individual
elements and either failed an assertion (when assigning the entire array)
or failed to compile (when assigning an array slice).
Improve path search between nets, so that paths containing
concats as well as part selects can be found.
Signed-off-by: Michael Kupfer <michael.kupfer@fau.de>
Only vector types can be cast to real. Report an error when trying to cast
a different type instead of triggering an assert later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently nested lvalues are only supported for vector typed properties.
Refactor the code to also support other types.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently assignment operators on queues and dynamic elements trigger an
assert.
Add support for handling this properly. Since the operation for loading an
element for an queue or dynamic array is identical most of the code can be
shared, only writing back the value has to be handled separately.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently assignment operators on object properties are silently
ignored. Make sure that they are handled.
To enable this refactor the code a bit so that the assignment
operator handling can be shared between object property assignments
and scalar value assignments.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Logic type class properties use the wrong constructor resulting in a
default value of a vector with 0 width. Switch to the right constructor to
fix this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Then temporarily add the resulting configure and lexor_keywords.cc
files to the repository so they will be included in the snapshot and
release tarballs that are automatically generated by GitHub. Remove
these files in the post-snapshot/post-release cleanup.
The old MAKE_SNAPSHOT.sh and MAKE_RELEASE.sh scripts created tarballs
that could be uploaded to icarus.com and SourceForge. Now we release
on GitHub, we need to make all the necessary changes in the git
repository, temporarily creating a release_tag.h file and deleting it
after we have created the snapshot or release tag. This allows GitHub
to automatically generate the tarballs for us.
Now we publish releases on GitHub, we need to commit the file to the
repository when making a snapshot or release, so we need to use a
different filename to the one that is automatically generated by
'git describe' (which we still want git to ignore).
Remove implicit casts between vector and real in tgt-vvp. These are not
required since any implicit cast in the source will be converted to an
explicit cast in the elaboration stage.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The code doesn't currently handle the case of different bits within
the vector needing different delays (e.g. when the rise and fall
delays are different and some bits are rising as other bits are
falling) and aborts with an assertion failure. For now, output a
suitable "sorry" message and exit gracefully.
Although the introductory paragraph seems clear enough, add a reminder
at the start of the section on extended arguments that they must appear
after the input file name.
This adds a "-q" option on the vvp command line and a vvp_set_quiet_flag()
function in the VVP library API. Setting this flag will cause all output
to standard output via MCD bit 0 to be suppressed. It will not prevent the
output being sent to a log file if the vvp "-l" option has been used, and
it will not affect output to the STDOUT file descriptor.
Newer version of the linker on MacOS provide a deprecation warning when
using the `-undefined` flag with the `suppress` value. This is cause CI to
fail to do logs not matching when building VPI modules.
Switch to using the `dynamic_lookup` value for the flag instead, which
resolves the warning and is the behavior we want when loading the module.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The vlog95 code generator collects all the constant assignments to a net
within each scope and then emits them. The old code only recorded the
ivl_signal_t for each constant assignment, which meant it had to iterate
through the nexus pointers in the assicated nexus to find the constant.
When there were multiple constant assignments to the same net, it needed
to record which assignments had already been emitted, which it did by
keeping a count in the nexus private data and skipping that many constants
on each successive assignment. However the count did not get reset after
emitting all the assignments in that scope, so if there were assignments
to the same net made in another scope, the count would already be positive
and those assignments would also be skipped.
This could probably have been fixed by clearing the nexus private data
after processing the constant assignment list for each scope, but it is
more efficient to record the ivl_nexus_ptr_t for each constant along with
the ivl_signal_t, eliminating the need to search for the associated nexus
pointer.
Internally, the maximum address space of a vector is 31 bits + a sign bit
to signal invalid addresses (out of bounds or has one or more x or z bits).
This commit ensures that unsigned part-select bit addresses which would
otherwise overflow and wrap around within this address space are correctly
handled as out of bounds.
The for loop initialisation statement, termination condition, and step
statement were only made optional in IEEE 1800-2012. Commit 0695c1fe
enforced this. So we need to compile with -g2012. The vlog95 code
generator doesn't currently translate this, so the tests will fail
when compiling the translated code.
Early editions of the SystemVerilog standard did not specify the return
type for $bits, so we made it 32 bit unsigned 2-state. Later editions
state the return type is integer (32 bit signed 4-state), so make it so.
When multiple words in one array were connected to the same nexus as a
single word array, the code generator was sometimes failing to generate
all the necessary aliases. This was highly dependent on the elaboration
order.
This fix should be more robust, but there are currently no tests in the
test suite that cause the compiler to generate whole-array aliases, and
I can't think of a way to make it do so as we don't yet support unpacked
arrays in module ports, so that branch of the code is currently untested.
Add a regression test to check that the right-hand side of a shift
operation is always treated as unsigned, even if it is a signed registers
or a variation thereof.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When loading a signal into into an index register currently the signedness
of the signal is used when deciding whether sign-extension should be
performed or not. But this can lead to incorrect results, instead the
signedness of the expression must be used as that might be different from
the signal. E.g.
```
reg signed [1:0] = 2'b10;
$display(1 << x[1:0]);
```
gives the wrong result without this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that assignments with undefined intra-assignment delay get executed
with zero delay. The assignment should not be skipped.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Assignments with an undefined intra-assignment delay should be treated like
assignments with zero delay. For the most part this is implemented
correctly, except for assignments to a part of a vector where the offset
inside the vector is an immediate value. E.g.
```
reg [1:0] x;
integer d = 'x;
...
x[0] <= #d 1'b1
```
Here when loading the delay into the index register flag 4 is updated, but
never cleared afterwards. As a result, if the delay is undefined, the vector
assignment will be skipped. Fix this by making sure flag 4 is always
cleared before the vector assignment instruction.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For sequences where the tgt-vvp backend generates `%pushi` followed by one
of the operations that have an immediate version replace it with the
immediate version. This is slightly more efficient.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
As discussed in issue #1143, the for loop initialisation statement,
termination condition, and step statement were only made optional in
IEEE 1800-2012. So check all three are present when compiling for
ealier generations.
SystemVerilog makes all of the initialisation, condition, and step
components of a for loop optional. We already support this for the
initialisation and step components.
A constant function call may be inside a named block, so we need to
search upwards to find the enclosing module before checking that the
called function is local to that module.
SystemVerilog allows constant function calls to reference functions
in (other) packages or in the $unit scope, so extend the checks to
permit that.
Update the versions of called Actions to prevent warnings.hi and add
"workflow_dispatch" to allow testing.
Unrelated: add "*.so" to .gitignore to hide built libvvp.so.
The tran island resolution tests and caches the state of all branch
enable inputs before resolving the branch endpoint values. If a
branch enable is connected directly to a branch endpoint, we need
to update the cached stete and rerun the island resolution if any
enable state changed.
This fixes issue #1122.
If a net or variable is referenced in another net or variable declaration
or in a value parameter definition (e.g. when using the $bits function)
and hasn't already been elaborated, we need to elaborate it early. So
during the scope elaboration phase, add placeholders in each NetScope
object to record the PWire objects that are yet to be elaborated. This
allows the symbol_search() function to find the unelaborated objects
and to trigger early elaboration.
Add a flag in the PWire object to indicate when we are elaborating it.
This allows us to detect circular references and avoid an infinite loop.
This fixes issue #483, issue #575, and issue #1097.
If a signal has been cast to a different type, synthesis needs to
reflect the expression type, not the base signal type.
If a part select selects the entire signal, unless otherwise cast,
the expression is unsigned, regardless of the base signal type.
This fixes the additional issues reported in issue #1099.
Most pre-processor errors are flagged to the main compiler by a comment
at the end of the pre-processed output. But certain errors, such as
failing to find or open an include file, cause the pre-processor to
exit immediately, which bypassed the generation of that comment. So
we need to also generate that comment for all early-exit cases.
This fixes issue #1104.
When there is only one operand, we elide the concatenation during
expression synthesis. But if that operand is signed, we need to
insert an intermediate local signel to cast it to unsigned.
This fixes issue #1099.
This only applies to simple identifiers. Only return a match if the
lexical position of the identifier being searched is later in the
source text than the lexical position of a matching symbol.
Enhance the lists of identifiers and declaration assignments generated
by the parser to associate each identifier with its lexical_pos. Also do
this for single items in complex parser rules where the location passed
to the pform is not the location of the identifier.
This is needed for detecting use before declaration. The lexical scanner
is the only place where we process the source text in strict lexical
order, so do it there.
As Verilog allows modules to span multiple source files, don't reset
the counter when we reset the lexor.
cb_data.obj must be set to a valid handle when requesting vpiScaledRealTime.
Check the returned time value as well as the actual callback time. Zero
the requested cb_data after registering the callbacks to make sure it
is not used during the callback execution.
NOTE: This removes the ability to request vpiSuppressTime for the
simulation time callbacks (other than cbNextSimTime). Requesting
this is clearly stated to be an error in IEEE 1364-2001 onwards.
IEEE 1364-1995 has different wording to later versions of the standard,
stating "For reason cbNextSimTime, the time structure is ignored." So
it's possible old VPI code might not pass a valid time pointer or time
structure. So remove the checks that the time pointer is non-null and
that the time type is not vpiSuppressTime.
To allow a user to select the time type, we have to assume that if
the time pointer is non-null, it is a valid pointer and not just an
uninitialised field.
When registering a cbReadWriteSynch or cbReadOnlySynch callback,
the time type must be either vpiSimTime or vpiScaledRealTime.
vpiSuppressTime is illegal. The required behaviour is a delay of
zero, so use vpiSimTime with the high and low fields set to 0.
The old code only worked for VPI objects that represented variables
and nets. For simulation time callbacks, the user might pass an
object that represents a scope.
This adds support for vpiScaledRealTime in various callbacks where it
wasn't previously supported. However this doesn't work properly when
the cb_data.obj field references a scope handle.
Previously they were reusing the pointer supplied when the callback
was registered, which is not guaranteed to still be valid.
Note that the IEEE standard states:
The only fields in the s_cb_data structure that shall need to
be set up for simulation action or feature callbacks are the
reason, cb_rtn, and user_data (if desired) fields.
so for cbEndOfSimulation callbacks we cannot rely on the time pointer
being either valid or null. The standard does not require that the
time structure should be filled in when the callback occurs, but for
backwards compatibility continue to do so, returning a vpiSimTime
value.
Fill out cb_data.time and require it is non-NULL.
Record the last NextSimTime CB so we don't call CBs added during this timestep.
(cherry picked from PR #740)
If we have a variable which is part driven by a continuous assignment,
the parts that are not driven by that assignment can be the target of
more than one procedural assignment. So we need to only test the cassign
mask, not test and set it, when elaborating the procedural assignments.
This is legal if the procedural and continuous assignments target
different words.
NOTE: This is not fully compliant with the standard, because vvp
does not know that the nets were originally declared as variables,
so initialises to 'bz instead of 'bx and does not handle release
correctly.
We have already eliminated procedural assignments to uwires, so if
we find a l-value of type UNRESOLVED_WIRE, it must be a variable
that has a continuous assignment. Report it as such.
A uwire is never a valid l-value for a procedural assignment (other
than a force/release), so catch that error as soon as we can. We
then know that any remaining l-values with type UNRESOLVED_WIRE must
be variables which have been coerced by a continuous assignment.
Internally we convert SystemVerilog variables that have a continuous
assignment into unresolved wires. But from a user's perspective they
are still variables, so we should refer to them as such in error
messages. This new flag lets us distinguish between such variables
and nets that were declared as uwires.
SystemVerilog allows variables to be driven by continuous assignments,
including port connections. Internally we handle this by converting
the NetNet from a REG to an UNRESOLVED_WIRE. Here we handle the case
of an unpacked array variable connected to a module output port.
This fixes issue #1001.
This test uses 'wire real' but specified the '-gno-xtypes' option.
This is because it named a variable 'wreal' which is a keyword when
that option is enabled.
When using the Icarus extension for wire types, only logic (4-state)
wires may have multiple drivers (as documented in extensions.rst).
Other types of wire should be treated as unresolved wires.
When the Icarus extension is disabled, only 4-state wires are
allowed (IEEE 1800-2017 section 6.7.1).
Whilst the wording in the IEEE standards is ambiguous, discussions on
the standards committee mailing lists clarify that an unsized literal is
supposed to be the same size as an integer (as shown in IEEE 1364-2005
table 5-22). The token following the base format character is specified
to be an unsized number. So to maintain compatibility with the standards
and with other tools, if the unsigned number part of an unsized signed
based literal can be represented in less than integer_width bits and the
MSB is a '1', we need to add a leading zero to ensure it is zero-extended
when used in an expression.
This fixes issue #1082.
Arguably this should be done in the target code generator, as the code
generator can infer the value for undriven bits from the net type. But
in practice it is quite hard to do this in the vvp code generator. So
adapt the cprop functor that concatenates part selects to do this as
well.
This fixes issue #1047 and issue #1083.
When driving a 2-state net, any undriven bits in the concatenation
of part selects should be driven to '0', not 'z'. This saves having
to cast the result.
This removes the regress-msys2.list file, fixes the output from the
pr2509349a.v test to not be different on different systems, and
documents the $readmempath task.
This file contained some SystemVerilog tests that are not yet supported.
Move the tests to the regress-vvp.list format, and mark them as NI so
that we know what's going on.
A concat typically has multiple inputs. Whenever one of the input values
change the output value of the concat is updated and propagated to its
downstream consumers.
When multiple inputs change within the same cycle each input will cause a
update propagation. Depending of the overall structure of the design this
can cause a significant performance penalty.
E.g. the following synthetic structure has a exponential runtime increase
based on the value of N.
```
reg [N-1:0] x;
generate for (genvar i = 0; i < N - 1; i++)
assign x[i+1] = ^{x[i],x[i]};
endgenerate
```
To improve this defer the value propagation of the concat to the end of the
current cycle, this allows multiple input updates to be included in a
single output update.
For the example in report #1052 this reduced the runtime from 2 minutes to
essentially 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The concat functors use individual bit access to initialize and copy
values.
For initialization pass the initial bit value to the constructor and for
coping use set_vec() instead. Both can be a fair bit faster since data is
copied word by word rather than bit by bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The implementation for partial receive for concat only differs from the
regular receive in that it takes an additional offset.
The regular receive can easily be implemented by calling the partial
receive with an offset of 0. This allows to remove some duplicated code.
The overhead of this is negligible, but to help the compiler to optimize this
a bit better mark the `recv_vec()` and `recv_vec_pv()` functions as final.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The pr1002 test has a always block with the `dataout` in its sensitivity
list. It compares `dataout` to `expected_dataout`.
Both `dataout` and `expected_dataout` depend on `datain` and are updated in
the same cycle. This means there is no guarantee in which order they are
updated and the always block might get scheduled before `expected_dataout`
has been updated. This can lead to a test failure.
To avoid this slightly change the test to use a task to perform the
comparison and add an explicit delay before the task is executed so that
all updates have a chance to be fully resolved
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The first evaluation of an `assign` statement is scheduled at the same time as
`initial` statements.
There are some test cases that evaluate the result of an `assign` statement
in an `initial` statement. This is an inherent race condition and might
fail depending on the exact order of evaluation.
To fix this add an additional delay in the `initial` block. This will make
sure that all `assign` statements get fully resolved first.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`IVCXX` which contains the C++ compiler that will be invoked when building
an vpi module might contain additional arguments that get passed to the
compiler. E.g. such as the C++ version (`-std=c++11`). For this to work
properly `IVCXX` needs to be put in quotes.
This fixes intermittent CI failures for the MacOS target.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
To escape the `.` in the regex it needs to be prefixed with a `\`. But
since the `\` is a escape character in python strings it needs to be
escaped as well.
Without this some versions of python print the following warning:
run_ivl.py:36: SyntaxWarning: invalid escape sequence '\.'
match= re.search(b'Icarus Verilog version ([0-9]+)\.([0-9]+)', text)
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Before the start of simulation, functor update events resulting from
initial value propagation are added to the initialisation event queue
(schedule_init_list). Once simulation has started, they are added to
the main event queue (sched_list). The cbStartOfSimulation callbacks
are executed after the initialisation event queue has been emptied.
Currently, if these callbacks generate further functor update events,
those events are added to the initialisation event queue, but that
queue is not looked at again. Instead, make sure any new events are
added to the main event queue.
This issue and proposed fix was reported by gatk555 in PR #1065.
Starting with commit 96df251c95 ("Suppress unnecessary VCD/LXT/LXT2
warnings about packages.") there is no longer a warning printed that the
unit scope can't be printed if it is empty.
Remove the special SystemVerilog mode gold file for the pr1963962 test that
expects this warning.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The part functor has no real typed state and the bitsr field of the state
struct is unused. Remove it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Only output a warning if a package contains dumpable items. This is
mainly to avoid the warning about the $unit scope when a design has
been compiled for a SV generation (issue #710).
The condition expression may require the loop variable width to be
expanded. The compiler wraps the NetESignal with a NetESelect to
do this, so we need to handle that when checking that the condition
expression uses the loop variable.
Fixes issue #687 and issue #1004.
This causes tgt-vvp to use a lower case 'c' instead of an upper case
'C' as the prefix for constant values used to initialise undriven nets.
For use by the following commit.
vvp_net_ptr_t uses vvp_sub_pointer_t to implement a tagged pointer with the
tag containing the port number.
The size of the tagged pointer is that of a normal pointer and could easily
be passed in a register when passing it as an argument to a function.
But since the vvp_sub_pointer_t type has a non-standard destructor it is
instead passed on the stack with the register containing a pointer to the
stack location where the value is stored.
This creates extra boiler plate code when passing a vvp_net_ptr_t to a
function writing and reading the value to and from the stack.
Use the default destructor for vvp_sub_pointer_t to avoid this and have the
value passed in a register.
There isn't much of a performance gain but the change is simple enough to
do anyway.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently replication in a concatenation is implemented by simply
concatenating the input signals multiple times by the replication amount.
Replace this to use NetReplicate on the concatenation instead. In case
there is only one input vector to the concatenation the replication will directly
connect to the input vector.
This is slightly more efficient in vvp since the replication functor has
only one input while the concatenation has multiple inputs connected to the
same wire. When an update of the input occurs the replication functor will
only receive a single update, while the concatenation will receive multiple
update events, one for each replication.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The repeat functor can receive a partial vector. Make sure this is handled.
Since the expectation is that will only happen if the input wire is driven
by a single partial selection the default recv_vec4_pv_() can be used which
replaces the missing bits by `z`.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The current `PEIdent::test_width()` method is only able to calculate width
of a path with up to two elements.
For more complex paths it will not be able to calculate the width. E.g.
* Nested struct member access
* function call of a enum member in a struct
To make nested structures work properly walk the whole path tail element
by element updating the type along the way. Also take the indices into
account and update the type if an arrays dimensions have been fully
consumed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that reversed part selects result in an error. Check this for both
right-hand and left-hand side expressions as well as for inner and outer
dimensions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The order of the indices of a part select need to match the order in which
the dimension of a packed array has been declared. E.g. if the msb is less
than the lsb in the declaration it also has to be for the part select.
If the order of the part select is the opposite of the declaration this is
an error. This works as expected for part selects on the most outer
dimensions.
But for inner dimensions the current implementation just swaps the msb and
lsb of the part select if they are in the wrong order.
Refactor this so that an error is reported for both the outer and inner
dimensions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
An initial value propagation should only be scheduled for variable array
ports, but not for net array port since those do not contain any values.
This got accidentally broken when fixing support for 2-state variable
array ports.
Add a check that only does the initial value propagation if the port is for
a variable array.
Fixes: 0eb01fff1e ("vvp: Fix initial value propagation for 2-state non-automatic arrays")
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The elaboration of the base expression of a vector slice index can fail and
return a nullptr. Currently this results in a nullptr deref. Handle that
case by exiting the function early.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Commit 56c5bf1da1 ("ivtest: Remove regress v11, v12, and v13") removed the
`expected_fail` argument from the `check_run_outputs()` function, but did
not remove all references. This causes the run_ivl.py script to fail. The
script is part of the CI pipeline and causes all PRs to fail.
Remove the remaining references to `expected_fail` to make it work again.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
find_scope() requires the hierarchical path to use escaped identifiers;
without the leading '\' and trailing ' ', if there are any '.' characters,
the path will be broken up at the wrong point(s).
vvp is missing a parser rule for unsigned 2-state net arrays. E.g.
```
bit a[0:1];
assign a[0] = 1'b0;
```
will synthesize fine, but when running it with vvp cause a syntax error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Now that out-of-bounds access on 2-state queues and dynamic arrays yields
the right value move the tests from the "Not Implemented" list to the list
of tests that get run.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
vvp does not track whether the values stored in a dynamic array or queue
are 2-state or 4-state. Internally the data is always stored as 4-state.
To make sure that the read value is actually 2-state do a cast for 2-state
reads.
E.g. performing an out-of-bounds access on a 2-state dynamic array or queue
will yield a undefined value.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The sv_queue_vec test uses queues of 2-state vectors, but also checks if
certain operations on the queue yield 'X.
2-state queues should never yield 'X and the test only passes because of a
bug. In preparation for fixing the bug change the test to use a 4-state
base type instead.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For 2-state non-automatic arrays currently real 0.0 value is propagated as
the initial value. This will cause an assert at the downstream receivers
which expect a vector.
Make sure that the vector value 0 is propagated instead for 2-state
vectors.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Most places in the code use a std::vector for array dimensions.
The only exception is the constructor of NetNet, which uses
a `std::list` to pass the unpacked dimensions. But to store the
unpacked dimensions it also uses a `std::vector`.
There does not seem to be a good reason why the constructor
has to take a `std::list`, so switch it also to `std::vector`.
This allows to simplify the code and remove some special handling
for `std::list<netrange_t>`.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`std::vector<netrange_t>` is used for signal array dimensions. As such it is
used in quite a few places.
Add a typedef that can be used as a shorthand to refer to it. This helps to
keep lines where this is used from growing to overly long.
The new type is called `netranges_t`.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are two `NetNet` constructors, one for arrays and one for non-arrays.
There are a few places where the array constructor is used for non-arrays,
but with an empty unpacked dimensions list. Switch this over to using the
non-array constructor.
This slightly reduces boiler-plate code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `netrange_width()` helper function computes the total width of a set of
ranges. There are a few places where this is currently open-coded and
`netrange_width()` can be used. This removes a bit of duplicated code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are sometimes cases where calculating the total width of a
`vector<netrange_t>` has to take into account an existing base width. E.g.
when chaining multiple `vector<netrange_t>`. Add support to the
`netrange_width()` function to be able to handle this case.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that binding task and function arguments by name works as expected.
Also check that is works for the various variations of invoking a class
constructor.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In addition to providing positional arguments for task and functions
SystemVerilog allows to bind arguments by name. This is similar to how
module ports can be bound by name.
```
task t(int a, int b); ... endtask
...
t(.b(1), .a(2));
```
Extend the parser and elaboration stage to be able to handle this. During
elaboration the named argument list is transformed into a purely positional
list so that later stages like synthesis do not have to care about the
names.
For system functions and tasks all arguments must be unnamed, otherwise an
error will be reported.
In addition to functions and tasks arguments can also be bound by name for
the various different ways of invoking a class constructor.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Attach line information to named items. This allows to provide better
location information for messages involving named items. The location of
item itself can't always be used, since the item itself might be empty.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a few different places in the parser that all parse named
expressions in the same way. Consolidate them into a single rule.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a few places in the code where a std::list is copied to a
std::vector by iterating through the list and copying each element over to
the vector. The std::vector type has a iterator based constructor that can
do the same.
Update the code to use it instead. This removes a bit of boilerplate code
and also makes it easier to update the code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`named_pexpr_t` is a typedef for `named<PExpr*>`. There are a few places
where `named<PExpr*>` is used directly. Replace those with `named_pexpr_t`
for consistency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a few places where some sort of expression list is printed. Add
helper functions to consolidate this in a single place and reduce the
amount of code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The last user of the named_number_t type was removed in commit 2f474358d9
("2f474358d99929ec625a46690d1be6939ed67064"). Remove the type as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When vvp parses a command which it thinks is a system call it tries to
match the symbols to values in the scope. The typo uses the wrong index
variable to access the vpi table. This results in a failed dynamic cast
which goes unchecked until the value is dereferenced, resulting in a
segfault.
Check that constructor chaining for various corner cases of mixing implicit
and explicit constructors are handled correctly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently when neither an explicit constructor is specified nor any
properties are present in the class that will create an implicit
constructor there will be no constructor for the class.
As a result a class that specifies the arguments for the base class
constructor as part of the `extends` clause will not have the base
constructor called with the right arguments.
E.g.
```
class C;
function new(int a);
endfunction
endclass
class D extends C(10);
endclass
```
To avoid this make sure that an implicit constructor is created when
passing arguments through the `extends` clause.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are some corner cases around class constructor chaining that can
result in chained constructors not being called, or being called multiple
times.
This is primarily related to that a class can have either an explicit
constructor called `new` and an implicit constructor called `new@` and how
the lookup of them is done.
Lookup is currently done independently for the implicit and explicit
constructor using the `method_from_name()` method. `method_from_name()`
will search the whole class hierarchy for a class method. If a class
doesn't have a method by that name it will look in the parent class and so
on.
As a result the lookup for the explicit constructor can return the explicit
constructor of a parent class if the class itself only has an implicit
constructor and vice versa.
E.g. in the following example the constructor of D will not be called
because the implicit constructor for C is found when looking for a implicit
constructor in D.
```
class C;
int x = 10;
endclass
class D extends C;
function new;
$display("D");
endfunction
endclass
class E extends D;
int y;
function new;
y = 20;
endfunction
endclass
E e = new;
```
There is a similar case where the constructor of a base class can be called
multiple times if the base class has an explicit constructor and the
derived class has an implicit constructor. In that case the derived class
constructor will call the base class constructor, but the code that is
emitted for the `new` statement will call both of them.
To mitigate this introduce a new method to lookup the constructor that will
search for either the explicit or implicit constructor in the current class
and only continue to search in the base class if neither is found.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Commit 3daa2982ac ("Add support for `const` variables") added support for
constant variables, but had a small mistake and did propagate the constant
flag from the parser if the variable is declared with the `var` keyword.
Still allowing to modify those variables. Fix this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Automatic 2-state vectors currently get initialized to 'hx, while their
default value should be 0.
Make sure the vector is initialized to 0 at the beginning of the automatic
context.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows to declare const variables. These variables are
read-only and can not be assigned a value after their declaration. It is
only possible to assign an initial value as an initializer.
E.g.
```
const int x = 10;
x = 20; // Error
```
The LRM requires that for variable declarations with static storage the
initializer is a constant expression with the extension that other const
variables are also allowed. const variables with automatic storage can
be initialized by any expression.
Checking if an expression contains only const variables requires a bit more
work to implement. So for now be more lenient that what the standard
requires and allow arbitrary expressions to initialize const variables even
for those with static storage.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
arith_expr_type() queries the expression type of its two child nodes up to two
times. Since the child nodes might also need to query their child nodes
expression type to determine their own this can lead to an exponential runtime.
For complex expressions this can easily result in very long elaboration time.
Avoid this by querying the expression type only once for each child node.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to declare module ports with only partial
attributes. Other attributes should be inherited from the previous port in
the list or use the default.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In Verilog it is possible to declare multiple ports as part of the same
port declaration. Ports declared this way all have same direction, signal
kind and data type. E.g.
```
module M (input [3:0] a, b, c) ...
```
SystemVerilog extends this and allows to override on a per port basis
certain port attributes. E.g. redefine just the data type
```
module test (input [3:0] a, [1:0] b, int c) ...
```
Or to just redefine the port kind
```
module test(input [3:0] a, var b, wire c) ...
```
It is even possible to leave out the direction for the very first port. As
long as at least one other property of the port is specified. In that case
the direction will default to `inout`. E.g.
```
module test(integer a, b, c) ...
```
Furthermore it is possible to specify unpacked dimensions for each of the
ports. E.g.
```
module test(input integer a, b[1:0], c[3:0][1:0]) ...
```
If all port properties are omitted for the first port this indicates the
start of a non-ANSI port list.
Extend the parser to handle this.
If all three direction, port kind and data type are omitted they are
inherited from the previous port. Otherwise
* If the direction is omitted it is inherited from the previous port.
* If the data type is omitted it defaults to logic.
* If the port kind is omitted the behavior depends on the direction.
For output ports with an explicit data type it is a variable, for
all others it is a net.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a helper function to the parser that handles module port declaration.
This allows to reduce a bit of duplicated code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`$bits()` for array types is supposed to return the full size of the array
in bits. This currently works for data types that are passed to `$bits()`,
but not for array typed identifiers.
E.g.
```
typedef int T[1:0];
T x;
$display($bits(T)); // -> 64
$display(x); // -> 32
```
Since the `$bits()` implementation uses the expr_width of an expression
include the size of the unpacked dimensions in that for array identifiers
and array slices. Strictly speaking an array identifier does not have an
expression width, but this would be its expression with if it were for
example bitstream cast to a vector.
Special care needs to be take to not trying to pad array identifier
expressions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Bit selects on packed arrays are always unsigned and have a width of 1.
Element selects on a multi-dimensional packed array are always unsigned and
have the width of the element.
At the moment a element or bit select on the last level element of a
multi-dimensional signed array will incorrectly yield a signed expression.
Commit 40b36337e2 ("Fix some bugs with packed array dimensions") added
some special checks to fix the width on multi-dimensional array element
selects. But this removed the unsigned attribute from bit selects.
Commit 81947edaa5 ("A bit select is not the same as selecting part of a
packed array") fixed this for single dimensional packed array, but left it
broken for multi-dimensional arrays.
Commit 7c024d6cab ("Fix width calculation for bit/part selects of
multi-dimensioned packed arrays.") added some additional fixes for the
width calculation, which make the special checks in the first commit
unnecessary.
We can now remove those checks which will give us the correct behavior in
terms of the signedness of bit and element selects on both single- and
multi-dimensional packed arrays.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
At the moment there are two rules for port declarations. One that allows
the port to be declared as an unpacked array, the other that allows to
specify an initializer expression.
SystemVerilog allows both to be specified in the same port declaration. Add
support for this to the parser.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The module_output_port_list_def declares a output port with an implicit
data type and assigns an initial value to it. Since output ports with an
implicit data type are nets this test is not standard compliant.
This only works because at the moment the parser incorrectly flags all
output ports with an initial value as variables rather than following the
method defined by the standard to decide whether the port should be a net
or variable.
Make the test standard compliant by using an explicit data type for the
output port, in which case it will be a variable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The currently used checkout@v2 CI action shows the following deprecation
warning
```
Node.js 12 actions are deprecated. Please update the following actions to
use Node.js 16: actions/checkout@v2. For more information see:
https://github.blog/changelog/2022-09-22-github-actions-all-actions-will-begin-running-on-node16-instead-of-node12/.
```
Github has announced that this will eventually stop working somewhen in mid
2023.
Switch to checkout@v3 which uses Node.js 16 to avoid the ci from breaking
in the near future.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that basic assignment patterns are supported for unpacked arrays.
Check that all of packed types, reals and string arrays are supported.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows to use assignment patterns to assign values to an
array. E.g. `int a[4] = '{1, 2, 3, 4}`.
Each value is evaluated in the context of the element type of the array.
Nested assignment patterns are supported. E.g. `int a[2][2] = '{'{1, 2},
'{1, 2}};`
Add initial support for array assignment patterns for both continuous as
well as procedural assignments.
For continuous assignments the assignment pattern is synthesized into an
array of nets. Each pin is connected to one of the assignment pattern
values and then the whole net array is connected to target array.
For procedural assignments it is unrolled in the vvp backend. E.g
effectively turning `a = '{1, 2};` into `a[0] = 1; a[1] = 2;`.
Not yet supported are indexed initializers or `default`.
E.g. `int a[10] = '{1:10, default: 20};`
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Types for array signals are currently handled as a special case. The type
that is associated with the signal is not the array type itself but rather
the element type.
There is a fair amount of existing code that depends on this behavior so it
is not trivial to change this.
But there are certain constructs such as assignment patterns or array
concatenation where the array type itself is required.
Add a new `NetNet::array_type()` method that will return the array type if
the signal is an array. This will allow to query the array type when
needed.
`NetAssign_::net_type()` is updated to use this new method to return the
array type if the assigned signal is an array.
Long term the special handling of arrays for signals should be removed.
This will for example allow to unify the handling of arrays for signals,
class properties and struct members.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The are many binary operations where if the two operands are 2-state the
result is guaranteed to be 2-state.
This is true for all arithmetic operation with the exception of division
where division by 0 will always result in 'x even if the inputs are both
2-state.
The same is true for all binary bitwise operators as well as the binary
logical operators.
Having the expression type be 2-state avoids some unnecessary %cast2
instructions that would otherwise get inserted when assigning the result to
a 2-state variable.
E.g without this change the following will result in
```
int a, b, c;
b = a + b;
```
will result in
```
%load/vec4 ...;
%load/vec4 ...;
%add;
%cast2;
%store/vec4 ...;
```
For binary comparison operators this is already handled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are some cases where during an assignment the elaboration step can
generate constructs with the right-hand-side expression being wider than
the left-hand-side expression.
To handle this the tgt-vvp backend inserts a %pad operation when necessary.
One place where this is missing is when writing to an string element. Here
instead an assert is triggered requiring the right-hand-side expression to
be 8 bits wide.
E.g.
```
bit [7:0] x;
bit [8:0] y;
string s;
x = y; // tgt-vvp inserts %pad
s[0] = y; // tgt-vvp triggers assert
```
Long term this should be fixed at the elaboration stage and insert the
proper width cast. But for now solve this the same way as other places in
tgt-vvp and insert the %pad operation for string element assignments if the
width does not match.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`ivl_assert()` is similar to `assert()` except that it will also include
source file and line information about the expression for which the assert
was triggered.
Use `ivl_assert()` instead of `assert()` where the line information is
available. This will generate better bug reports and make it easier to
diagnose why an assert is triggered.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that the file and line location is correct for errors
related to implicit named port connections.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Some tests require a specific compiler error, rather than just failing. Add
support for this by allowing to check for gold files for CE tests.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Implicit named port connections are only supported by SystemVerilog. Add a
check to generate an error when trying to use it in Verilog mode.
Regression test br_gh315 is modified to run in SystemVerilog mode since it
makes use of implicit named port connections.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The implicitly generated identifier for implicit named port connections
gets its file and line information from the optional attributes. If no
attribute list is specified this will just point to the beginning of the
file resulting in incorrect line information.
Use the file and line information from the identifier token instead to fix
this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that implicit import of functions and tasks is supported if the
wildcard import statement is in the unit scope.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog requires that functions and tasks are not implicitly imported
if a symbol with the same name appears in the scope, even if it the symbol
is declared after its usage.
To support this a list of potential imports is collected while parsing a
scope and only when the end of the scope is reached it is evaluated whether
the symbol should be imported or not based on whether it already exists in
the scope.
This currently works fine for all scopes except for the unit scope. Since
the unit scope might span multiple files it is never explicitly closed and
the potential imports are never checked.
Make sure that after parsing all files is done the potential imports for
the unit scope are checked.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add support for `continue` and `break` in constant functions. This is done
in a similar way to how `disable` is implemented for constant functions.
Two new global flags are introduced `loop_break` and `loop_continue` that
get set when evaluating the corresponding statement. If either of these
flags are set all other statements are ignored until the end of a loop is
reached. At the end of the loop both `loop_break` and `loop_continue` get
cleared. If `loop_break` was set before clearing it the loop is exited.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to omit trailing ports in a module ordered list
connection list.
Also check that an error is generated if too many ports are specified in a
ordered list connection.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The current implementation expects that for a module instantiation with a
ordered list connection all ports are supplied.
But there doesn't seem to be such a requirement in the LRMs. The Verilog
LRM doesn't mention anything in this regard and the SystemVerilog LRM
mentions in section 23.3.2.1 that a blank or omitted port connection is
either left unconnected or uses the default value of the port.
Update the implementation so that it allows to omit trailing ports and only
generates an error message if too many ports are specified in the ordered
port list.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently continue and break are supported in most loops. But not in
do-while loops. Add support for them in do-while loops as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that partial and fully out-of-bound writes to a function's return
value are handled correctly. Check this for both 4-state and 2-state
vectors.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Partial out-of-bounds write to a function's return value will trigger an
assert, even though the operation is valid.
The assert checks that the truncated value has the expected width, but
instead it should check that the non-truncated value has the expected with.
Move the assert before the truncation to fix this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Directly casting a negative double to a unsigned integer type is undefined
behavior and has different results on x86 and ARM based platforms.
On x86 the behavior is similar to casting a signed int to an unsigned
integer, i.e. the sign bit will end up in the MSB. But on ARM the result
will be 0.
To get consistent behavior, first cast to signed integer and then cast the
signed integer value to an unsigned integer value.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The current check to decide whether a port is an array or a scalar signal
uses the number of pins on the NetNet. If it is larger than one the code
assumes that it is an array.
But for arrays with on a single element the number of pins will be 1 and
the port is incorrectly treated as a scalar signal which results in an
error.
Instead of using the number of pins check for the number of unpacked
dimensions to decide whether the port is an array.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check support for using the return statement in a task.
* That it is possible to exit form a task using the `return` statement
without affecting other concurrently running instances of the same task
* That it is possible to use return in a named block in a task
* That using a return value in a task results in a elaboration error
* Returning from inside a parallel block in a task results in a
elaboration error
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows to use the `return` statement in a task to exit the
task before it reaches the end of its execution. This is defined in section
13.3 ("Tasks") of the LRM (1800-2017).
This is similar to using `disable` to stop a task from within itself with
the difference that `disable` will affect all concurrently running
executions of a task, while `return` will only affect the task from which
it has been called.
The `%disable/flow` vvp instruction allows to implement the required
behavior for task return.
There is one complication in that it is not allowed to call return from
inside a parallel block (fork-join). If a parallel block is unnamed and has
no variable declarations there won't be a NetScope for it. So it is not
possible to detect whether the return is inside a parallel block by
walking up the scope chain.
To solve this add a design global counter that gets incremented when
entering a fork block and decremented when exiting a parallel block. The
return implementation then checks if the counter is non 0 to determine
whether it is in a parallel block.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that assigning array that have opposite left-to-righto order for
their dimensions have their elements assigned in reversed order.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In SystemVerilog arrays assignments are supposed to be connected left to
right. This means if the left to right direction differs between the two
arrays they will be connected in reverse order.
E.g.
```
logic a[1:0];
logic b[0:1];
assign b = a;
```
should connect a[0] to b[1] and a[1] to b[0]. Things get a bit more tricky
for multi-dimensional arrays where some dimensions have a matching
direction and some do not.
The current implementation always connects them low to high, which results
in incorrect behavior.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In the current implementation a `%fork` instruction in a final block will
get scheduled, but never executed.
And while SystemVerilog requires a `final` procedure to execute in 0 time
and so no SystemVerilog `fork` is allowed inside of it, there are some
other scenarios where iverilog generates `%fork` statements.
For example when declaring variables in a sub-block a sub-scope with its
own thread is is used to allocate the storage for those variables and
`%fork` is used to execute the child thread.
E.g. the following, while being valid SystemVerilog, will never execute the
loop because the generated code will implement the loop as a child thread
being executed by a `%fork` statement.
```
final for (int i = 0; i < 10; i++) $display(i);
```
To mitigate this treat final statements the same as functions and rather
than scheduling a child thread, execute it immediately when using the
`%fork` statement.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The port_index_ member of the NetNet is not initialized which can lead to
undefined behavior. Make sure to initialize to -1 to indicate that the net
is not associated with any port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that foreach counts counts from $left to $right. This means it should
count up if $left is less than $right and count down otherwise.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
foreach loops are supposed to iterate arrays $left to $right. E.g. `reg
x[3:0]` should be iterated from 3 to 0 and `y[1:4]` from 1 to 4.
The current implementation iterates them from $low to $high. Modify this to
either count up or down depending on whether $left or $right is the larger
of the two values.
Note that the same applies for dynamic arrays. But since for dynamic arrays
$left is always 0 and $right is always $high they always count up and we do
not need to differentiate between two different cases.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
vvp_reg.py requires 4 gold files. One for each of stdout and stderr of both
iverilog and vvp. Most of these log files will be empty for most test
cases. This will result in a lot of empty files being added to the
repository.
If a gold file for a specific output stream can not be found assume that
the output stream is supposed to empty. This allows to omit the empty gold
files.
Also remove all the existing empty gold files.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This adds the "normal-vlog95" test type, because we need to run a different
set of commands for this to work so a new test type makes sense. This also
moves a few of the existing tests to the new format in order to test the
new test rig.
Check that packed array assignment patterns and struct assignment patterns
are supported for continuous assignments.
Check for both assignment to variables as well as array elements.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently when creating the NetNet for a continuous assignment to an array
element the type of the element is flattened into a canonical 1 dimensional
form. This works for most cases because packed types are compatible if
their total packed with is the same.
But there are some contexts such as if the right-hand-side is an assignment
pattern where the actual type matters and flattening the type will result
in incorrect behavior.
Retain the original type of the array element when creating the NetNet for
the array element assignment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a regression test to show that the proper dumpfile is selected, by
noting in the output from the vvp command what file name it is creating.
To make this work, I also needed to add some capabilities to the vvp_reg.py
regression test rig.
The -dumpfile=<path> vvp extended argument sets the default nanme to use
for the various dumpers. If this flag is not given, the default is "dump".
The $dumpfile system task overrides the default or this command line flag.
This commit also factors out all the dumpfile selection code for the various
dumper implementations.
This generates a fresh copy of config.sub.
The existing config.sub calls 64-bit ARM targets `aarch64`, which is
the official name for the target. However, Apple targets go by the
name `arm64-apple`. As a result, this platform was not recognized.
This gets iverilog building on Apple targets with 64-bit ARM processors.
Signed-off-by: Sean Cross <sean@xobs.io>
This creates a new test suite driver and infrastructure for going
forward. This cleans up the descriptions for tests, and is more
extensible.
Include documentation for the new engine, so that new tests can go
here instead of the old test suite.
Check that struct assignment patterns with only positional arguments are
supported. Also check that invalid assignment patterns for structs report
an error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that positional and nested positional assignment patterns are
supported for packed arrays. Also check that invalid assignment patterns
for packed arrays result in an error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Structs can be initialized by an assignment pattern. E.g.
```
struct packed {
int x;
shortint y;
} S = '{ 1, 2};
```
is the same as
```
struct packed {
int x;
shortint y;
} S;
s.x = 1;
s.y = 2;
```
Add initial support for unnamed struct assignment patterns. Named struct
assignment patterns like
```
struct packed {
int x;
shortint y;
} S = '{x: 1, y: 2};
```
are still unsupported.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows to use assignment patterns to assign a value to a
packed array.
This is similar to using a concatenation, with the difference that for
concatenations the values are evaluated in a self-determined context and
for assignment patterns they are evaluated in a context defined by the
element type of the packed array. This means that the value is for example
automatically width expanded or truncated if it does not have the same size
as the element type. Automatic type conversion is also done when allowed. E.g.
```
bit [3:0][3:0] x = '{1'b1, 32'h2, 3.0, "TEST"};
$display("%x", x); // -> 1234
```
Nested assignment patterns are also supported. E.g.
```
bit [1:0][3:0][3:0] x = '{'{1, 2, 3, 4.0}, '{5, 6, 7, 8}};
$display("%x", x); // -> 12345678
```
Add support for using assignment patterns as the right hand side value.
Since the complete type of the target variable is required to correctly
evaluate the assignment pattern it is handled as a special case in
`elab_rval_expression()`. For other types of expressions for packed values
only the total width of the target value is provided to the rvalue
elaboration function.
SystemVerilog also supports assignment patterns for the left hand side in
assignments. This is not yet supported.
Also not yet supported is specifying array elements by index, including
`default`.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that package exports are supported. Also check for various scenarios
where package exports should fail.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
By default an identifier that has been imported into a package is not
available for imports by other packages. Only imports that have been
exported can be imported again. E.g.
```
package P1;
int x;
endpackage
package P2;
import P1::x;
export P1::x;
endpackage
module test;
import P2::x; // This will only work if x has been exported.
endmodule
```
Exports follow the same syntax as imports and allow both export of specific
identifiers or wildcard export. Export supports the special `*::*` target,
which will export all imported items.
Add support for handling package exports.
There is one special cases that needs to be considered. Usually when using
wildcard imports from multiple packages it is an error if there multiple
import candidates for an identifier. With exports it is possible that there
are multiple candidates through different packets, but they all refer to
the same identifier. In this case it does not create a conflict. E.g.
```
package P1;
int x;
endpackage
package P2;
import P1::x;
export P1::x;
endpackage
package P3;
import P1::*;
import P2::*;
int y = x; // No import conflict
endpackage
```
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This is a test for github issue#800. This should work on all platforms,
but Windows seems weird. The issue seems to be with Windows comparing
gold files with CR-LF weirdly, so make all the tests internal.
Add additional enum compatibility tests that check for compatibility in
different contexts.
* Array element
* Function return value
* Function and task argument
* struct member
* class property
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In SystemVerilog it is not allowed to assign a value to a enum variable
that is not of the same time as the enum variable.
This is currently enforced for assignment and continuous assignment. But
ignored in other places such as function parameter passing.
Move the enum type check into `elab_rval_expr()` to cover more cases.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In most cases the type of an lvalue part select is the base type of the
lvalue with the width of the part select. But there are some exceptions.
1) An index into a `string` type is of type `byte`.
2) Packed structs are implemented as packed arrays under the hood. A lvalue
struct member is elaborated as a normal part select on a packed array. The
type of that select should be the type of the member.
For the case 1 there is some special handling for strings that accounts for
this. But for case 2 the type information of the member is lost.
This works fine for most things but there are a few constructs where the
type information is required.
* Enum type compatibility check
* Assignment pattern behavior depends on the type of the lvalue
Allow to attach a specific type to a lvalue part select to allow correct
behavior for constructs where the type is required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The NetAssign_:net_type() function return the type of lvalue expression.
But it only does so for a limited amount of cases.
Refactor the function so that it works for the general case and always
returns the data type, if the data type of the lvalue expression is known.
This will allow to implement better type checking and other constructs such
as pattern assignments that require to know the type of the lvalue.
It also allows to remove some duplicated code in other methods of
NetAssign_ that want to lookup the type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that an error is reported when accessing a hierarchical identifier
through a package scoped identifier.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Package scoped identifiers should only be able to access identifiers that
are declared in the package, but not identifiers that are visible in the
package, but declared outside of it.
```
int x;
package P;
int y;
endpackage
module test;
initial begin
$display(P::x); // Should fail
$display(P::y); // OK
end
endmodule
```
Make sure that the symbol search will not attempt to cross the package
boundary during identifier lookup.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In SystemVerilog identifiers can usually have an additional package scope
in which they should be resolved. At the moment there are many places in
the code base that handle the resolution of the package scope.
Add a common data type for package scoped paths as well as a
symbol_search() variant that works on package scoped identifiers. This
allows to handle package scope resolution in a central place.
Having the code in a central place makes it easier to ensure consistent and
correct behavior. E.g. there are currently some corner case bugs that are
common to all implementations. With the common implementation it only has
to be fixed in one place.
It will also make it easier to eventually implement class scoped
identifiers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a few NetExpr subclasses where the data type of the expression
is known, but it not attached to the NetExpr and only kept as a private
member in the subclass.
Attaching the type directly to the NetExpr allows to query it externally
and implement better type checking.
It also allows to remove a bit of duplicated code in the subclasses and
rely on the default implementation in the NetExpr base class.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The current NetExpr::enumeration() always returns a nullptr.
The NetExpr class has a ivl_type_t member that represents
the type of the expression.
Provide a default implementation of NetExpr::enumeration() that
casts this type to the netenum_t type. This will allow
to share this implementation between subclasses and remove
a bit of duplicated code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that function calls with empty arguments are supported. Check the
general case and special cases such as calling a function with empty
arguments as part of a module port binding or force statements in automatic
contexts.
Also check that calling a function with too many trailing empty arguments
as well as passing an empty argument for a port without a default value is
an error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that class properties can be shadowed by local symbols in class
methods and also check that a package scoped identifier with the same name
as class property can be accessed in a class method.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are currently two mechanisms for handling class properties. One that
is used when a class property is accessed through an object and other when
a class property is used freestanding in a class method.
Both are very similar, but there are some small differences. E.g. one
supports arrays, the other supports nested properties.
```
class B;
int x;
endclass
class C;
B b;
B ba[2];
task t;
ba[0] = new; // Does work
this.ba[0] = new; // Does not work
b.x = 10; // Does not work
this.b.x = 10; // Does work
endtask
```
There is another problem where free standing properties take precedence
over local variables. E.g.
```
class C;
int x = 1;
task t();
int x = 2;
$display(x); // Should print 2, will print 1
endtask
endclass
```
The class property elaboration also ignores the package scope of the
identifier resulting in access to a class property being elaborated if
there is a property of the same name as the scoped identifier. E.g.
```
package P;
int x = 2;
endpackage
class C;
int x = 1;
task t;
$display(P::x); // Should print 2, will print 1
endtask
endclass
```
Consolidate the two implementation to use the same code path. This is
mainly done by letting the symbol search return a result for free standing
properties as if the property had been specified on the `this` object. I.e.
`prop` and `this.prop` will return the same result from the symbol search.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
As a quirk of the (System)Verilog grammar a function or task argument list
with no arguments can not be distinguished from a argument list with a
single empty argument. The iverilog parses it as the latter. There are
currently many places in the code base where this is fixed up in slightly
different ways.
Fix this up in the parser in a central way before passing the arguments to
the elaboration stage.
The existing implementation in some cases removes all empty trailing
arguments. While this works to handle the case for zero arguments it also
hides some errors that should be detected. E.g. in the following 3
arguments are passed to a function which only takes two arguments. But no
error is reported since the explicitly specified empty arguments are
removed.
```
function f(integer a, integer b = 2); ... endfunction
f(1,,);
```
In the new implementation the empty argument will only be removed if there
is exactly one empty argument in the argument list.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
A function parameter can be an empty value, in which case its expression is
a nullptr and can not be dereferenced. Make sure this case is handled in
the has_aa_term() and declare_implicit_nets() methods.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The default value for a function or task argument is elaborated once and
then used for each function invocation where no actual value is provided.
This means if a function or task is called multiple times the same NetExpr
is passed as a sub-expression to multiple statements or expressions such as
the function call.
This is causing problems because each expression or statement expects to
have exclusive ownership over its sub-expressions. It can for example
result in a double free or other undefined behavior.
To mitigate this duplicate the default argument expression before it is
given as a sub-expression to another expression or statement.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are no users of the old symbol_search that need the cls_val result.
Remove it as a output parameter of the function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This includes support at the parser (pform) through enaboration
and the netlist format for the break and continue statements.
Elaboration actually already worked for for-loops, but since the code
generators need more information, this is a rewire of that support to
be explicit about for-loops. This means they are not rewritten as fancy
while loops. The code generators will have to handle that.
Given the elaboration of for-loops now work, write the vvp code generator
support needed to implement it.
Now that for-loops are presented as for-loops to the code generator, the
vlog95 code generator doesn't need to infer them anymore. Generate the code
more directly.
Also update the tests list so that the vlog95_reg tests all pass.
Check that it is possible to call a method on a package scoped identifier.
Both for built-in types as well as class objects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently package scoped function calls are supported. Update the parser
and elaboration to also allow method calls on packaged scoped variables.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that an error is reported when trying to access an imported
identifier through a hierarchical name.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Imported identifiers should only be visible in the scope they have been
imported too. They should not be accessible through hierarchical names into
that scope. This is defined in section 26.3 ("Referencing data in
packages") of the LRM (1800-2017).
Modify the symbol search to not look at imports if the name is part of a
hierarchical path.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The github CI VM has multiple CPUs. 2 for Linux and Windows, 3 for macOS.
Make use of parallel build to speed up the CI tests a bit.
For Windows the `makepkg-mingw` command already schedules a parallel
build, so no changes are made to the Windows build.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that null-bytes get removed when reading a value through the VPI API
as a vpiStringVal. Also check that null-bytes are not removed from string
literals when string literals are read through the VPI API as a non
vpiStringVal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The vlog95 backend currently strips null-bytes from strings in structural
elements. E.g. `assign y = "a\000b"` gets translated to `assign y = "ab"`.
This changes the behavior of the generated output compared to the input.
Don't ignore the null-bytes to make sure the behavior stays the same.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When a string literal is used in a context where it needs to be wider than
it is it will get left-padded with null-bytes. When the vlog95 backend
emits the string literal it will strip the leading null-bytes as it results
in much more legible code.
Unfortunately there are some corner cases where this results in a change of
behavior of the generated code compared to the original. E.g. if the
context that caused the width expansion has been removed by optimization.
`$display(0 ? "Yes" : "No")` should print " No" due to width expansion, but
when running through the vlog95 backend it will print "No".
Another scenario where there is a change in behavior is when a null byte
was explicitly added at the front of a string literal. E.g. $bits("\000ab")
should print 24, but will print 16 when running through the vlog95 backend.
To mitigate this remove the stripping of the leading null-bytes from the
vlog95 backend. This results in slightly less legible code being generated
in some cases, but makes sure that the code is always correct.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently when reading a number literal through the VPI API as a
vpiStringVal all null-bytes in the literal get ignored. This behavior is
different from when reading a signal through the VPI API as a vpiStringVal.
The latter will only ignore leading null-bytes and replace other null-bytes
with a space. E.g. the following two will print different values.
```
$display("%s", "a\000b"); // -> " ab"
reg [23:0] x = "a\000b";
$display("%s", x); // -> "a b"
```
For consistency modify the number literal formatting code so that it has
the same behavior as the signal value formatting code and only replaces
leading null-bytes.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The VPI API for string literals does not correctly handle the case where a
null-byte ('\0') appears in the string literal. It uses strlen() to
calculate the length of the literal, which will give the wrong result if
there is a null-byte in the string literal. Instead of using strlen() use
the stored length to fix this.
In addition when formatting a string literal as a string ignore any
null-bytes. The LRM is not entirely clear what should happen to null-bytes
when formatting a value as a string. But the behavior of ignoring the
null-bytes is consistent with the rules of SystemVerilog for converting a
string literal to a SV string.
This problem can occur when a string literal gets null-byte left-padded due
to width of its context of its expression, but then optimization removes
part of the expression and only leaves the padded string literal.
E.g.
```
$display(0 ? "Yes" : "No");
```
will be transformed into
```
$display("\000No");
```
There is also one subtle change in behavior associated with this. The empty
string ("") is supposed to be equivalent to 8'h00. So e.g.
`$display(":%s:", "")` should print ": :" since the width of the empty
string is 1 byte and the %s modifier prints a string with the width of the
value, left-padding with spaces if necessary. The current implementation
will print "::" though. This change requires to update the marco_with_args
gold file.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that when assigning or casting a string literal or vector to a SV
string type that null-bytes are removed.
Also check that writing a null-byte to an element of a string variable is
ignored.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `%pushi/str` and `%concati/str` instructions should remove null-bytes
from the string literal when converting it to a string. This is defined in
section 6.16 ("String data type") of the LRM (1800-2017).
This is already handled correctly when converting a vector from the stack
to a SV string, just not when converting a string literal to SV string.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Make sure the package scope is considered when elaborating identifiers for
continuous unpacked array assignments.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Classes are allowed to access properties of the base class. This also
includes static properties. Currently when looking up a static property
only those of the class itself are considered. Extend this to also consider
properties of the base classes.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that an error is reported, rather than crashing, when trying to do a
package scoped function call when the function does not exist in the
package or is not a function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently a package scoped function call will result in an assert if the
function does not exist in the package scope.
For non-package scoped function calls instead a proper error is reported.
Refactor the code to share the same code paths between package scoped and
non-package scoped function calls. This makes sure that errors are reported
in both cases. It also makes the code slightly smaller.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that indices to package scoped identifiers are evaluated in the scope
where the identifier is accessed and not in the scope where the identifier
is declared.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a few cases where a member select on a package scoped identifier
is evaluated in the scope of the package rather than the scope where the
identifier is referenced.
This leads to incorrect behavior if a local symbol is used as an index in a
part select of the referenced member select. E.g.
```
package P;
localparam N = 1;
struct packed {
logic [3:0] x;
} s = 4'b0101;
endpackage
module test;
localparam N = 2;
initial $display(P::s.x[N]); // Will print 0, should print 1
endmodule
```
Use the scope where the member select is used, rather than the scope where
the identifier is defined, to fix this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`PECallFunction::test_width()` does not consider the package scope and will
not return any information for package scoped function calls.
As a result in contexts where the width or sign of a expression must be
known produces the wrong result when using a package scoped function.
Make sure to search for the function name in the package scope if a package
is specified.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The vlog95 backend currently ignores the sign of a function return value.
Check for it and if `-pallowsigned=1` was specified emit the `signed`
keyword. Otherwise report an error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The parameter_no_default test is expected to pass in SystemVerilog mode.
Make sure the expected result is correctly annotated in the results file.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows struct members to have default values specified as
part of the struct declaration. But this is only allowed for unpacked
structs. For packed structs an error should be reported. This is defined in
section 7.2.2 ("Assigning to structures") of the LRM (1800-2017).
Currently default member values are just silently discarded if specified
for a packed struct. Make sure to report an error instead.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Make sure that comments spanning multiple lines are supported in multi-line
macros. Since the lexer parses line by line we need a flag to track whether
a multi-line comment is currently active.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
A '*' or '/' directly following a C-style comment in a macro currently
triggers the detection of the start of another comment. Fix this by first
looking for a '/' that should start the comment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that variables used in void functions contribute to the sensitivity
list in a always_comb block.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Internally void function calls are modeled as task calls. But unlike task
calls, access to a signal inside a void function is supposed to contribute
to the sensitivity list of an always_comb block.
Make sure that the same logic applied for non-void functions is also
applied for void functions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that an error is reported for size casts with either a value of 0, a
negative value or an undefined value.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Size casts are only allowed if the value is positive. For cases where it is
0 negative or undefined an error should be reported. Currently the negative
case is not handled. Extend the test to also check for negative values.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
msys2 removed the gperf package from the base-devel package collection[1].
Add gperf explicitly to the dependency list, without this the Windows
CI will fail.
[1] 085698dce3
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the Windows build generates a warning
=> WARNING: MINGW_INSTALLS is deprecated, use MINGW_ARCH instead
Make this change to the CI workflow file.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
With the development version bumped to v13 the regression tests runner
expects a `regress-v13.list`. Provide one, which is just a copy of the
`regress-v12.list` for now.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to use the `super` keyword to access properties
and methods of the base class that exist with the same name in current
class.
Also check that `this.super` is supported as an alternative to `super` and
has the same behavior.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows to use either `super` or `this.super` to access the
base class. Both have the same behavior. Currently only `super` is
supported, also add support for `this.super`.
To support it the parser has to be changed slightly and move the trailing
`.` after the `this` or `super` keywords into the `implicit_class_handle`
parser rule. This is necessary to avoid reduce conflicts in the grammar.
As a side effect `super` can no longer be used as a standalone identifier.
E.g. `return super;` But that's not legal SystemVerilog anyway, so that is
OK.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows to use the `super` keyword to access properties and
methods of a base class. This is useful if there is for example an
identifier with the same name in the current class as in the base class and
the code wants to access the base class identifier.
To support this a bit of refactoring is required. Currently properties are
internally referenced by name, this does not work if there are multiple
properties of the same. Instead reference properties always by index.
In addition when looking up an identifier that resolves to an object return
both the type and the object itself. This is necessary since both `this`
and `super` resolve to the same object, but each with a different type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Internally the special THIS_TOKEN("@") and SUPER_TOKEN("#") are used
to represent the special `this` and `super` keywords in a component
name.
When printing an identifier replace the tokens with their keywords.
This generates nicer error and debug messages.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The PEIdent elaborate_expr() and elaborate_lval() are sort of open-coding
the path traversal implemented by the new symbol_search() using the old
symbol_search().
Switch them over to use the new symbol search as it is better at handling
the corner cases and is also less code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
One variant did, the other variant didn't. As well as being a trap for
the unwary, this gets in the way of using yywarn/VLwarn for non-fatal
"sorry" messages.
The function prototypes both use the name VLwarn, with a macro definition
providing the alias to yywarn. But one of the variant implementations was
named yywarn. Make it consistent with the function prototype.
Always prefix with "error: ". Capitalise the first word of the main
message unless it's a Verilog keyword. Use VLerror() in preference
to direct output to cerr.
Check that typed constructors calls are supported. Also check various
invalid usages of typed constructor calls and check that an error is
reported.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
By default when creating a new class object the type of the object is
determined by the type of the target.
SystemVerilog also allows to explicitly specify the type of the object to
be created. The specified class still needs to be assignment compatible
with the target. This is e.g. useful to construct an object of a derived
class of the target. E.g.
```
class B; ... endclass
class C extends B; ... endclass
B b;
b = C::new;
```
Add support for this to the parser as well as handling it during
elaboration.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Class methods with static lifetime are not allowed in SystemVerilog. Report
an error when such a method is declared.
Note that this is different from static class methods
E.g.
```
class C;
task static t; endtask // Class method with static lifetime, forbidden
static task t; endtask // Static class method, allowed
```
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Up to 1800-2017 the grammar in the LRM allowed an optional lifetime
qualifier for class declarations. Icarus supports this and uses this as the
default lifetime for methods of the class. But the LRM never specified what
this qualifier should do actually actually. Starting with 1800-2023 the
qualifier will be removed from the grammar[1].
Furthermore the LRM states that methods of a class are supposed to have
automatic storage and static storage is forbidden.
This currently works in Icarus for the most part since the liftime attached
to class methods is ignored during elaboration in most places. Where it
does not work is for variable initializers where it results in broken code
being generated and vvp crashes at runtime. E.g.
```
class C;
task t;
int x = 10;
endtask
endclass
```
Keep the optional lifetime qualifier for classes in the grammar for now, to
ensure backwards compatibility in case somebody is actually using it. But
ignore it and print a warning if it is specified.
In addition set the default lifetime for all classes to automatic. This
makes sure that variable initialization in classes works as expected.
[1] https://accellera.mantishub.io/view.php?id=3561
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Normally the preprocessor will catch these and report them as undefined
macros. But in case the compiler is run without the preprocessor, also
catch them in the compiler scanner. This will ensure the scanner properly
rejects directives that have additional garbage characters tacked on the
end.
Verilog compiler directives are free-form and, subject to semantic rules,
can appear anywhere in the source code. Whilst it is common practice to
write them on a separate line, we should handle all legal syntax.
Clean up warnings that show up on newer compilers. Many of these warnings
are related to obsolete c library features or language features. This does
not clear up warnings in code generated by bison or flex.
It was common practice in the past to just declare a port direction
and declare it as a vector in a subsequent type declaration. Versions
of the standard up to and including 1364-2005 include an example that
does this (e.g. 1364-2005 section 12.3.7). Users may have old or
third-party code that they can't or don't want to modify, so allow
the warning to be suppressed by including it in the anachronisms
category.
Check various different scenarios for array compatibility in continuous
array assign. Both testing cases that should work and cases that should
fail.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently there is no error checking for continuous assignments to unpacked
arrays. If the lvalue and rvalue net are not compatible undefined behavior
occurs. For some types of incompatibility it will crash during elaboration,
for others it will crash during simulation, and for some it will just work,
even though the assignment is not allowed by the standard.
Implement checking to ensure the two nets are compatible as required by the
standard and report an error otherwise.
Two arrays are considered to be compatible if their element types are
equivalent, they have the same number of ranges and each range has the same
number of elements.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to assign an object to another object that is of
a type of any of its base classes. Also check that an error is reported if
this is not the case.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows objects to be assigned to a variable that is a base
type of the objects type.
E.g.
```
class B; endclass
Class C extends B; endclass
C c = new
B b = c;
```
Add a type_compatibility() method for netclass_t that allows these kinds of
assignments.
This already works fine in vvp since, as SystemVerilog does not support
multiple inheritance, properties will always be at the same offset in the
base class and the inheriting class.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to use a function with a return type as a
statement by using a void cast.
Also check that trying to void cast a void function, a task or an
expression results in an error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog has explicit support for calling a function
as a statement. This is allowed when the function call is encapsulated in
`void'(...)`. E.g. `void'(f(1, 2, 3));`
We already support calling function calls as statements without the void
cast and emit a warning when doing so.
Adding support for void casts only requires to update the parser to handle
the void cast and then do not emit the warning if a function is called as
a statement as part of a void cast.
Void casting a task or void function call is not allowed and will generate
an elaboration error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When calling non-void functions or non-void methods of built-in types as a
task a warning is issued. But when calling a non-void method of a user
defined class as a task an error is generated.
Be consistent here and generate a warning in both cases.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Unpacked array dimensions that are specified with only a single size value
(C-style unpacked arrays) have a $left of 0 and a $right of size - 1. E.g.
`x[10]` is equivalent to `x[0:9]`. This is defined in the LRM (1800-2017)
section 7.4.2 ("Unpacked arrays").
Currently it is implemented the other way around. There are a few contexts
where this distinction matters. For example array to array assignments,
which are supposed to be done left-to-right.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that an error is reported when either calling a task or a void
function as part of an expression.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Calling a task as part of an expression should report an error. The current
implementation uses `func_def()` and if that returns nullptr will report
the error. But `func_def()` will trigger an assert if the underlying scope
is not a function.
Make sure to first check that the scope is actually a function before
trying to call `func_def()`. If the scope is not a function report an
error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Unlike normal functions void functions can not be called as part of an
expression. Trying so will currently hit an internal assert.
Make sure an error is reported instead.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
It is not allowed to create objects of virtual classes. Currently the
virtual keyword is accepted by the parser, but otherwise ignored.
Keep track of whether a class is virtual and generate an error when the
class new operator is used for a virtual type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that a sign, width or type cast expression that contains an automatic
term is detected as such and can not be used as the left-hand side in a
procedural continuous assignment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
If the base expression of a cast expression has an automatic term then the
cast expression itself has an automatic term.
Make sure this is implemented so that an error is properly reported when
using such an expression in a context where automatic variables are not
allowed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
With the recent refactorings pform_make_task_ports_vec() and
do_make_task_ports() are now very similar.
Consolidate them into a single function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The ivl_variable_type_t in PWire is now only used for passing the base type
for vector types to the elaboration stage. But we can query the base the
from the vector_type_t itself. If the there is no data_type_t set for the
PWire the base type will default to IVL_VT_LOGIC.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For loops may have empty initialization statements. In that case some things
can't be done, such as loop unrolling or synthesis, but otherwise it is a
valid thing to do. So generate the correct code in this case.
Check that it is possible to use a packed scope type identifier for the
type of a class property when the class is defined in the unit scope. This
makes sure that the elaboration is done in an order so that the type is
available when the class property is elaborated.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to use a forward declared class type as the type
of a property in another class.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Elaborating uses a multi stage approach. Currently non-static class
properties are elaborated during the scope elaboration phase. This can
cause problems if the type of a property is declared in a different scope.
In that case it is possible that the scope in which the type is defined has
not been elaborated yet and the type is not available. E.g.
```
package P;
typedef int T;
endpackage
class C;
P::T x;
endclass
```
Another area where this is problematic is when a class has a property of a
another class that has a forward declaration. In this case the type of the
forward declared class, which is created when the scope is elaborated, is
not available when the scope of the class that is using it is elaborated.
E.g.
```
typedef class B;
class A;
B b;
endclass
class B;
endclass
```
To avoid this elaborate the properties during the signal elaboration phase.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows to skip dimensions in a foreach loop by not specifying
an identifier name for the dimensions. E.g. the following will iterate over
the first and last dimensions, but skip the middle dimension.
```
int x[1][2][3];
foreach(x[a,,b]) ...
```
Add support for this to the parser as well as elaboration.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently when the number of loop variables in a foreach loop is larger
than the number of array dimensions an assertion is triggered.
Turn this into a error message instead for graceful error reporting.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog supports type parameters. These are similar to value
parameters, but they allow to pass a type to a module or similar when
instantiating it.
E.g.
```
module A #(parameter type T = int);
endmodule
module B;
A #(.T(real)) i_a;
endmodule
```
Add support for handling type parameters.
For the vlog95 and vhdl backends type parameters, similar to typedefs, get
replaced with their actual value. For modules with non-local type
parameters for each module instance a unique module or architecture is
generated with the actual type.
Querying type parameters through VPI is not yet supported.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Rather than moving one item at a time form the elaboration_work_list to the
temporary queue use std::swap to exchange them all at once. This is a bit
more efficient.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that all sorts of forward typedefs are supported.
Also check that any recursive use of a type results in an error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog supports forward type declarations. This allows to declare a
type identifier and use it, e.g. in a signal declaration, before declaring
what the actual type is. The type still needs to be fully defined
eventually in the same scope as its forward type declaration. E.g.
```
typedef T;
T x;
typedef int T;
```
The forward type definition can also contain the kind of the type it is
going to be. E.g struct, union, class, etc. The LRM calls this the basic
type. If the actual type is not of the basic type specified in the forward
type declaration this is an error. E.g.
```
typedef struct T;
typedef int T; // Error, int is not a struct
```
It is legal to have more than one forward type declaration for the same
type name, as long as the basic type is the compatible. It is even legal to
have a forward type declaration after the actual type has already been
declared. E.g.
```
typedef T;
typedef int T;
typedef T;
```
Implement support for forward type definitions as part of the new
typedef_t. The basic type will be attached to the typedef_t.
The compatibility of the basic type for multiple forward type declarations
will be checked in the parser. The compatibility of the basic type to the
actual type will be checked during elaboration, once the actual type is
known.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Enum types are currently elaborated in lexical declaration order. With forward
typedefs it is possible that a type is referenced before it is declared.
To support this elaborate the enum type on demand when it is used. This is
similar to what is being done for other types.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
With forward type declarations it is possible to create a circular type
definition where a type resolves to itself. E.g.
```
typedef T1;
typedef T1 T2;
typedef T2 T1;
```
Flag a type as elaborating when elaboration of the type is started and
clear it when elaboration finishes. If the elaboration function is entered
again while the flag is still set a circular type has been detected and an
error is reported.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently typedefs are just a pointer to a data_type_t.
Currently typedefs are implemented by setting the name field of a
data_type_t when a typedef of the type is declared. This works mostly, but
there are some corner cases that can't be supported.
E.g. a typedef of a typedef does not work as it overwrites the name field
of the same data_type_t multiple times.
Forward typedefs can also not be supported since forward typedefs allow to
reference a type before it has been declared.
There are also some problems with type identifier references from a
higher-level scope if there is a type identifier in the current scope with
the same name, but it is declared after the type identifier has been
referenced. E.g. in the following x should be a vector fo width 8, but it
will be a vector of width 4, because while the right type is used it is
elaborated in the wrong scope.
```
localparam A = 8;
typedef logic [A-1:0] T;
module M;
localparam A = 4;
T x;
typedef int T;
endmodule
```
Furthermore typedefs used for the type of ports are elaborated in the wrong
scope.
To handle these corner case issues introduce a data_type_t for typedefs.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that compressed assignment statements are supported for genvar loops.
This is supported in SystemVerilog, but not in Verilog.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog supports using compressed assignment operators for the genvar
for loop variable update.
Add support for this in a similar way as increment/decrement operators by
transforming the statement to its uncompressed equivalent. E.g. `x += y`
gets transformed to `x = x + y`.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that $signed/$unsigned works when being combinatorially assigned with a
delay and the target of the function is a net without any drivers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Trying to add a drive strength or delay to a undriven net will result in an
assertion. Make sure that a driver is added to undriven nets.
A driver is already added for all NetESignals, which covers most expression that
can produce a raw net rvalue. But there are other ways we can end up with just a
net as the rvalue, e.g. when applying a sign cast to a net. The following
example triggers the issue
```
wire [7:0] a;
wire [7:0] b = $signed(a);
```
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
macro_start_args truncates def_buf, but does not check to ensure that
someone has allocated def_buf first. This will cause a null pointer
dereference if the first access to def_buf while parsing a file is a
macro invocation. Fix this by avoiding truncating def_buf if it is NULL,
as it is effectively already truncated.
Fixes: 680196953 ("Add support for text macros with arguments.")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Check that it is possible to have scoped reference to a type identifier in
a package.
* As part of variable declarations
* As an argument to a system function
* As the type in a type cast
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that for a module port with a vector type identifier the type is
elaborated in the scope where it is declared rather than the scope of the
module port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently when referencing a typedef this gets replaced with the
`data_type_t` that the typedef points to. This works for most cases, but
there are some corner cases where it breaks down.
E.g. it is possible to have a scoped type identifier which references a
type defined in a package. For such type identifiers, only the data_type_t
itself is remembered, but not the package scope. This will cause the type
identifier to be elaborated in the wrong scope.
Furthermore type identifiers of vector types used for module or task port
might not be elaborated in the correct scope.
Introduce a new `typeref_t` which has `data_type_t` as a base type and can
be used as the data type for a signal. A new instance of a `typeref_t` is
created when referencing a type identifier. The `typeref_t` remembers both
the data type and the scope of the type identifier.
When elaborating the `typeref_t` the elaboration is passed through to the
referenced `data_type_t`. But special care is taken to lookup the right
scope first.
With the new approach also typedefs of typedefs are supported. This
previously did not work because chained typedefs all reference the same
`data_type_t`, but each typedef sets the `name` field of the `data_type_t`.
So the second typedef overwrites the first typedef and a lookup of the
scope of the first typedef by name will fail as it will return the scope of
the second typedef.
This refactoring also allows to define clear ownership of a data_type_t
instance. This e.g. means that an array type owns its base type and the
base type can be freed when the array type itself is freed. The same is
true for signals and class properties, they now own their data type and the
data type can be freed when the signal or property is freed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The current class end label parser rule gets the data type from the
TYPE_IDENTIFIER, casts that to a class_type_t and gets the name from that.
This code was written when the TYPE_IDENTIFIER only provided the data type.
But these days it provides both the data type and the name. Simplify the
code to get the name directly from the TYPE_IDENTIIFER.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There is compatibility code that defines unique_ptr as auto_ptr if the C++
version is before C++11.
But there are already other parts of the codebase that do require C++11 and
the minimum required version to build the project is C++11. So remove the
compat code as it is no longer needed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are C++11 constructs in Icarus at the moment and the plan is to
retain C++11 compatibility until more modern versions are widely available
in the default installation of systems.
Pass `-std=c++11` to the compile to enforce building with C++11, this will
make sure that neither an older nor a newer version is used. E.g. compilers
on some platforms still default to an earlier version of C++11.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to call a void function from a class method.
Check this for both functions defined in the global scope as well as
functions that are methods of the class or a base class.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Calling a void function (or a regular function and ignoring the result)
from within a class method will currently result in an error unless the
void function itself is a method of the same class.
This is because we add the implicit `this` as an object on which to search
for the function and if we do not find it print an error. Change this to
only print an error if the implicit this was not added and it was a method
call on an object identifier.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check for various dynamic array and queue types that their type
compatibility is handled correctly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Icarus allows to pass a value of the element type as an argument to the
dynamic new operator. To allow this the type compatibility check for
dynamic arrays allows both the dynamic array type itself and also the
element type.
This currently leads to a confusing error message if neither type matches.
The error message will say that the passed value is not compatible with the
element type. E.g.
```
real d1[];
int d2[];
d1 = d2;
```
results in
```
error: the type of the variable 'd2' doesn't match the context type.
: variable type=dynamic array of netvector_t:bool signed[31:0]
: context type=real
```
This is slightly confusing. Change the way the error message is reported so
that the context type is the type of the dynamic array and not the element.
With the change the above results in
```
error: the type of the variable 'd2' doesn't match the context type.
: variable type=dynamic array of netvector_t:bool signed[31:0]
: context type=dynamic array of real
```
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog defines different levels of type compatibility.
* Matching
* Equivalent
* Assignment compatible
* Cast compatible
At the moment the `nettype_t` has only one type compatibility test. It is
used to check assignment compatibility when assigning to a dynamic array,
queue or class.
The current implementation rejects a few cases that should allowed and
allows a few cases that should be rejected.
Dynamic arrays and queues are assignment compatible if their element types
are compatible. And two packed types are equivalent if they are both
2-state or 4-state, both signed or unsigned and have the same packed with.
In the current implementation the sign is not considered and instead of
checking if the packed width is the same it checks that the dimensions are
identical.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `netdarray_t` type implements the `packed_width()` method by returning
the packed width of the element type. It is the only non-packed type that
implements the method.
This triggers an assert in the vlog95 backend for tasks with dynamic array
typed parameters. And while the vlog95 backend does not support dynamic
array types it should not result in a crash, just an error message.
The only place that relies on the behavior that the packed width of the
element type is returned is in the vvp backend where variable declarations
are generated. Update that code to query the packed width of the element
type instead and then remove the `packed_width()` implementation for the
`netdarray_t` type.
This fixes the assert in the vlog95 backend. But it is also nicer from an
architectural perspective as this brings the type in line with the other
types in terms of behavior.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The C++ API for `ivl_type_t` has a method to query the total width of a
packed type. This is currently not exported to the C API and the tgt-vvp
backend implements similar functionality by querying the individual
dimensions of a type.
Export the `packed_width()` method to the C API. This allows to remove the
custom implementation from the tgt-vvp backend.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Current regression tests only cover checking for invalid non-blocking
writes to constructs that are valid in Verilog. Add two tests to
additionally cover some SystemVerilog constructs.
* Non-blocking writes to members of a struct typed variable with automatic
lifetime
* Non-blocking writes to class typed variables with automatic lifetime
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `PEIdent::has_aa_term()` method still uses the old `symbol_search()`
and will fail to find the variable if part of the identifier path is a
member select of a variable.
As a result such writes to fields of automatic structs can be classified as
static and it is possible to do non-blocking assignments to them. E.g.
```
task automatic t;
struct packed {
logic x;
} s;
s <= ...; // This fails
s.x <= ...; // This works, but should fail
endtask
```
Switch to the new symbol search to make sure this case is handled
correctly. The new symbol search will correctly handle identifier paths
that have a trailing item after the variable, while the old symbol search
will always return an error in that case.
Note that while it is not allowed to do a non-blocking write to a class
object automatic variable, it is allowed to do a non-blocking write to a
property of a class object that is stored in an automatic variable, as the
non-blocking write is supposed to capture a reference to the object and not
reference the variable. E.g.
```
class C;
int x;
endclass
task automatic t;
C c;
c <= ...; // Not allowed
c.x <= ...; // Allowed
endtask
```
Non-blocking access to class properties is not yet support in
Icarus in general, but the error handling for that needs to be done
somewhere else.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that default values for class methods are handled correctly and it is
possible to omit any argument. Check it for both functions and tasks.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For class function method calls currently only as many arguments as have
been supplied are elaborated. Any trailing arguments that might have default
values are skipped. This will trigger an assertion later on in the vvp code
generator backend.
Fix this by making sure that all arguments of the function are evaluated.
Note that this already works correctly for class task method calls.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to reference a package scoped identifier that has
the same name as a local identifier, but is a different kind of identifier.
* A variable or function identifier from a package scope if it is a
type identifier in the current scope
* A type identifier from a package scope if it is a non-type identifier
in the current scope
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In order to avoid conflicts in the grammar the lexer distinguishes between
identifiers and type identifiers. To correctly classify an identifier the
lexer needs to know in which scope a token is parsed. E.g. when the parser
encounters a package scope operator it calls `lex_in_package_scope()` to tell
the lexer which scope the following identifier should be classified in.
Currently the `lex_in_package_scope()` is only used when a type identifiers
is parsed, but on for normal identifiers. As a result it is not possible to
reference variables or function from a package scope that have the same
name as a type identifier in the current scope. E.g.
```
package P;
int T;
endpackage
module test;
typedef int T;
initial $display(P::T);
endmodule
```
Another problem is that in expressions both type identifiers and signal
identifiers can be referenced. As a result there are two rules in an
expression that can be reduced
* <PACKAGE_TYPE> :: <TYPE_IDENTIFIER>
* <PACKAGE_TYPE> :: <IDENTIFIER>
The way the rules are formulated at the moment the parser has to use token
lookahead to decide which rule to follow before it can reduce the package
scope operator. As a result the lexer detects the token before
lex_in_package_scope() is called and the identifier does not get evaluated
in the package scope, but in the current scope. Which can cause the
identifier to be misclassified. E.g.
```
package P;
typedef int T;
shortint X;
endpackage
module test;
typedef byte X;
initial $display($bits(P::T));
initial $display($bits(P::X));
endmodule
```
Here `P::T` gets classified as a signal identifier and `P::X` gets
classified as a type identifier.
To solve this introduce a common rule for the package scope operator. Using
the same rule everywhere allows the parser to reduce it unconditionally
without using lookahead.
Note that there are additional problems with resolving the type of a scoped
type identifiers in expressions, but this is a prerequisite to solve that.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to declare an unpacked array type with an
unpacked array type as the base type.
Also check that it is possible to declare an signal with an unpacked array
dimension with an unpacked array base type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
It is currently possible to declare an unpacked array with multiple
dimensions. But trying to declare an unpacked array that has another
unpacked array as a base type will result in undefined behavior. E.g.
```
typedef int T1[1:0];
typedef T1 T2[3:0];
T2 x[7:0];
```
To support this recursively unwrap the data type and add the unpacked
dimensions to the signal until the base type no longer is a unpacked array
type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that for a module port with an array type identifier the type is
elaborated in the right scope.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
elab_anet.cc was removed from the build in commit 4a8be3db9c ("Implement
bi-directional part selects."). But the file itself was never removed,
remove it now.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that package scope function calls work with and without arguments as
well as empty positional arguments.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The parser currently only allows package scoped functions to be called if
there is at least one argument. But package scoped functions are the same
as normal functions and it is allowed to call them with no arguments. It is
even possible to pass no value for a positional argument, if the positional
argument has a default value.
Update the parser to handle this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For function calls when calling the PECallFunction() constructor a copy is
made of the argument expression list. This means the original list should
be deleted within the rule.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
If the type of a port is an array type it currently always gets evaluated
in the scope where the port is declared.
But if the type is a typedef it might be declared in a different scope and
must be evaluated in that scope. E.g. the following will declare an array
port with 10 entries and an element type of a 5 bit vector, while it should
declare one with 4 entries and an element type of a 2 bit vector.
```
localparam A = 2;
localparam B = 4;
typedef [A-1:0] T[B];
module test (
T x
);
localparam A = 5;
localparam B = 10;
endmodule
```
This is in part due to array types being given special handling. This was
necessary before because each base type required slightly different
handling and so the base type had to be extracted from the array type.
This has now been consolidated and all data types are treated the same.
The only exception is the vector type which still needs special handling to
support separate definition of port direction and type.
As a result it is possible to remove the special handling of the array
type. This solves the problem of evaluating the type in the wrong scope.
Some special handling needs to be retained though to be able to
differentiate between array dimensions that are part of a type and array
dimensions that are part of port declaration. This is again necessary to
correctly support separate definition of port direction and type. E.g. in
the example below port `x` and `y` get treated slightly differently, even
though the resulting signals will be identical.
```
typedef logic [7:0] T[1:0];
...
input T x;
input [7:0] y[1:0];
```
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to copy empty dynamic arrays and queues.
If the target is a dynamic arrays there are two ways of copying. Through
direct assignment as well as the array new operator.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
An empty dynamic array or queue is represented by a null object in vvp.
Currently when trying to copy such an object results in undefined behavior
in various places. Either hitting an assert or causing a nullptr
dereference.
Make sure that the empty object is handled correctly by treating it as a
special case.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There is nothing special to do for return class objects from a function.
They can be handled the same as other objects such as dynamic arrays and
queues.
But there currently is an assert in the code that handles function calls
assigned to objects that will trigger if the target type is not an queue or
dynamic array.
This is because Icarus allows dynamic arrays to be initialized with a
single value and for that the element with of the dynamic array needs to be
known, so the single value expression can be evaluated correctly.
Since classes can not be initialized from vector expressions the width does
not matter in that case.
Update the code to only query the element width if the target type is an
dynamic array or queue and pass a placeholder value of 1 for the width
otherwise.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For modules with parameters the vlog95 backend generates one module
declaration for each module instance. This is done so that different values
for the module parameters can be supported.
Local parameters are guaranteed to have the same value for all module
instances though. Add support for detecting the case that all module
parameters are local parameters and in that case only create one shared
module declaration. This is similar to what the vhdl backend does.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We differentiate between local and non-overridable parameters
in the frontend to be able to generate better error messages.
For the backend they should both be considered local parameters.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that a packed struct or union with an unpacked array, dynamic array
or queue as a member is detected as an error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Unpacked dimensions for struct or union members are currently silently
discarded. E.g.
```
struct packed { int x[2]; } s;
```
will elaborate successfully as a struct with a non-array int typed field.
This should instead elaborate to an unpacked array of ints typed field. And
subsequently, since unpacked arrays are not allowed in a packed struct or
union, result in an error instead.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The figure_packed_base_type() method can be used to check whether a type is
2-state or 4-state at parse time. The parser no longer cares about the
specific type of a data type. The figure_packed_base_type() function is
no longer used, so remove it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Packed arrays are only allowed of packed base types. Currently whether the
base type is packed is checked before elaborating the base type.
This works as long as the actual type is known before elaboration. But for
example with type parameters the actual type is only known after
elaboration. In order to be able to support type parameters move the check
for whether the type is packed after elaboration.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The parser used to have behavior that was dependent on the
`ivl_variable_type_t` of a signal. It also used the `ivl_variable_type_t`
of a signal to decide whether a signal can be re-declared as part of a
non-ANSI port declaration.
Neither of these is done anymore and most of the reference to
`ivl_variable_type_t` can be removed from the parser. The only thing it is
still needed for is to decide whether a vector type is 4-state or 2-state.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`pform_make_task_ports()` has code very similar to `pform_set_net_range()`.
Use that helper function instead of duplicating the code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
pform_module_define_port() has code very similar to `pform_set_net_range()`.
Use that helper function instead of duplicating the code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Now that pform_set_range() is only used for vector types pass the
vector_type_t as an argument rather than deconstructing the type into range
and signedness.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that all kinds of invalid repeated task port declarations are
detected as errors. They should not crash the application nor should they
result in successful elaboration.
The tests are created for corner cases that previously resulted in
incorrect behavior.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that all kinds of invalid module port declarations, where the
declaration conflicts with previous declarations, are detected as errors.
They should not crash the application nor should they result in successful
elaboration.
The tests are created for corner cases that previously resulted in
incorrect behavior.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that when port direction and data type are declared separately that
an error is reported if the port direction has an explicit range
specification, but the data type has not. This should even be the case if
the data type has an implicit range, e.g `int` or a struct type.
For vector types also check that it is an error if the ranges are not
identical.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that when port direction and data type are declared separately that
an error is reported if the port direction has an explicit range
specification, but the data type has not. This should even be the case if
the data type has an implicit range, e.g `int` or a struct type.
For vector types also check that it is an error if the ranges are not
identical.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
(System)Verilog allows to declare the port direction separate from the
signal declaration. E.g.
```
output x;
integer x;
```
But this is only allowed if the port declaration
* does not have an explicit net type
* does not have an explicit data type
* is a non-ANSI style declaration
For all other cases of port declarations the signal is considered fully
defined and it is not allowed to have a separate signal declaration.
In addition the declared packed dimensions need to match between the port
and signal declaration.
In the current implementation there are a few cases where this is not
handled correctly.
1) It is possible to declare non-ANSI task ports with the same name over
and over again, if it was declared as a signal before the port.
```
task t;
string x;
input logic x;
output real x;
endtask
```
2) It is possible to re-declare non-ANSI input ports of a module that have
a data type, but no explicit net type.
```
module M;
input integer x;
wire integer x;
endmodule
```
3) It is possible to re-declare a ANSI port if it has an implicit data type.
```
module M(output [1:0] x);
reg [1:0] x;
endmodule
```
4) It is possible to declare a vector signal for a scalar non-ANSI task
port.
```
task t;
input x;
reg [7:0] x;
```
To handle all of these correctly refactor signal declaration and lookup a
bit.
The PWire class that represents a signal already has two flags `port_set_`
and `net_set_`. These flags indicate whether a signal has already been used
in a port or signal declaration. A port declaration that includes an
explicit data type is considered both a port and signal declaration.
Use these flags to decide whether it is possible to extend an existing
declaration. E.g. when creating a port without an explicit data type and a
PWire by that name already exists and the `port_set_` flag is not set
extend the existing PWire. On the other hand if the `port_set_` flag is
already set report an error.
Similar for signals but with the `net_set_` flag.
For port declarations with an explicit data type or ANSI style port
declarations it is always an error if a PWire by that name already exists.
This is for both module and task/function ports.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are some tests that use non-ANSI style task port declarations where
the port direction has no packed range specification, but the corresponding
signal declaration has as range specification.
This is not valid, the standard requires the range specification for both
to match.
These tests are currently passing because this error is not detected if the
port direction declaration is scalar.
In preparation for eventually detecting this error set the
`no-io-range-error` flag for these tests. When this flag is set the error
is downgraded to a warning.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The br_ml20150606 regression test uses ANSI style port declarations, but
also re-declares the ports inside module as signals.
This is not valid (System)Verilog, even though the data type in the port
declaration is an implicit type. An ANSI-style port is always fully
defined. This defined section 23.2.2.2 ("ANSI style list of port
declarations") of the SystemVerilog LRM (1800-2017) and section 12.3.4
("List of ports declarations") of the Verilog LRM (1364-2005).
The test was originally added in response to a similarly non-compliant test
in the Yosys test suite, but that test has subsequently been updated to
conform to the standard[2].
Remove the non-compliant test in preparation for adding strict standard
compliance checking on ANSI port redeclarations.
[1] https://sourceforge.net/p/iverilog/mailman/message/34182256/
[2] https://github.com/YosysHQ/yosys/issues/1570
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The default implementation of the virtual method `NetExpr::has_width()`
returns true. There are a few classes that directly inherit from NetExpr
that override the method with the exact same implementation. Remove these.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are no users for the `NetScope::find_enumeration_for_name()` and
`Definitons::enumeration_for_name()` methods. Remove both of them.
The last user was removed in commit 61a088fa78 ("Use elaborate_type()
infrastructure to elaborate signal types").
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The last user of the `make_range_from_width()` was removed in commit
f6042033d0 ("Correctly handle separate port type declaration for
`integer` and `time`").
Remove the function itself as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The last user of the `PExpr::is_the_same()` method was removed in commit
37b60a4c52 ("Clean up interface of the PWire class").
Remove the method.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that default values are support for module port lists.
* For output ports it is supported in both Verilog and SystemVerilog.
* For input ports it is only supported in SystemVerilog.
* For inout ports it is never supported
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Both Verilog (2005) and SystemVerilog support default port values for
variable output ports. SystemVerilog also supports default port values for
input ports. For port declaration lists it is possible to specify the
default value for port identifier.
E.g.
```
module M (
input integer x, y = 1,
output integer z, w = 2
) ...
```
Currently the parser only supports specifying the default value for the
first identifier in the list. Extend the parser to also allow to specify
the default value for identifiers in the list.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a few places where it is possible to provide an optional
initializer in the form of `[ = <expression> ]`.
There are currently multiple rules that implement this behavior as well as
few places with duplicated rules, one with and one without the initializer.
Introduce a common helper rule for optional initializers. This allows to
remove some duplicated code from the parser.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For output port lists with a default value for the first port declaration
all subsequent port declarations are declared as inout ports. This is due
to a small typo when setting the `port_declaration_context` port direction.
Fix this to make sure all ports in the port declaration list are declared
as output ports.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that SystemVerilog sign cast are supported correctly. The regression
tests are modeled after the existing tests for $unsigned/$signed.
They check that
* Width extension is done correctly on the cast expression
* Expressions in the sign cast are evaluated as self-determined
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog supports sign cast where it is possible to change the
signedness of an expression. Syntactical it is similar to width or type
casting, except that the keywords 'signed' or 'unsigned' are used in front
of the cast operator. E.g.
```
logic [3:0] a = 4'b1000;
logic [7:0] b = signed'(a); // b is 8'b11111000;
logic signed [3:0] c = 4'b1000;
logic signed [7:0] d = unsigned'(c); // d is 8'b00001000;
```
As noted by the LRM section 6.24.1 ("Cast operator") applying a sign cast
to an expression is equivalent to calling the $signed() and $unsigned()
system functions on the expression.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that the var keyword is supported in the following contexts
* Module ports (both ANSI and non-ANSI)
* Module variable declarations
* Package variable declarations
* Task and function ports
* block variable declarations
* for loop variable declarations
Also check that it is an error to use the var keyword in a for loop without
an explicit data type, as that is not allowed by the standard.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog adds the `var` keyword that can be used to declare a signal
as a variable.
In contexts where a signal is always a variable it is purely optional and
it makes no difference whether it is specified or not. This is in
* for loop variable declarations
* task and function port declarations
For variable declarations as block items when `var` is used it is possible
to omit the explicit data type and use a implicit data type instead. E.g.
all of the following are valid.
```
var x;
var signed y;
var [1:0] z;
```
For module input and output ports the `var` keyword can be used in place of
the net type. It can be combined with either an implicit or explicit data
type.
E.g.
```
input var x
output var [1:0] y
```
inout ports can not be variables and will be reported as an error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Refactor the variable lifetime parser rules so that instead of having too
rules, one with lifetime and one without, there is a single rule where the
lifetime is an optional element.
This helps to avoid a combinatorial explosion of parser rules once we
add `var` support.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the parser can recover from `integer` or `time` variable
declarations, but not for variables of other types. Refector the parser
rules so that it can recover for all variable types as well as events.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows input ports to be variables. If something is connected
to the input port it will be converted to an unresolved wire.
This is handled the same as having a continuous assignment on a
SystemVerilog varibale.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
If the parameter has no explicit type, the type is inferred from the RHS
expression. The first time the parameter is evaluated, the RHS hasn't yet
been elaborated, so the type is unknown. This causes the evaluation to be
performed by NetScope::evaluate_parameter_logic_, which correctly handles
both logic and real types. However, on subsequent evaluations of the
parameter, the expression type is now known, so the evaluation was being
performed by NetScope::evaluate_parameter_real_. This function requires
the parameter to have an explicit type.
For now, rather than add more code to NetScope::evaluate_parameter_real_
to handle an implicit type, force NetScope::evaluate_parameter_logic_ to
be used whenever we have an implicit type. This should probably be reworked
if support for more complex types is added.
Without this fix, ivlh_textio was failing at step 11 where the time is read from the file. This was because clang happens to put period directly after the units buffer on the stack. sscanf writes the terminating NUL overwriting the low byte of period, which is 100, so it returns 0.
Example clang warning fixed:
warning: 'sscanf' may overflow; destination buffer in argument 4 has size 2, but the corresponding specifier may require size 3 [-Wfortify-source]
Both the `vvp_fun_signal_real` and `vvp_fun_signal_string` classes
implement a `size()` method that returns 1. There are no users of these
methods, remove them.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add regression tests for the following types partial writes for both
2-state and 4-state vectors.
* Non-blocking
* Blocking
* Blocking event control
Check that all in-bounds partial writes, partial out-of-bounds and
full out-of-bounds all works as expected.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Writes to 2-state arrays currently only support full writes. If the write
is a partial write it will trigger an assert. E.g.
```
int a[3:0]
int i = -1;
a[i+:8] = 8'h0; // Triggers assert
```
Add support for partial writes by doing a read-modify-write in the same way
as for 4-state arrays.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `%store/vec4a` instruction does not handle partial of full
out-of-bounds writes to a vector array element. Trying to do so will
trigger an assert. E.g.
```
integer a[3:0];
integer i = -10;
a[0][i+:8] = 8'h0; // Triggers assert
```
For fully out-of-bounds writes the write should be skipped, for partial
out-of-bounds writes the value needs to be resized to be within the bounds
of the vector. Use the `resize_rval_vec()` helper function to implement
this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a few functions that handle implement different kinds of vector
writes that have to handle that the assigned value partially or completely
out-of-bounds.
Each function has similar, but not identical, code for this, sometimes with
small bugs for corner cases.
Add a helper function that takes care of handling of updating the width and
offset of the assigned value if necessary.
This ensure consistent and correct behavior and allow to remove some
duplicated code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `%assign/vec4/a/{d,e}` instructions, when checking for a full
out-of-bounds write on the low side, uses the target signal width, while it
should use the assigned value width.
This can lead to a fully out-of-bounds write to be assumed to be a partial
out-of-bounds access, which will trigger an assert later on.
E.g.
```
integer a[1:0];
integer i = -4;
a[0][i+:4] <= 4'h0; // Triggers assert
```
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that multiple events can be used in a non-blocking event control
assignment. The assignment should happen if either of the events trigger.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When multiple events are used in a non-blocking event control they need to
be combined into a single event using `event/or`.
The generated `event/or` statement is missing the trailing semicolon and
newline, which results in parser error when vvp tries to run.
E.g.
```
event e, f;
integer x;
x <= @(e or f) 10;
```
Add the missing semicolon and newline to fix this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that a non-blocking event control assignment works as expected to a
lvalue concatenation. All values that are part of the concatenation should
only be assigned after the event triggers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that non-blocking event control assignments works on an array part
select if the part select index is not an immediate value.
This is a copy of the nb_ec_array_pv test, but using variable indices
instead of immediate values.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
A non-blocking event controlled assignment consists of 3 steps.
* Setup event
* Perform assignment
* Clear event
This works fine if the lvalue is a singular value. If the lvalue is a
concatenation multiple assignments are generated and the event is cleared
after each assignment. As a result only the first assignment is event
controlled. All other assignments will be regular non-blocking assignments.
E.g.
```
reg x, y;
event e;
{x,y} <= @e 2'b11;
$display(x, y); // x will be 1'b1, y will be 1'bx
```
To resolve this the event needs to be cleared after all assignments have
been done. This requires changes to both tgt-vvp and the vvp runtime.
tgt-vvp is updated to only insert a single `%evctl/c` instruction for each
event controlled non-blocking assignment.
The vvp runtime is not updated to implicitly clear the event in the
`%assign/vec4/e` instruction and instead rely on the explicit `%evctl/c`.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
VVP array assignment operations expect the array element index to be in
index register 3.
For array element assignments with a dynamic part select the array index
gets moved into a temporary index register and has to be moved into
register 3 after evaluating the dynamic part select. This is currently not
done non-blocking event control assignments. This causes the write to go to
the wrong array element. It will go to whatever value is in the register 3
from previous operations.
```
reg [3:0] a[1:0];
integer i = 0;
event e;
a[1][i+:2] <= @e 2'b10; // Will write to the wrong array element
->e;
```
Make sure to move the temporary register to register 3.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Both the `%concati/vec4` and `%pushi/vec4` instructions need to construct a
vector from the immediate value encoded in the instruction. Currently both
these instructions have a custom implementation for that.
Remove the custom implementations from those functions and use the
`get_immediate_rval()` helper function. This removes a bit of duplicated
code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `%cmp/ws` and `%cmp/wu` instructions compare two index registers. They
are currently unused. Since the index registers are not used for data there
is not really a need to compare them. Values can be compared before loading
them into an index register.
So remove these two instructions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `%mov/wu` instruction moves data from one index register to another.
The instruction is not used. It also does the same as `%ix/mov`. So remove
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `recv_vec{4,8}_pv()` functions are used to implement a partial write to
a vector. As parameters they take both the value and the width of the
value.
All callers of of these functions pass `val.size()` or a variation thereof
as the width of the value. And all implementations that do anything with
the data have an assert that `val.size() == wid`.
Remove the `wid` parameter from these functions and just use `val.size()`
directly where needed. This allows to simplify the interface and also
to remove the asserts.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that assignment operators on real array entries are supported.
Also check that
* out-of-bounds indices work as expected
* it works after a comparison that set vvp flag 4 to 0
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The basic structure for supporting assignment operators on real arrays
exists in the tgt-vvp backend. But there are a few problems, most
importantly it generates the wrong instruction for loading data from the
real array.
The instruction it uses is `%load/reala`, but that instruction does not
exist, the correct name is `%load/ar`.
In addition to this there are a few minor problems.
* Out-of-bounds access on the array triggers an assert
* Missing `%pop/real` instruction when skipping a write due to
out-of-bounds access
Address these so assignment operators are supported on real array entries.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that the signedness of a struct member is properly handled when being
passed to a system function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Access to members in packed struct fields is internally implemented using a
part select.
vvp has a special syntax for passing a part select of a vector to a system
function. This special syntax assumes that the part select is unsigned like
it is for normal Verilog part selects.
As a result passing a signed struct member to a system function will
interpret it as unsigned.
Add a check to make sure that the expression is actually unsigned. If it is
not fall back to evaluating the expression on the vector stack and pass the
value on the stack to the system function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that an assignment operator on an out-of-bounds array element works
as expected. The out-of-bounds access should leave the array unmodified,
but the right-hand side must be evaluated regardless.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For an out-of-bounds assignment operator on an array element an assert is
hit if the element width is great than 32.
Remove the assert and make sure that this case is handled correctly by
using the `%pad/s` instruction to extended the X value to the correct
width.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
If the index of an array access is known to be out-of-bounds during
elaboration it is replaced with 'x. In the tgt-vvp backend that is handling
compressed array assignments there is an assert() that triggers if the
index is an undefined immediate.
There is already an existing code path that is capable of handling
out-of-bounds access. Remove the assert and set the index to ULONG_MAX to
trigger taking the out-of-bound access path.
On this out-of-bounds path the write to the array is skipped. But this
leaves the result on the vector stack. Insert the `%pop/vec4` instruction
to make sure it is removed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Parameters with real values are possible in Verilog, but not in the VCD
format, so lie a little and call them "real" objects. Otherwise, we can
treat them like constants and it works out, at least for gtkwave.
Check that for the following operations the load or store is not skipped
after a operation that sets vvp flag 4.
* Assignment to immediate indexed real array entry
* Assignment operator on immediate indexed vector array entry
* Assignment operator on dynamic vector part select
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The operator assignment on dynamic part selects uses the `%store/vec4`
instruction to store the value. This instruction will skip the assignment
if flag 4 is set. This is for handling the case where the index is
undefined.
Since the left hand side of the assignment is an arbitrary expression it
can change the flag. The implementation handles this by making a copy of
the flag and restoring it before executing the `%store/vec4` instruction.
The flag is set by the `%ix/vec4` instruction when loading the index
register. But the copy of the flag is made before that and just picks
up the flag that was stored by previous expressions. This can cause
the store to be skipped when it shouldn't.
E.g. in the following code the increment will be skipped. Flag 4 is used
from the `a == 0` comparison, rather than from computing the part select
index.
```
int a = 0;
if (a == 0) begin
a[a+:2] += 1;
end
$display(a); // Will print 0, should print 1
```
Fix this by moving the copy of the flag after the `%ix/vec4` instruction.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The vvp `%load/vec4a` instruction will skip the load if vvp flag 4 is set
and return 'x. This is meant for handling the case where the index is
undefined.
For assignment operators on array entries, when the index is an immediate
value, vvp flag 4 is not cleared before the load instruction. If a previous
instruction set flag 4 it load yield 'x.
E.g. for the following sequence `x[0]` should be `11`, but will be `'x`.
```
integer x[10];
logic a = 1'b0;
x[0] = 10;
if (a == 0) begin
x[0] += 1;
end
```
Properly clear the flag before the load instruction to handle this
correctly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When assigning a value to a real typed array entry the vvp `%store/reala`
instruction. This instruction will skip the store if the vvp flag 4 is set.
This is to handle the case where the index is undefined.
When the index into the array is an immediate value the flag 4 is not
cleared. If a previous instruction set flag 4 the store will be skipped.
E.g. for the following r[0] will remain 0.0 since the assignment to it is
skipped.
```
integer a = 0;
real r[1:0];
if (a == 0) begin
r[0] = 1.23;
end
```
Fix this by using the `draw_eval_expr_into_integer()` helper function to
evaluate the index into a word register. The function correctly handles all
the special cases.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Writing parameters into VCD files makes the values available to waveform
tools. This can be done easily enough by writing out a $dumpadd section
at the beginning of the file that sets the parameter values. We don't need
to track the values over change, because by definition they do not change.
This changes the typical vcd output as well, so a few of the regression tests
need to be adjusted to account for this.
Also, while tracking this down, found and fixed the vvp/README.txt documention
for the .param/x records.
Check that out-of-bounds access on a dynamic array or queue works and
returns the correct value.
* 2-state vectors: '0 with the element width
* 4-state vectors: 'x with the element width
* reals: 0.0
* strings: ""
Note that the 2-state test currently still fails as out-of-bounds access on
a 2-state vector incorrectly returns 'x.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Commit e1870acfac ("Return the correct value when a queue or darray
references an undefined element") added support for specifying the width of
the vector elements stored in a queue or dynamic array, so that an
out-of-bounds access can create a word with the right width.
To get the element width of a queue or dynamic array it uses the
`packed_width()` method. But this method is only implemented for
`netqueue_t` and returns always 1 for dynamic arrays. As a result
out-of-bounds access on a dynamic array will push a vector of the wrong
width onto the stack if the vector element is wider than 1 bit. This will
usually trigger an assert in vvp.
Fix this by moving the `packed_width()` method implementation from
`netqueue_t` to its base class `netdarray_t` so that it works for all types
of dynamic arrays.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The custom `svector` class is essentially a subset of `std::vector`. There
is no inherent advantage to using `svector`. Both have the same memory
footprint.
`svector` was designed to be of static size, but there are a few places in
the parser where it has to grow at runtime. Handling this becomes a bit
easier by switching to `std::vector` since it is possible to use its
methods which take care of resizing the vector.
This also allows to remove the unused parameter of the `lgate` struct
constructor, which was only needed for compatibility with `svector`.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The get_signed() method for the netqueue_t class is identical to that of
its base class netdarray_t.
Remove the redundant re-implementation of the method.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Ever since the conversion to use a stack for vectors `draw_eval_bool64()`
has been unused. The last caller of `draw_eval_bool64()` was removed in
commit e4b862f3d1 ("Clean up vector handling dead code.").
Remove `draw_eval_bool64()` and related functions as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that scalar typed parameters are handled correctly. Make sure the
width of the parameter only depends on the type and not on the value
assigned to the parameter.
Same for parameters with a 1-bit range specification.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Parameters without any type or range specification inherit the type from
the value that has been assigned to it. Similarly a parameter with just an
`signed` or `unsigned` keyword will inherit its range from the value
assigned to it.
In the current implementation any vector type parameter that does not have
a range specification inherits the type form the assigned value. That
includes parameters with an explicit scalar vector type. E.g.
```
parameter bit X = 10
```
Make sure that a parameter only uses the width from the assigned value if
the parameter does not have an explicit data type.
To support this we need to remember whether a `netvector_t` was declared as
an explicit or implicit data type. Currently this information is only
available on the unelaborated `vector_type_t`.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There is currently a restriction in the vvp code generator backend that
throws an assertion when generating wire access for a multi-dimensional
real array.
But there is nothing special about multi-dimensional arrays. In vvp arrays
are in canonical form. Meaning they only have a single dimension and the
conversion form multi to single dimension is done in the higher layers.
Remove the assert to allow multi-dimensional real arrays.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that using a class new operator on a variable that is not of a class
type results in an error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Using a class new operator on a non-class variable should result in an
error. At the moment when using a class new operator on a dynamic array or
queue will result in an segmentation fault. This is because the
implementation assumes that the left hand side is of a class type.
Add a check in the class new operator implementation that the type of the
left hand side is a class. Report an error if it is not.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The lgate struct has its own fields for tracking file and line number,
while everything else that has this information attached inherits from the
LineInfo class.
Make lgate also inherit from LineInfo for consistency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are some cases where the r-value for an assignment just can't
be elaborated. Instead of segfaulting on the error, handle it by
assuming that the nullptr came from an error message, and ignore it
going forward.
PECastType currently uses the unelaborated data type to make the decision
how to implement the cast. The unelaborated data type is provided by the
parser and this works as long as the parser knows the data type.
But for example with type parameters the actual data type is not known
until elaboration. In preparation for supporting type parameters make sure
to only use the elaborated type in the PECastType implementation.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that module ports can have the shortreal data type.
Note that SystemVerilog does not allow nets to be of shortreal type.
Supporting net ports with a shortreal type is a Icarus extension.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently there is a restriction in the parser that rejects `shortreal`
typed module ports. And while at the moment `shortreal` signals are
implemented as `real` typed signals, which is not standard compliant, there
is nothing special about module ports in this regard.
Note that support for `shortreal` (and `real`) nets is an Icarus extension,
but ports can also be variables, in which case a shortreal port is allowed
by the LRM.
`shortreal` variables and nets are allowed everywhere else. There is no
good reason to not allow them for module ports, so remove the restriction.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `pform_attach_discipline()` function creates a signal using
`pform_makewire()` and then looks it up by name.
`pform_makewire()` now returns the signal, so use that directly and skip
the look-up by name.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `pform_set_data_type()` function is used to set the data type as well
as attributes on a list of signals. Currently the signals are passed as a
list of signal names and then the function looks up the actual signals from
the names.
Refactor the code to directly pass a list of signals. This will allow to
skip the look-up by name.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `pform_set_net_range()` function currently looks up a signal by name.
But in all places where it is called the reference to the signal is already
available.
Refactor the code to pass the signal itself, rather than the signal name, to
`pform_set_net_range()`. This allows to skip the look-up by name.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`pform_make_var_init()` calls `pform_get_wire_in_scope()` but never uses
the result other than checking that the signal exists. But we already know
that the signal exists since we only call `pform_make_var_init()` for a freshly
created signal.
Remove the unnecessary signal look-up by name.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows to declare signals of nested unpacked types. E.g. a
queue of dynamic arrays.
This is currently not supported by Icarus. Add regression test nevertheless
to check that this is reported as a non-supported construct and does not
result in random crashes.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that the maximum size of a bounded queue is properly handled when
being used as the return type for a function.
Elements beyond the maximum size should be ignored.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are currently two implementations for elaborating unpacked array
types. One that is used when elaborating a signal with an unpacked array
type and one that is used everywhere else using the elaborate_type()
infrastructure.
The elaborate_type() implementation is less complete and for example does
not support bounded queue types.
Consolidate both into a single implementation to reduce duplicated code and
get consistent behavior. This for example makes sure that the maximum queue
size is respected when used as a function return type.
Nested data structures of arrays, dynamic arrays or queues are not yet
supported. In the current implementation when encountering such a type an
assert will be triggered and the application crashes. In the new
implementation an error message will be printed without crashing the
application.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that expressions within assignment patterns are evaluated as if they
were assigned to a variable with the same type as the base type of the
assignment pattern target.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The expressions within an array assignment pattern should be evaluated in a
context that is equivalent to an assignment to a variable of the element
type of the l-value array.
This is defined in section 10.9.1 ("Array assignment patterns") of the LRM
(1800-2017).
At the moment the values in an assignment pattern are evaluated in a self
determined context, which can lead to incorrect behavior.
Use the existing `elaborate_rval_expr()` function, which is meant for
elaborating assignments, to elaborate the assignment pattern values.
This solves the following issues:
* implicit width conversion (including sign extension)
* implicit type conversion (e.g. real to vector)
* math operators that depend on the target width (e.g. addition)
* use of expressions that require `test_width()` to be called. (e.g.
unary operator)
* use of concatenations
* use of named constants (e.g. parameters or enums)
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `elaborate_rval_expr()` function takes a `data_type_t`, a
`ivl_variable_type_t` and a `width` parameter. In most places the
ivl_variable_type_t and width are directly derived from the data_type_t.
This slightly simplifies the code.
The only place where this is currently not possible is when assigning to a
compound expression like a concatenation, e.g. `{a,b} = c;`.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
`pform_set_reg_idx()` is always called right after `pform_makewire()`. Move
it into the function. This avoids the extra lookup that
`pform_set_reg_idx()` does to get the PWire from the name.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a few parameters for `pform_makewire()` and related functions
that always get passed the same value.
* port_type is always NetNet::NOT_A_PORT
* attr is always 0
Remove these parameters.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that a queue type is supported for the return type of a function.
Make sure that the queue is not cleared in between invocations for
non-automatic functions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the elaboration function for unpacked array types prints an error
for queues that they are not allowed inside classes. And while this error
gets triggered when declaring a property with a queue type, it also gets
triggered for other places that uses a queue type, e.g. a function return
type. The only exception is signals which uses a different internal code
path when elaborating queue types.
Move the error message, that is class property specific, to the class
property elaboration. This also makes sure that the error messages
references the line where the property is declared and not the line where
the type is declared.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Dynamic arrays and queues can be implicitly cast between each other. At the
moment this only works if the right hand side is a signal or assignment
pattern.
But this should be possible for other r-value expression that returns a
queue or dynamic array type. E.g. function calls or class properties.
Since the expr_type() method is defined for all NetExpr objects we can use
that and do not have to cast to NetESignal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This will allow to generate error messages that point to the right line if
there is something wrong or not supported in a class property declaration.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The LineInfo class defines a copy-constructor, but relies on the default
copy-assignment operator.
In newer versions of C++ this deprecated and modern compilers generate a
warning about this. A class must either use the default copy-constructor
and default copy-assignment operator or provide a user defined version of
both.
Since the current user-defined copy-constructor for LineInfo does the same
as the default copy-constructor, remove the custom one and rely on the
default constructor.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `%store/dar/...` and `%store/qdar/...` instructions are used to load a
value into an entry in dynamic array or queue. These instructions will skip
the load if VVP flag 4 is 1.
For assignment pattern initialization these instructions are used to load
the value of the individual assignment pattern expressions into the dynamic
array.
For queues flag 4 is never cleared when generating the code for the
assignment pattern. This means the initialization might be skipped
depending on what value the flag had before.
```
int a = 1;
int q[$];
a = a == 1;
q = {1, 2, 3, 4};
```
For dynamic arrays it is cleared once in the beginning. But each item in
the assignment pattern can be an arbitrary expression. Evaluating the
expression can cause the flag to get overwritten. E.g. the following code
will skip the assignments.
```
int a = 1;
int d[];
d = {a ? 1 : 1, 2, 3, 4};
```
To fix these issues make sure that the flag is cleared after evaluating
each initialization expression and before executing the `%store/...`
instruction.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `pform_set_param_from_type()` function is not used. The last user was
removed in commit 16646c547c ("Rework parsing of parameter types").
Remove the function itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that the signedness of class properties is handled correctly
* When sign extending
* When passing as a value to a system function
Check this for both when accessing the property from within a class method
as well as accessing it on a class object.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that the signedness of the return value of methods is handled
correctly.
* When sign extending
* When passing as a value to a system function
Check this for both methods on user defined class as well as built-in
methods on SystemVerilog types.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The signedness of an expression can change depending on its context. E.g.
for an arithmetic operation with one unsigned operand all operands are
treated as unsigned.
This is currently not considered when accessing class properties. This can
lead to incorrect behavior with regards to sign extension.
E.g. the following will print 4294967295 rather than 65535.
```
class C;
shortint x = -1;
endclass
...
C c = new;
$display(c.x + 32'h0);
```
Furthermore the return value is not expanded to the width of its context.
This can cause vvp to crash with an exception when it expects a vector on
the stack to have a certain width. E.g.
```
class C;
shortint x = -1;
endclass
...
C c = new;
int x;
bit a = 1'b1;
x = a ? c.x : 64'h0;
```
Solve both of this by using `pad_to_width()` on the property expression if
it is a vectorable type. Since any identifier, not just class properties,
need to have this done insert this on the common path and remove the
`pad_to_width()` call on individual paths.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The signedness of an expression can change depending on its context. E.g.
for an arithmetic operation with one unsigned operand all operands are
treated as unsigned.
For methods, both on built-in SystemVerilog types as well as user defined
classes, this is currently not considered. This can lead to incorrect behavior
if the value is sign extended.
E.g. the following will print 4294967295 rather than 65535.
```
shortint q[$];
q.push_back(-1);
$display(q.pop_front() + 32'h0);
```
Furthermore the return value is not expanded to the width of its context.
This can cause vvp to crash with an exception when it expects a vector on
the stack to have a certain width.
E.g.
```
int d[];
longint x;
bit a = 1'b1;
x = a ? d.size() : 64'h0;
```
Solve both of this by using `pad_to_width()` on the method return value if
it is a vectorable type. Since any function call, not just methods, needs
to have this done to its return value insert this on the common path.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When calling a queue method without parenthesis it gets elaborated through
the PEIdent path. On this path the type, width and signdess are not
reported for the method call. This leads to incorrect behavior in contexts
where those are important.
Correctly report the type, the same as when the method is called with
parenthesis.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The result for the built-in methods for the SystemVerilog types is
currently always unsigned. This can lead to incorrect behavior if the value
is sign extended or passed as an argument to a system function (e.g.
$display).
For most built-in methods this does not matter, since even though they have
a signed return type, they will not return a negative value. E.g. the
string `len()` or queue `size()` functions.
It does make a difference though for the queue `pop_front()` and
`pop_back()` methods. Their return type is the element type of the queue.
If the element type is signed and the value in queue is negative is will be
handled incorrectly.
E.g. the following will print `4294967295` rather than `-1`.
```
int q[$];
q.push_back(-1);
$display(q.pop_front());
```
To correctly support this consistently assign the actual data type of the
built-in method's return value to the `NetESFunc`, rather than just the width
and base type. The width, base type and also the signedness can be derived
from the data type.
Note that this only fixes the default signedness, but not the case where
the signedness of the expression is changed by its context (e.g. in
arithmetic expression). Handling this will require some additional work.
Also note that assigning the actual data type is also required to support type
checking on the return value, e.g. as needed for enum types.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a couple of different NetNet constructors for different data
types. They are all very similar, consolidate them into a single
constructor taking a ivl_type_t.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that the behavior of the Verilog AMS `abs()` function is correct when
its argument is a function call. Check this for both vector as well as real
types.
This test is largely a copy of the existing vams_abs2 test, just replacing
the identifier argument with a function call argument.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently a `vector_type_t` with the base type set to `IVL_VT_REAL` is used as
the data type for real type signals. But there is also the `real_type_t` data
type, which is used as the data type for function return types and class
properties.
Move signals also over to using `real_type_t`. This ensures consistent
behavior between all sorts of constructs with a data type, makes sure that
`vector_type_t` is only used for vector types.
It also allows to eventually differentiate between `real` and `shortreal`
at the elaboration stage. Currently this information is discarded by the
parser.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
reals are both signed and scalar. But the real_type_t currently reports as
neither.
This isn't much of a problem because most real signals are implemented
using netvector_t with the base type set to IVL_VT_REAL, for which the
signedness is correctly reported. Function return values and class
properties use the netreal_t as their data type, but most places that work
with reals check the base type and assume that the value is signed when the
base type is real.
The only place where this really makes a difference at the moment is the
Verilog-AMS function when being passed a function call as its argument. In
that case the `abs()` function will be optimized away and a negative value
will be passed through as negative.
But going forward netreal_t is also going to be used for the data type of
real type signals.
To fix the `abs()` issue and to be ready to switch real signals over to
using netreal_t as their type implement the appropriate methods on
netreal_t.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently only the netvector_t type implements the get_scalar() method. To
check whether a type is scalar it is first cast to netvector_t and then the
method is called.
But there are other types, such as areal that can also be scalar. To
support indicating that a real type is scalar add a virtual get_scalar()
method to ivl_type_s, which is the base class for all types.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The compiler normally optimises away the enclosing block statement
if a block only contains one statement. But this is not valid for
a fork/join_none block.
Check that static class properties can be accessed for read and write and
that they are shared between all instances of a class type.
Check that this works for the following 3 cases
* accessing the static property in a class function or task
* accessing the static property in a class function or task using `this`
* accessing the static property on a class object instance
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Assigning a value to a static class property in a class task or function
will currently not write to the static signal, but instead to an otherwise
invisible per instance property. E.g. the example below will print 0 when
the task `t` is called.
```
class C;
static int i;
task t;
i = 10;
$display(i);
end
endclass
```
Since static class properties are implemented as normal signals just
fallback to the default signal handling when an assignment to a static
class property is detected.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that constant recursive functions are supported. Check both Verilog
style using assignments to the implicit function return signal and
SystemVerilog style using `return`.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a regression test that checks that recursive functions using a `return`
statement work correctly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
A `return` statement in a function gets translated into a vvp `%disable`
instruction. This works fine as long as no recursion is involved. The
`%disable` instruction will stop execution of all active threads of a
particular scope. For recursive functions this means as soon as the inner
most function returns all containing outer function calls get disabled as
well. This results in incorrect behavior.
To make recursive functions using the `return` statement work use the new
vvp `%disable/parent` instruction. This instruction will only disable the
closest thread in the thread hierarchy that matches the target scope.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `%disable` instruction will stop the execution of all active
threads of a specific scope. This is what is required to implement
the semantics of the Verilog `disable` statement.
But it is not suited to implement the SystemVerilog flow control
statements such as `return`, `continue` and `break`. These only
affect the thread hierarchy from which it is called, but not other
concurrently running threads from the same scope.
Add a new `%disable/flow` instruction that will only disable the thread
closest to the current thread in the thread hierarchy. This can either be
the thread itself or one of its parents. This will leave other concurrent
threads of the same scope untouched and also allows function recursion
since only the closest parent thread is disabled.
Note that it is not possible to implement this using `%jmp` instructions
since a block in a function with variable declarations will be its own
sub-thread, but using flow control instructions it is possible to exit from
that thread to the parent scope, which is not possible with `%jmp`
instructions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Embed the Icarus Verilog documentation, and format it so that the
Sphinx tools can process it into html or other formats. This will
make the documentation easier to keep up to date with the actual
software.
Check that it is not possible to declare a variable in a package without an
explicit data type for the variable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Variable declarations in packages need an explicit data type. Omitting the
data type or using just packed dimensions is not valid syntax. E.g. the
following should not work.
```
package P;
x;
[1:0] y;
endpackage
```
The current implementation does accept this tough. To fix this update the
parser to only allow explicit data types for package variable declarations.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This simplifies the code by making it independent of the size of 'long', and
fixes the behaviour of urandom_range when the upper limit is > 0x7fffffff.
Check that it is possible to declare the type separately from the direction
for non-ANSI integer, time and atom2 ports. Check that it is possible to
both declare the type before and after the direction.
For integer, time and atom2 types the range specification on the port
direction declaration should be empty, rather than the implicit packed
dimension of the integer type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When using non-ANSI style port declarations it is possible to declare the
port direction and the data type for the port in separate statements. E.g.
```
input x;
reg x;
```
When using packed array dimensions they must match for both declarations.
E.g.
```
input [3:0] x;
reg [3:0] x;
```
But this only applies for vector types, i.e. the packed dimension is
explicitly declared. It does not apply to the `integer` and `time` types,
which have an implicit packed dimension.
The current implementation requires that even for `integer` and `time`
types the implicit dimension needs to be explicitly declared in the port
direction. E.g. the following will result in a elaboration error
complaining about a packed dimension mismatch.
```
module test;
output x;
integer x;
endmodule
```
Currently the parser creates a vector_type_t for `time` and `integer`. This
means that e.g. `time` and `reg [63:0]` are indistinguishable during
elaboration, even though they require different behavior.
To fix let the atom2_type_t handle `integer` and `time`. Since it no longer
exclusively handles 2-state types, rename it to atom_type_t.
This also fixes a problem with the vlog95 target unit tests. The vlog95
target translates
```
module test(output integer x);
endmodule
```
to
```
module test(x);
output x;
integer x;
endmodule
```
which then fails when being elaborated again. There were some regression
tests that were failing because of this that will now pass.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When using non-ANSI style port declarations it is possible to declare the
port direction and the data type for the port in separate statements. E.g.
```
input x;
reg x;
```
When using packed array dimensions they must match for both declarations.
E.g.
```
input [3:0] x;
reg [3:0] x;
```
But this only applies to vector types, i.e. the packed dimension is
explicitly declared. It does not apply to the atom2 types which have an
implicit packed dimension.
The current implementation requires that even for atom2 types the implicit
dimension needs to be explicitly declared in the port direction. E.g. the
following will result in a elaboration error complaining about a packed
dimension mismatch.
```
module test;
output x;
byte x;
endmodule
```
Currently atom2_type_t's are deconstructed into base type, range and
signdness in the parser. That data is then passed to the signal
elaboration, which will then construct a netvector_t from it. This makes it
impossible to e.g. differentiate between `bit signed [31:0]` and `int`
during elaboration.
Instead of breaking the data type apart pass it as the data_type_t of the
signal and use the elaborate_type() method in the signal elaboration to
generate the netvector_t.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to both declare and call class constructors
without using parenthesis after the `new` keyword.
Check that a non-ANSI port for a class constructor results in an error.
Check that it is possible to invoke a class task through a implicit class
handle (`this` or `super`) without using parenthesis after the task name.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
It is possible to call a class method without parenthesis if no arguments
are specified.
At the moment this works when calling a class method by name. But when
using the implicit class handle `this` or `super` it does not work.
Add support for this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Class constructors can be declared without parenthesis after the `new` when
no arguments are required. Just like for normal function.
In a similar way the base class constructor can also be invoked without
parenthesis after the `new`.
```
class C extends D;
function new;
super.new;
endfunction
endclass
```
Add support for this by making the parenthesis optional in the parser.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Class constructors don't allow for non-ANSI ports. E.g. the following is
not valid.
```
class C;
function new();
input int i;
endfunction
endclass
```
The parser will currently accept this, but otherwise ignore the non-ANSI
port. Modify the parser rules so that this is a syntax error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a few places in the grammar that follow the pattern of
`implicit_class_handle '.' hierarchy_identifier` and then splice the two
identifier paths into a single one. Factor this into a common helper rule
to avoid duplicated code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a few places in the grammar where it is possible to specify a
argument list in parenthesis or nothing. E.g. a task invocation.
```
task t(int a = 10);
endtask
initial begin
// All 3 are valid syntax
t(1);
t();
t;
end
```
Factor this out into a common rule to be able to remove some duplicated
code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a few places in the grammar where it is possible to specify a
task/function port list in parenthesis or nothing. E.g. task and function
prototypes. Factor this out into a common rule to be able to remove some
duplicated code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that for typedefs of array, dynamic array and queue types the base
type is elaborated in the right scope. There are separate tests for vector
base type and other base types since these take different paths internally.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The base type of an array type needs to be elaborated in the scope where
the array type is declared. At the moment it is elaborated in the scope
where the signal is declared, which can cause incorrect results.
E.g. in the example below the width of the array base type would be 4
instead of 8.
```
localparam A = 8;
typedef reg [A-1:0] T[1:0];
module test;
localparam A = 4;
T x;
endmodule
```
If an unpacked array type is specified use the scope of the array type as
the default scope for the base type. Note that the base type can still be a
typedef in a different scope than the array scope, but we need to start
searching for it in the array scope.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the string containing the current source file path to derive the
object file name, not the string containing the space-separated list
of source files.
(thanks to DavidC-75 for pointing out the error)
Previously both ':' and ';' were recognised as path separators on all
platforms, but ':' can't be used in Windows. So now we only recognise
';' when running in Windows and ':' when running in any other OS.
Check that the behavior for all sorts of base types for enums is correctly
implemented. Both for valid as well as invalid base types.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The base type for an enum type can be a type identifier for a typedef as
long as it resolves to a vector or integer type with at most one packed
dimension. This is described in section 6.19 ("Enumerations") of the LRM
(1800-2017). E.g.
```
typedef bit [3:0] T;
enum T {
A
} e;
```
Add support for this by allowing to specify a type identifier as the base
type for an enum in the parser. During elaboration it is checked whether
the type identifier resolves to a valid enum base type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to create a typedef of an array type that shadows
an existing typedef in a higher level scope.
Also check that it is possible to create a typedef in a class scope that
shadows an exiting typedef in a higher level scope.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
It is possible to declare a new typedef that shadows an existing typedef in
a higher level scope. E.g.
```
typedef int T;
class C;
typedef real T;
endclass
```
In the current implementation this works for scopes that are not class
scopes.
Update the parser to also support this in class scopes by re-using the
existing parser rule that is used for the other scopes.
Reusing the existing rule also adds support for class forward typedes
inside classes.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
It is possible to declare a new typedef that shadows an existing typedef in
a higher level scope. E.g.
```
typedef int T;
module M;
typedef real T;
endmodule
```
In the current implementation this only works as long as the new type is
a not an array type.
Update the parser to allow to specify unpacked dimension when overwriting
a typedef from a different scope.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to have multiple instances of a module
that declares a class and that the class in each module instance
is a unique type that can have dependencies on module parameters.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For classes declared inside a module each module instance creates a new
unique class type. These types are not compatible to each other. This is
necessary since module parameters can change the class implementation.
This is defined in section 6.22 ("Type compatibility") of the LRM (1800-2017).
In the current implementation when a class is elaborated the elaborated
type is stored in the class_type_t so it is possible to look up the
elaborated class type. But this class_type_t is shared among elaborated
class types. As a result when creating multiple instances of a module with
a class definition an internal assert is triggered.
To support multiple module instances with class definitions instead of
storing the elaborated type in the type definition look up the type in the
scope in which the type definition is references.
This is similar to how the same problem is solved for enum types.
For packages we still need to remember the elaborated type otherwise scoped
class type references wont work. Since there is only one instance of a
package this doesn't have the same problem as classes in modules.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The base class type is not owned by a class and is shared. For this reason
it must not be modified. To ensure this mark the base class pointer as
const.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Array ports are created via a resolve list. We need to detect and
record whether they need to be created in an automatic context at
the point they are declared, not at the time they are created.
Check that the compatibility of signals of enum data type across module
boundaries.
If the enum data type is declared at a higher level scope or imported from
a package the signals are compatible between different module instances. If
the enum data type is declared within the module itself though the signals
are not compatible.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
An enum data type declared in a module is not compatible between different
instances of the module. The type is unique in each hierarchical instance
scope. The type can for example depend on module parameters which would
result in conflicting definitions. This is defined in section 6.22 ("Type
compatibility") of the LRM (1800-2017).
At the moment enum compatibility is checked by comparing the enum_type_t.
But the enum_type_t is shared among the netenum_t that are created for each
module instance and gives the wrong result.
Since there is exactly one netenum_t created for each enum and each
instantiated scope use this to check if the data type of two enum type
signals is compatible.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to declare a registered output of a user defined
primitive using the `output reg` syntax.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The parser currently expects `reg output` for UDP registered output. But
the correct syntax is `output reg`. Fix this to accept the correct syntax.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The `net_type` and `dt` parameter of `pform_set_net_range()` always get
passed the same value, NetNet::NONE and IVL_VT_NO_TYPE respectively. Both
these values are ignore by the function. So these parameters don't do
anything useful, remove them.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a couple of different functions for the different data types that
are called when the type of a signal is set. But they all effectively do
the same.
Consolidate this code by moving the common code into the main
pform_set_data_type() function.
This allows to remove most of the type specific functions and eliminates
some duplicated code. It ensures consistent and data type independent
behavior at the parser level. Something that will be required to eventually
support type parameters.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When creating a PWire for a enum type the signedness as well as whether
the base type is an integer is assigned to the wire.
But this information is never queried again. When creating the netenum_t
this information is directly taken from the enum_type_t.
The signedness and integer information of the PWire is only used when
elaborating a netvector_t.
Removing this makes the pfrom_set_enum() function similar to those for
other types and will allow us to consolidate them in follow up patches.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to define the data type of a non-ANSI task port
in a separate declaration from the port direction. Add tests for both the
type declared before the port direction and for the type declared after the
port direction.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to define the data type of a non-ANSI module port
in a separate declaration from the port direction. Add tests for both the
type declared before the port direction and for the type declared after the
port direction.
Note that this doesn't work yet correctly for integer type module ports
yet, so there are no tests for this. This will be addressed in follow up
work.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When using non-ANSI ports (System)Verilog allows to have separate
declarations for the port direction and data type. E.g.
```
input x;
reg x;
```
It is also allowed to first declare the data type and then the port type.
E.g.
```
reg x;
input x;
```
Currently this fails with an error message. Add support for handling this
by allowing to change the port type of a signal from `NOT_A_PORT` to port
direction.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For some data types the value returned by the `elaborate_type()` method is
shared among different signals of that type. E.g. all string or real types
get elaborated to the same ivl_type_s. This means the returned value must
not be modified, otherwise the data type for unrelated signals might get
changed.
To enforce this and protect against accidental breakage make the return
type of the `elaborate_type()` and the related `elaborate_type_raw()`
methods const.
Note that `ivl_type_t` is used for the new return type which is a typedef
for `const ivl_type_s*`.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that a range mismatch is detected for non-ANSI task ports when
port direction and data type are declared separately.
An error should be reported and no crash should occur.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that a range mismatch is detected for non-ANSI module ports when port
direction and data type are declared separately.
An error should be reported and no crash should occur.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When using non-ANSI style port declarations it is possible to have both a
port and net or variable declaration for the same signal. In this case the
range specification for the two declarations have to match.
In the current implementation if the range specifications do not match an
error is reported and no signal is created. This generates follow up errors
about the signal not being declared when it is used.
In some cases it even causes the application to crash. E.g. the task
elaboration expects the port signal to exist. If it does not it will crash.
To avoid this still create the signal, even when an error is detected. Use
the range specification of the net or variable in this case. Overall
elaboration will still fail due to the error, but the application will not
crash.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently there is a mix of passing line information either as `struct
vlltype` or as a separate `const char *file` and `unsigned lineno`.
For consistency always use the struct vlltype variant.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There is a function prototype for `pform_make_reals()`, but the function
is never declared nor used. Remove it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that queues of packed arrays are supported. These tests are identical
to the existing queue tests for other data type, just that the data type
is a packed array.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to declare a dynamic array of a packed array
type. The test is identical to the tests for the other supported dynamic
array types.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently only dynamic arrays and queues of atom2 and vector types are
supported. Add support for packed arrays. Since these three types are
essentially handled the same internally supporting this only requires to
allow to elaborate a packed array base type.
Factor out type elaboration into a helper function that can be shared
between the elaboration of the base type of a dynamic array or queue and
the type for other signals. This gives consistent behavior and will also
make it easier to support additional base types for dynamic arrays or
queues.
Note that it is not yet possible to index elements of packed array dynamic
arrays or queues. But neither is it possible to do a bit select for vector
or atom2 type dynamic arrays or queues yet. Supporting this needs some
additional work.
There is one test that declares a queue of a struct type, but doesn't use
it since it is not supported. With this change a error will generated when
trying to declare a queue of a struct. So update that test to not declare
the variable so it does not fail.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Each data_type_t has a elaborate_type() method that returns the
corresponding ivl_data_t for that type.
Make use of that in PWire::elaborate_sig(). This removes duplicated code
and ensures consistent behavior between the different places where types
are elaborated.
This will also make it easier to add new data type that are going to be
elaborated this way.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In the vvp all vector signals are in canonical form. This means a single
dimension and the lsb starts at 0.
This means that there is no need to restrict new operations for dynamic
arrays of vectors to vectors with 0 or 1 packed dimensions. Multiple packed
dimensions will work just fine. All that is needed is the total packed
width for the signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The SystemVerilog grammar explicitly allows an empty class item
declaration. The empty class item declaration is just a semicolon and has
no effect.
E.g. the following is legal
```
class C
int x;;;
endclass
```
Add support to the parser to accept empty class item declarations.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
String literals may have escaped special characters in them. Make sure
we are processing all the special characters that the standard supports,
and also fix the handling of the assignment to strings. Note that the
vvp input has string literals sanitized so that the parser can handle
the various binary values. desanitize the strings when pushing string
literals into the string stack. This fixes string assignments, and other
string operations.
The logic that decides whether a vector is scalar or not incorrectly flags
all variables that are declared in packages as scalar. As a result it is
not possible to do a part select on a vector declared in a package.
Rather than having an independent scalar flag consider a vector as scalar
if it does not have any packed dimensions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
While a package can not have logic defined in it. It can have
variables with initializers. These initializers currently get
ignored when converting the package to a module in the
vlog95 backend.
Make sure packages are treated the same as modules here and
that the initializers are turned into initial blocks in the
generate vlog95 code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Using Verilog data types on module input and inout ports is an error in
Verilog. But in SystemVerilog it is allowed and the port should be a net
with the specified data type.
Check that this is supported.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add regression tests that check that declaring a net of type class, dynamic
array, queue or string result in an error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In Verilog module input ports can only have a packed dimensions and a
signed flag, but no explicit data type.
In SystemVerilog an explicit data type can be specified for module input
ports. Such a port is a net, regardless of the data type, unless
explicitly made a variable using the `var` keyword.
This works for the most part in the current implementation, but for some
data types such as `reg` and `integer` the input port is turned into a
variable. And since input port's can't be variables in the current
implementation this results in an error.
Fix this by completely removing the `reg_flag` that is used to indicate
that a certain data type is always a variable. There is no such restriction
on data types for SystemVerilog and for Verilog there are already checks in
place that a input port can only have an implicit (or real) data type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
While a variable can have any data type the data type for nets is quite
restricted.
The SystemVerilog LRM section 6.7.1 ("Net declarations with built-in net
types") requires that the data type of a wire is either a 4-state packed or
a unpacked struct or unpacked array of 4-state packed types.
As an extension to this iverilog allows real data type for wires as well as
2-state packed types.
Add a check that reports an error if a net with any other type is declared.
In addition in Verilog a net can not have an explicit data type at all. It
can only have a packed dimension and a signed flag. As an extension to this
Icarus also allows wires to be of `real` data type.
Note that in Verilog mode the data type is checked in the parser since only
the parser knows whether the data type is an implicit type (`input reg
[7:0]` and `input [7:0] x` elaborate the same). But for SystemVerilog the
type is checked during elaboration since due to forward typedefs and type
parameters the type is not necessarily known in the parser.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Consistently use ivl_assert() instead of assert() in the eval_tree()
implementations. ivl_assert() includes information about which expression
triggered the assert and it makes debugging easier.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There is now an implicit $unit package that needs to be ignored by
the blif target. Take this opportunity to make the root module checking
for the blif target a bit more robust.
Void functions can be used in always_comb, but since the compiler
uses the check_synth() method to generate some warnings, make sure
that function is implemented for functions as well as tasks.
Check that a output port that has a explicit data type, but no explicit
net type is elaborated as a variable type port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In SystemVerilog output ports are a variable if either:
* They are explicitly declared a variable (with the `var` keyword)
* There is no explicit net type, but a explicit data type
This is in detail described in section 23.2.2.3 ("Rules for determining port
kind, data type, and direction") of the LRM (1800-2017).
E.g.
```
output x // Net
output [1:0] x // Net
output signed x // Net
output wire x // Net
output wire logic x // Net
output var x // Variable
output logic x // Variable
output var logic x // Variable
output int x // Variable
output real x // Variable
output string x // Variable
output some_typedef x // Variable
```
At the moment the code checks for certain data types and only makes the
output port a variable for those. And it is even different data types
depending on whether the port is declared ANSI or non-ANSI style.
Change this so that if a data type is specified and it is not a implicit
data type (i.e. only ranges or `signed`) then the output is of type
variable.
This ensures consistent and correct behavior.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently module ports only support vectors, atom2, enum and struct packed
types, but not packed arrays.
Generalize the code so that any packed type is supported.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Task and function item rules are identical. Consolidate them into a single
set of rules to remove some duplicated code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
NetNet::get_isint() is never used anywhere, remove it. The information
whether a signal is an integer is always directly queried from the signal
data type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For signals that are declared in a block string_type_t is already used to
pass the type information to the signal elaboration.
But for task ports it is passed as IVL_VT_STRING. Switch this over to also
passing the type information as a data_type_t.
This allows to remove the special handling for IVL_VT_STRING in the signal
elaboration.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to declare task ports with SystemVerilog types.
Both ANSI style and one for non-ANSI style.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows unpacked array dimensions on non-ANSI style task and
function ports.
To support this refactor pform_make_task_ports() to accept a of
pform_port_t, which in addition to the identifier name also allows to
specify per port unpacked dimensions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Tasks and functions support two types of port declarations. Either ANSI
style, in parenthesis after the task name, or non-ANSI style, as
declaration statements in the task body.
In the current implementation SystemVerilog types are only accept for ANSI
style port declarations, while non-ANSI style only accept Verilog types
(reg, integer, time, real).
Add support for SystemVerilog data types for non-ansi style ports.
This also makes the parsing rules simpler since we can use `data_type` to
match all data types and don't need a explicit rule for each supported data
type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows `parameter` and `localparam` to declare constants
within a class scope. E.g.
```SystemVerilog
class C;
localparam A = 10;
endclass
```
In this context both declare a local parameter that can not be overwritten.
Supporting this can be achieved for the most part by adding a parser
sub-rule in class declaration rule. In addition some extra support code is
needed to mark the parameter as non-overridable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
It is allowed to access a constant declared in a class scope, such as a
enum value or parameter, on an object of that class type. This is described
in section 8.5 ("Object properties and object parameter data") of the LRM
(1800-2017).
E.g.
```
class C
enum { A } e;
endclass
C c = new;
c.e = c.A;
```
Support this by in addition of searching for class properties on the object
also search for constants in the class scope.
A bit of refactoring is needed around the parameter elaboration functions
since they expect a non-const NetScope, but for classes we only have a
const scope available.
The non-const scope is needed to be able to mark specparams as
non-annotatable. Since classes can't have specparams this part is factored
out into a separate function the NetScope parameter for the shared
functions is made const.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Parameter expressions need to remember the scope they have been declared in
so that the code generator backends can insert the right parameter
reference, rather than a constant value.
Currently the scope is stored as a non-const reference. But that is not
needed. Mark the scope reference as const so NetEConstParam and
NetECRealParam can be created when only a const scope reference is
available.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The NetScope class has a method called find_parameter() that looks up the
parameter and returns a iterator to it. This is only ever used to get the
line information of the parameter.
Refactor the function so that it only returns the line info. This will
allow to call this function on a const NetScope object.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The has_parameter_port_list member of the LexicalScope class is not
initialized, which means its default value is undefined. This leads to
random failures where a parameter is marked as non-overridable when it
shouldn't.
Make sure has_parameter_port_list is properly initialized to false.
Fixes: 673b40b78c ("Elaborate `parameter` as non-overridable where required")
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that it is possible to use a class new as
an initializer for a variable or property declaration.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are currently two rules for parsing variable declarations.
One that is used when declaring variables in as a block declaration item
and another that is use everywhere else.
Consolidate those into a single set of rules. This removes a fair bit of
duplicated code in the parser.
A side effect of this refactoring is that class new statements can be used
as variable initializers as allowed by the standard. E.g.
```
module test;
class C;
endlcass
C c = new C;
endmodule
```
This previously was not supported for block item variable declarations.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Variables don't have a delay or strength and the NetNet::Type is known. Add
a small wrapper around pform_makewire() that can be used to create
variables. This will allow to reduce the boilerplate code for variable
declarations.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a few places where pform_makewire() is used and attributes can be
attached to the created net or variable. At the moment pform_makewire()
doesn't allow to specify the attributes, and they either get dropped
silently or with a warning.
Add support for passing the attributes to pform_makewire() which will then
pass it on to pform_set_data_type() to attach it to the declared net or
variable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are currently two very similar implementations of pform_makewire().
One that takes a `net_decl_assign_t`, the other a `std::list<decl_assignment_t*>`.
The one that takes a `std::list<decl_assignment_t*>` is a superset of the
other. It can handle both wires and variables, while the other can only
handle wires.
Update the parser to generate a `std::list<decl_assignment_t*>` for wire
declarations. This allows to remove one of the two functions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that the following declarations inside a generate block generate an
error:
* module, program or interface
* specparam
* specify block
* timeunit
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Most things that can be declared in a module can also be declared in a
generate block.
But there are a few exceptions that can not be declared in generate block
* module, program or interface declaration
* specify block or specparam
* timeunit
Some of these currently work while some of them trigger an assertion and
cause and application crash.
Add checks to make sure that all of them these are reported as an error and
do not cause a crash.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Split the test into multiple tests that each check one type of invalid
override rather than having one big tests that checks for everything.
This allow to check whether the test passes or fails by seeing if it
compiles or not. The one big test on the other hand relies on seeing the
exact error messages as recorded in the gold file.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For modules, programs and interfaces that have a parameter port list, a
parameter declared inside the scope's body is supposed to be elaborated as
a local parameter.
TThis is described in the Verilog LRM (1364-2005) section 4.10.1 ("Module
parameters") and the SystemVerilog LRM (1800-2017) section 6.20.1
("Parameter declaration syntax").
Implement this by marking a parameter declared in such a way as
non-overridable.
Note that a parameter declared within a named block, function or task can
still be overridden, even if the module has a parameter port list.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The "->" operator is rarely used, but exists. Unfortunately, the syntax
is tied up in a horrible mess with the System Verilog constraint list
syntax. Do some flex magic to make it all work.
SystemVerilog supports parameters without default values in parameter port
list. Add regression tests to check this feature.
Also add a regression test to check that modules without a default
parameter are not automatically picked as a toplevel module.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows to omit the default value of a parameter declared in a
parameter port list. In this case the parameter must be overridden for
every module instance. This is defined in section 6.20.1 ("Parameter
declaration syntax") of the LRM (1800-2017).
In addition a module that has a parameter without a default value does not
qualify for automatic toplevel module selection.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For unpacked statically sized array types $bits() is supposed to return the
total size of the array. Accumulated the number of unpacked dimensions and
multiply it by the packed with of the base type to get the right result.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are a few system functions that take either an expression or a data
type. This is implemented in the parser by allowing a type identifier as a
primary expression.
But those functions allow any data type, not just typedefs. E.g.
```
$bits(int);
$bits(reg [1:0]);
$bits(struct packed { int x; });
```
Support this by changing the parser rule from TYPE_IDENTIFIER to data_type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are currently two different systems to evaluate constant expressions
in iverilog.
The PExpr based system using the eval_const() method and the NetExpr based
system using the eval_tree() method. The latter is more complete while the
former only implements the bare minimum and also has some minor bugs.
The PExpr based system is only used to evaluate expressions within
attributes.
Switch attribute expression evaluation over to elab_and_eval(). This
enables to use the full set of constant expressions for attributes, maybe
most importantly constant functions and system math functions.
It also allows to remove the PExpr based system since there are no more
users.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows to completely omit the `parameter` or `localparam`
keyword in the parameter list. Both at the beginning and before redefining
the parameter data type. This is not support in Verilog.
Add regression tests that check that this is supported when in
SystemVerilog mode.
It is not valid to use an implicit data type e.g. just `signed` when
`parameter` was omitted, add regression tests to check for this as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows to completely omit the `parameter` keyword in a
module parameter port list. This is described in section 6.20.1 ("Parameter
declaration syntax") of the LRM (1800-2017).
E.g.
```
module a #(X = 10) ...
module b #(int Y = 20) ...
```
It also allows to redefine the parameter type without having to have a
parameter or localparam before the type.
E.g.
```
module a #(parameter int A = 1, real B = 2.0) ...
module b #(int X = 3, real Y = 4.0) ...
```
Extend the parser to support this.
Note that it is not possible to declare a parameter with an implicit data
type this way.
E.g. the following is not legal SystemVerilog
```
module a #([3:0] A = 1) ...
module b #(int X = 2, signed Y = 3.0) ...
```
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When encountering a construct that requires SystemVerilog in most cases an
error message is generated when SystemVerilog is not enabled and parsing
simply continues.
Factor the checking and generating of the error message into a helper
function. This slightly reduces boiler plate code and gives consistent
error messages.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In Verilog a parameter in a generate block is invalid and should
result in a compile error.
In SystemVerilog on the other hand it is valid, but it is equivalent
to a localparam and can't be overridden.
Add regression tests that check for this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows to use the `parameter` keyword in a generate
block. If used in a generate block it behaves like a `localparam` and
cannot be overridden.
This is described in section 27.2 ("Generate constructs - Overview") of the
LRM (1800-2017).
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Parameters declared in certain scopes behave like local parameters and can
not be overridden. Rather than making those parameters a localparam track
whether a parameter can be overridden.
This allows to generate better error messages when trying to override the
parameter.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
During parsing parameters and localparams are kept in a separate list only
to be collected into the same list during elaboration.
Store them in the same list during parsing as well, this allows to remove
some duplicated code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
A base class can be referenced by scope. E.g. if the base class is in a
package.
```
package P;
class B;
endclass
endpackage
module test;
class C extends P::B;
endlcass
endmodule
```
To support this let the parser accept a scope identifier for the base
class.
A small change is also necessary to how the base class lockup is done
during elaboration. At the moment the code will search for the base class
by name in the current scope. This doesn't work with scoped identifiers.
But we already have a reference to the base class data type, so we don't
have to search for it by name.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are multiple places in the grammar where either a type identifier or
scoped type identifier is accepted.
Factor this into a common parser rule. This removes some duplicated code.
But it will also be required to avoid reduce-reduce conflicts for future
grammar extensions, e.g. to support type parameters.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently when encountering an end label on a unnamed block
a 'syntax error' will be generated and the parser will give up.
Slightly refactor the parser so that this case is detected, a more specific
error message is generated and the parser can recover and continue.
This also slightly reduces the parser since it allows to merge the almost
identical rules for handling named and unnamed blocks.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Most named constructs support a end label in SystemVerilog. The handling of
this end label is always the same.
* Generate an error if the end label does not match the name of the block
* Generate an error if not in SystemVerilog mode
* Delete the end label
Factor this into a common helper function. This reduces code size a bit and
results in consistent error messages.
The latter requires refreshing of some gold files to match the slightly
different error messages.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog supports variable declarations in unnamed forks, while
Verilog does not.
Add a regression test that checks for this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
While it is not a particular useful construct it is legal to have a
parallel block with just variable declarations and no statements. E.g.
```
fork
int x;
join
```
At the moment there is a special rule for completely empty parallel
blocks. Remove that rule and change the statement_or_null_list in the
fork/join parser section to a statement_or_null_list_opt. This way it
covers both completely empty parallel blocks as well as parallel blocks
with only variable declarations.
Note that this already works as expected for named parallel blocks.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that invalid parameter overrides generate an error.
There are some cases that are not handled correctly today. The test will be
updated once they are addressed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Overriding a parameter that does not exist will only generate a warning at
the moment. This can hide programming mistakes such as an typo in a
parameter override.
There is nothing in the LRMs to support that this should only be warning,
so elevate this to an error. This is consistent with how an error is
generated when trying to reference a non-existing port or variable.
The generated error message differentiates between whether the parameter
does not exist at all, or whether it is a localparam.
There are two regression tests that rely on that only a warning is
generated, these have been updated to expect an error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that all parameters in a parameter port list after a `localparam` get
elaborated as localparams, until the next `parameter`.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When declaring module parameters in the ANSI style parameter list it is
possible to omit the `parameter` or `localparam` keyword. In this case
whether the parameter is local or non-local is inherited from the previous
parameter.
In the current implementation when the type of the parameter is not
specified it will always use parameter. E.g. the following will create a
localparam A and a parameter B, while it should be localparam A and B.
```
module #(localparam A = 1, B = 2);
```
Fix this by remembering whether the previous entry was a parameter or
localparam. This is similar to how the parameter data type is already
remembered.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Verilog-AMS defines parameter value ranges which can restrict the value
that can be assigned to a parameter. It defines this for both `parameter`
and `localparam`. Currently it is only implemented for `parameter`. Support
it for `localparam` as well for consistency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The code for handling parameter and localparameter declarations is very
similar. Consolidate this into a single helper function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
struct members are currently always treated as unsigned. This leads to
incorrect behavior in contexts where the sign makes a difference. E.g.
```
struct packed {
int x;
} s;
s.x = -1;
if (s.x > 0) $display("FAILED");
```
Query the signedness of the struct member form the type of the member.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check that when an error message for a enum or struct data type is
generated it points to the location of the declaration of the type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
enum_type_t inherits from LineInfo, but also has a LineInfo field called
`li`.
When a enum_type_t is created the LineInfo of the object itself is set to
the location where the type is declared.
The `li` field gets set when a signal of the enum_type_t is created to the
location where the signal is created. The `li` field is then used when
elaborating a netenum_t to set the line information on the netenum_t.
This works fine when the enum is directly used to declare a signal, since
the location of the type and signal declaration are the same and there is
only one signal of that type.
But when using a typedef and declaring multiple signals with the same type
the `li` field will be repeatedly set and eventually point to the last
signal declaration of that type.
On the other hand when using or declaring an enum as part of an aggregate
type such as an array, struct or class the line info will never be
set.
This can cause misleading error messages. E.g.
```
typedef enum {
A, B = A
} e_t;
struct packed {
e_t e;
} s;
```
will generate
```
:0: error: Enumeration name B and A have the same value: 32'sd0
```
To fix this use the LineInfo that was assigned to the enum_type_t itself
when it was declared and remove the `li` field.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
netstruct_t inherits from LineInfo. But the file and line information is
never set leading to messages like
:0: error: Member r of packed struct/union must be packed.
When elaborating a netstruct_t set the line info from the struct_type_t it
is elaborated from. This makes sure that error messages for the struct type
have the proper file and line information when printed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Test that enums are elaborated in declaration order and a enum declaration
can reference a item of an enum that was declared before it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog supports variable declarations in unnamed blocks, while
Verilog does not.
Add a regression test that checks for this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
While it is not a particular useful construct it is legal to have a
begin/end block with just variable declarations and no statements. E.g.
```
begin
int x;
end
```
At the moment there is a special rule for completely empty begin/end
blocks. Remove that rule and change the statement_or_null_list in the
begin/end block parser section to a statement_or_null_list_opt. This way it
covers both completely empty blocks as well as blocks with only variable
declarations.
Note that this already works as expected for named begin/end blocks.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
enums for a scope are stored in a std::set. This means when iterating over
the enums during elaboration it is possible that they are elaborated in a
different order than they have been declared in. This causes problems if
one enum references items of the other enum. E.g.
```
enum {
A
} a;
enum {
B = A
} b;
```
In the current implementation whether this works or not depends on the
pointer values of the enum_type_t for `a` and `b`, which can change between
environments.
To make sure that enums are elaborated in the same order use a std::vector
instead of a std::set.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
These test verify that explicit cast to packed array and packed struct
types are supported and executed correctly.
The tests are based on the test for integer casts. Just the type of the
variables was changed to packed array and packed struct respectively.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Update the enum cast test to reflect that enum casts are now supported.
Also add a small check to verify that the right value got assigned to the
enum after the cast.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Assigning a value to an enum signal that is not of the same type as the
enum requires an explicit cast.
To support this attach the type of a type cast to the resulting expression.
This allows the assignment elaboration to confirm that value has been
explicitly cast to the right type.
Also handle the case where the value is a constant. In this case create a
NetEConstEnum instead of a NetEConst as the resulting expression.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The scope_ field of the NetEConstEnum class is initialized in the
constructor, but never used anywhere again. Remove it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently explicit cast is supported to atom2 and vector types. packed
struct, packed array and enum are not supported.
An explicit cast to packed type works the same for all packed types though.
Add support for handling also packed structs, packed arrays and enums by
make the code more generic and querying the packed base type from the
ivl_type_t.
To correctly handle enums a bit more work is necessary, which will be done
in a follow up patch.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Mark them as NI so that in the fugure they might be turned back
on if they can be made to work. Keep the tests around as reference.
Also, remove reports that are no longer tested in CI. This is because
they are no longer tested by a previous patch that relies on the
change vvp_reg.pl behavior around failed tests.
Remove now obsolete update_msys2_report.pl, and simplify the test.sh
script, since diff commands and Windows specific trickery are no
longer needed.
If there are any failures, return a non-zero exit status so that
invoking scripts can detect that failures happen. This eliminates
the need to use regression report reference outputs, and should
make it easier to merge PRs that add or impact tests.
Add a test that checks that signing annotations on structs are supported
and that signed structs are properly evaluated as a signed value.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
packed structs and packed unions as a whole can either be signed or
unsigned. This information is used when it is used as a primary in an
expression, i.e. without accessing any of the members.
Add support for parsing and elaborating signed structs.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Extend the array_packed test to check declaring a packed array of a type
from another scope that is addressed via a scoped identifier.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
It is possible to directly declare a packed array of a struct or enum
without having to create a typedef first.
Add a check to the array_packed test that this is supported and works as
expected.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Allow scoped identifiers to be used as the base type for packed array
types. Scoped type identifiers can be used the same way as unscoped type
identifiers.
E.g.
```
package p;
typedef logic [1:0] vector;
endpackage
module test;
p::vector [1:0] pa;
endmodule
```
is a valid construct.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
It is possible to directly declare a packed array of a struct or enum,
without having to typedef the struct or enum first. E.g.
```
struct packed {
int x;
} [1:0] pa;
```
Add support to the parser for handling this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
These tests check that a enum that is declared in a struct or class are
correctly elaborated and also name collisions with the enum names are
detected.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When creating an enum type it must be added to the scope where it is
declared so it can later be elaborated and the enum and its names can be
referenced in expressions.
In addition the names of the enum must be added to the lexor scope so that
name collisions are detected and can be reported as errors.
This is done with pform_put_enum_type_in_scope() function.
At the moment the function is called from two different places
* When adding a typedef of a enum type
* When creating a signal of a enum type
In addition the enum_type_t is added to a class scope `enum_sets` when
declaring a enum property in a class. But this only makes sure that the
enum gets elaborated, its names are not added to the lexor scope.
This works fine for the most part, but breaks for a few corner cases.
E.g. it is possible to declare a enum type as part of the subtype of
another packed type such as structs or packed arrays. E.g.
```
struct packed {
enum {
A
} e;
} s;
```
This is not covered by either of the cases above and neither do the names
of the enum get added to the lexor scope, nor is the enum type elaborated.
Another corner case that is currently not working is declaring a class
property where the type is a typedef of a enum that is declared outside of
the class. In this case the enum is elaborated again inside the class
scope. E.g. the below is supposed to work, but fails with an already
declared symbol error.
```
typedef enum {
A
} e_t;
class C;
typedef enum {
A
} e1;
e_t e2;
endclass
```
In addition since for enums declared in classes they are only added to
`enum_sets`, but names are not added to the lexor scope, it is possible to
declare a different symbol in the class scope with the same name.
E.g. the following elaborates fine
```
class C;
enum {
A
} e;
typedef int A;
endclass
```
To fix this call pform_put_enum_type_in_scope() when the enum_type_t is
created in the parser. This makes sure that it is handled the same
regardless where the type is declared or used.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Refactor the enum rule by adding a enum_base_type rule which handles the
type specific initialization. This allows to keep the non-type specific
parts in a common rule, which makes it easier to modify in future changes.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The test checks that all invalid declarations produce an error and also do
not crash the application.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When something goes wrong when parsing a struct member, e.g. the type does
not exist, a nullptr is added to the struct member list. This will cause a
crash when iterating over the list.
E.g.
```
struct packed {
logc x;
} s;
```
Add a check so that nullptr members are not added to the list.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
By adding ivtest to the iverilog source tree, it is easier to keep
the regression test synchronized with the source that is being tested.
This should be especially helpful for PRs that add a new feature, and
have a matching ivtest PR with the regression test for that feature.
Currently it is only possible to declare packed array variables with a
struct type as the element type.
Add support for packed arrays of other packed types. This includes packed
arrays of enums and vectors as well as packed arrays of packed arrays.
Since packed arrays of packed types are already supported for class members
the infrastructure for elaborating all types of packed arrays exists.
It just needs to be called when elaborating a signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When creating a signal of a packed array it is checked that the base-type
of the packed array is a packed type.
But this check is only done if the packed array itself is the type of the
signal. Placing the packed array in a struct or class will elaborate fine,
but then crash during simulation.
E.g.
```
typedef real myreal;
struct packed {
myreal [1:0] p;
} s;
```
Move the check from signal creation to type elaboration, so that it is not
possible to create a packed type with a non-packed base-type.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use netrange_t, which is meant for storing ranges, for storing the range of
a netenum_t.
This makes the integration with the rest of the codebase a bit more
seamlessly and also allow to reuse methods defined for netrange_t such as
the width() method rather than having to reimplement it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Specifying and enum with an invalid dimension range results in an assert or
segfault. E.g. `enum [$] E { ... }`.
Use the `evaluate_ranges()` function to elaborate the enum dimensions. This
functions has proper error checking and recovery built-in.
In addition verify that there is at most one packed dimension.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Having an enum with a lsb > msb base type, e.g. `enum logic [0:9]` is a
legal construct.
It is handled correctly for the most part already, there is just an assert
that triggers on it. Remove that assert.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
To determine the base type structs and packed arrays call the
figure_packed_base_type() for their sub-types.
This method is not defined for enum or atom2 types and the default
implementation returns IVL_VT_NO_TYPE.
As a result packed arrays of enum or atom2 types and packed structs with
members of enum or atom2 types get elaborated with IVL_VT_NO_TYPE
as the base type.
For example
```
struct packed {
bit signed [31:0] x;
} s1;
```
gets elaborated with a base type of IVL_VT_BOOL, while
```
struct packed {
int x;
} s2;
```
gets elaborated with a base type of IVL_VT_NONE.
To fix this define the figure_packed_base_type() for enum_type_t and
atom2_type_t.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Trying to elaborate a type with invalid packed dimensions currently results
in a crash. E.g. `typedef logic [] T;`
The issue is in the `elaborate_array_ranges()` function which
does not verify that the range specification is valid.
Replace the `elaborate_array_ranges()` with `evaluate_ranges()`, which does
the same thing, but properly checks the range specification and
reports an error if it is invalid.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
If the left-hand side of a logical operator is a constant that causes the
right-hand side to be short-circuited the right-hand side can be discarded
even if it is not constant.
In this case replace the expression by a constant.
E.g.
* `0 && expr` will be replaced by a constant 0.
* `1 || expr` will be replaced by a constant 1.
* `0 -> expr` will be replaced by a constant 1.
Note that it is not possible to replace the expression by a constant if
only the right-hand side is a constant, even when the value of the
expression is constant. The left side still has to be evaluated for side
effects.
E.g. it is known at elaboration that `a++ && 0` will yield 0, but the
increment on `a` has to be executed regardless.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Section 11.4.7 of the SystemVerilog LRM states
```
The && and || operators shall use short circuit evaluation as follows:
- The first operand expression shall always be evaluated.
- For &&, if the first operand value is logically false then the second operand shall not be evaluated.
- For ||, if the first operand value is logically true then the second operand shall not be evaluated.
```
vvp currently evaluates both operands of a logical operator. This works
fine as long as the right-hand side does not have a side effect. But if it
has the result might be incorrect.
E.g. for `a && b++` `b` must not be incremented if `a` evaluates to false.
The Verilog LRM mentions that it is allowed to short circuit any expression
"if the final result of an expression can be determined early". But there
is no requirement to do so.
So the new and the old behavior are both correct implementations in
Verilog.
Use the new behavior in both Verilog and SystemVerilog mode to make sure
the behavior is consistent when an expression has side effects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The code for generating the logical `and` and `or` operators is identical
except for the final opcode to combine the two results.
Consolidate this into a single function to reduce the code a bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
If this assert fires, the "this" pointer we pass to it will be a
null pointer, so will cause a null pointer dereference. We've
tested it is not null earlier, so we don't need the assertion.
When using the latest mingw64 header files, rpcndr.h (which is indiretly
included by windows.h) defines a type named "byte" which collides with a
definition in cpp_type_traits.h (included indirectly by the STL). This is
only a problem if "using namespace std" is declared prior to including
windows.h.
For non-ANSI port declarations that have both a port declaration and
a corresponding variable declaration, the signed attribute may be
attached to either the port declaration or the variable declaration,
or both declarations.
This also ensures the same genvar cannot be used in two nested loops
(issue #533), because the implicit localparam with the same name
shadows the genvar declaration.
This requires us to make a copy of the typedefs map when adding it to
a NetScope object, because the pform data is deleted before we are
finished with it.
The IEEE standard specifies that the numbering of generate blocks
restarts at 1 in each new scope, and that the 'else' part of an 'if'
construct is part of the same constuct, so has the same number.
This eliminates some indeterminism in the error messages, which was
causing occasional failures in CI. We don't expect this list to be
very large, so the O(n) insertion time should not be a problem.
A module port list may contain unnamed entries, e.g.
module dut(a,);
When performing a wildcard connection, these entries should be skipped,
as there is no name to match.
The old implementation connected all inputs to the same vvp_net_t port,
on the basis that we don't care about the data values or what port they
arrived on. But if one or more of the inputs fans out to multiple nets,
the chains get tangled, which either results in connections being lost
or inappropriate connections being made, depending on the order that
the inputs are linked.
This could have been fixed by using a standard wide functor. But as we
don't care about the data values, that would be unnecessary overhead.
We just need separate vvp_net_t objects to handle the input connectivity
and can keep using a single shared functor.
This is needed for the waveform dumpers now that vpi_iterate(vpiModule, NULL)
has been ficed to only return modules.
This includes recognising vpiProgram and vpiInterface, although the compiler
and vvp currently incorrectly classify them as modules.
(replacing assertions)
The IEEE standard either requires out-of-bounds bits to be ignored on
write, returned as 1'bx on read, or requires a compile-time error message.
The latter is easier to implement.
If we have a bit/part select that is selecting one or more sub-arrays, e.g.
wire [3:0][3:0] foo;
assign foo[1] = 4'd1;
we need to take into account the bit width of the sub-array when calculating
the bit width of the select.
The code assumed all handles stored in vpip_root_table were modules. This
is true for traditional Verilog, but not so for SystemVerilog.
Whilst here, also add support for iterating over packages.
To correctly restore the file name and line number after including a
file or expanding a macro, the preprocessor needs to be aware of the
changes introduced by `line directives. The `line directive still
needs to be passed on to the main compiler so it can track the
changes too.
To avoid duplicate error messages, the preprocessor silently ignores
invalid `line directives, relying on the main compiler to report the
errors.
This might come to pass for example when calling the function
$ivl_string_method$len(<expression>) where the expression is
calculated, and not simply a variable name.
There are too many ad hoc handlers of symbol_search partial results.
Rewrite symbol_search to clean up things like partial results and
member/method detections. Use this reworked symbol_search function
to rewrite expression elaborate for the PECallFunction expressions.
When elaborating a subclass, the base class scope needs to be elaborated
before the subclass scope. If the base class and subclass are defined in
different packages, this requires the package scopes to be elaborated in
the correct order. SystemVerilog reqires packages to be defined before
they are used, so that is the order we should elaborate them in.
Parameters can have string type and do the usual string stuff,
and also implement some of the string methods on string parameters
so that they evaluate down to constants.
Use the common data_type_or_implicit rules to support type
definitions for parameters. This eliminates a bunch of special
rules in parse.y, and opens the door for parameters having
more complex types.
In the rare cases where DARRAY signals are in the network, handle
them by creating the proper ivl_nexus_t node. This also implements
the receive of vvp_object_t objects bu vvp_fun_anyedge_sa. This
together makes it possible for IVL_VT_DQUEUE objects to be in
wait lists.
This fixes#412
Depending on the order of elaboration, a function may not have been
elaborated before a call to it is elaborated, so don't assert that it
has been. As an optimisation, try to elaborate it on the fly, so we can
elide the call if the function body is empty.
Use the new cur_instance variable to get the call handle instead of calling
vpi_handle(vpiSysTfCall, 0).
This completes a proper fix for issue #141, to replace the problematic fix
that was reverted in commit 8da8261f.
PLI 1.0 callbacks are directly associated with the instance of the system
task/function that initiated them, allowing them to access the task/function
arguments. However, we implement them using VPI callbacks, which are not so
associated. So we need to pass the VPI handle for the associated task/function
instance to the callback routine via the VPI callback user_data pointer,
because vpi_handle(vpiSysTfCall, 0) will return null when called from the
callback function.
This is the first step to a proper fix for issue #141, to replace the
problematic fix that was reverted in commit 8da8261f.
sync_cb::run_run() attempts to cast the obj field of the callback data to a
__vpiSysTaskCall pointer. But a sync_cb object is only used for simulation
time callbacks, where the obj field is (mostly) not used, so I can't see
that would ever succeed. As the obj field is not required to be set by the
user, the dynamic cast results in undefined behaviour, so mingw32 is not to
blame.
This code was introduced by Johann Klammer in commit c79df7c44, but the user
klammerj and all trace of that pull request have vanished from GitHub, and
there is no associated regression test, so I can't establish the rationale
for it.
When doing continuous assignment of packed structs, support the case
where the value being assigned is a member of a member, etc. Procedural
assignments already support this.
See issue#307
IEEE Std 1800-2017 Section 7.6 Array assignments
Assignment of a dynamic array creates a duplicate of the source,
so that assignments to the copy don't impact the original. Handle
all sorts of dynamic array base types.
This.new is not allowed.
super.new beyond the first statement is not allowed.
And while I'm at it, clean up the use of "@" and "#" in
the code as tokens for this and super.
A NetESelect is used for accessing packed struct members and also for
accessing dynamic array elements. In these cases the expr_type() and
enumeration() methods should reflect the member/element type.
The IEEE standard does not clearly state whether the `` directive is applied
before or after embedded macros are expanded. Other simulators vary in their
behaviour. For maximum compatibility, this fix adopts the behaviour found in
Verilator, where `prefix``suffix expands to <prefix>suffix if prefix is a
defined macro, otherwise it expands to <prefixsuffix> (where <...> is the
expanded macro text). Other simulators show this behaviour in at least some
circumstances.
Unless explicitly declared a wire an enum output port is of variable type
and should be marked as IMPLICT_REG.
Currently this is only done when the base type of the enum is `logic`. But
it should be done for all enums regardless of their base type.
Without this change for example the following snippet
```
typedef enum {
A,
B
} E;
module M (
input E ei,
output E eo
);
always_comb eo = ei;
endmodule
```
fails with the following error message
test_enum.sv:11: error: eo is not a valid l-value in M.
test_enum.sv:8: : eo is declared here as wire.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Since commit 62fce50f8c ("Remove dead code for allocate_vec handling.")
vector.c only contains the license header and some include directives
but no actual code.
Remove the file.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Since commit 15cda5fe, forked threads are never embedded in the parent
thread, so we no longer need the special case code that ensured that
task/function calls were reaped before a join.
This also fixes GitHub issue #368.
Given a macro definition like this:
`define name `macro``text
the preprocessor should expand `macro, not `macrotext, when it expands
`name. This also ensures that
`define name(p,s) p``_``s
`define PREFIX my_prefix
`define SUFFIX my_suffix
`name(`PREFIX, `SUFFIX)
expands to
my_prefix_my_suffix
as the user would expect.
When -pfileline=1 is used the queue procedural warnings have file
and line information added to the messages. Also switch the trace
debugging to be off by default.
Also, Add some preliminary missing darray functionality.
When connecting module inout ports, an island is created. If there
is no other driver on one of the island ports, a tie-off is added.
In the case of a tri0 or tri1 net, this must have the correct (pull)
drive strength.
With a pattern rule, the recipe will only be executed once, even when
the rule has multiple targets. Using this to handle the output from
bison is included as an example in the GNU make manual.
This fixes the makefiles so that bison-generated header files will be
regenerated if they are deleted.
The current bison (3.7) generates a *.cc file that includes the header
it generated. For parse.cc this would be parse.hh. Right now, we rename
this header to have a common name used in other files, but this results
in a compile error for the parse.cc file:
parse.cc:462:10: fatal error: parse.hh: No such file or directory
462 | #include "parse.hh"
| ^~~~~~~~~~
Fix this by telling bison to output the header file to the correct
filename in the first place so that we don't have to rename it.
(using the --defines instead of -d option).
This looks like a bison specific option not available in Posix yacc;
but looks like we're requiring bison anyway.
Signed-off-by: Henner Zeller <h.zeller@acm.org>
* Update README to reflect that bison fails to generate correct code
on newer MacOS as well and bison 3.6+ works fine as well
* macos.txt removed because it contains outdated instructions
For functions without a port list in parantheses, declarations are optional in SystemVerilog.
This is true even in IEEE1800-2005, but not in IEEE1364-2005
__CYGWIN32__ is not defined when building with the 64-bit Cygwin
toolchain. According to the Cygwin FAQ, __CYGWIN__ has been defined
since 1998, so this should still work for users on 32-bit systems.
When module ports are collapsed, we can't tell which of the nexus drivers
are associated with a given module port and should be routed through an
associated modpath delay. Work round this by inserting a transparent
buffer or tran_vp if an output or inout port has a modpath delay. The
target code generator can elide this once it has handled the modpath
delays.
In PR #300, @xdch47 pointed out a stable way to fix parallel
installation problems.
This fix applied the method, thanks!
Signed-off-by: Huang Rui <vowstar@gmail.com>
When installing tgt-stub and tgt-vhdl, due to the wrong target
path, the install scripts can't find the file to be installed.
The missing file is: stub.conf, stub-s.conf, vhdl.conf, vhdl-s.conf
Changed to right path fixed this problem.
Thanks @minux help to fix.
Signed-off-by: Huang Rui <vowstar@gmail.com>
As for parentheses, we need to ignore commas within a pair of braces
when parsing a macro argument, e.g. `MACRO({a,b}) has one argument.
This fix is a little crude in that it doesn't distinguish between
parentheses and braces, e.g. it will accept {a,b). But any errors
like that will be caught by the compiler proper.
See also: https://bugs.gentoo.org/706366
gcc-10 and above flipped a default from -fcommon to -fno-common:
https://gcc.gnu.org/PR85678
Usually all it takes is to add a few 'extern' declarations and
move definitions from header files to modules. I've port iverilog
to gcc-10 accroding to this guide:
https://wiki.gentoo.org/wiki/Gcc_10_porting_notes/fno_common
To fix this, I analyzed the code, and found ``pli_trace`` has been
defined at here:
https://github.com/steveicarus/iverilog/blob/v10_3/libveriuser/priv.c#L24
So I changed ``FILE* pli_trace;`` to ``extern FILE* pli_trace;``.
The var ``current_file`` only in ``cfparse_misc.h``, I changed it
from ``char *current_file;`` to ``extern char *current_file;`` and
declaring it in cflexor.lex
And then it works.
Signed-off-by: Huang Rui <vowstar@gmail.com>
The compiler elaborates types on the fly as they are used. For user-
defined types (typedefs) we must do the elaboration in the scope where
the type was declared, not in the scope where it is used.
If the condition expression is 2-state, the result won't be blended, so
the result will be a valid enum value if both true and false expressions
return the same enum type.
When strings are arguments to functions/tasks, that doesn't suddenly
make them implicitly scalar. Strings are vectors and should be treated
that was, even if they are IMPLICIT_REG.
The fix for the compiler hang when calculating the sensitivity list
for an always_comb construct containing recursive function calls
could cause the compiler to ignore sequential calls to the same
function, and thus not add the arguments of those calls to the
sensitivity list.
The old scheme of linking the VPI modules with the vvp exports meant they
did not work when loaded by the compiler. Instead, let each client create
a jump table for the VPI routines and pass that to each VPI module as it
is loaded.
We don't support evaluating user-defined system functions at compile
time. If possible, defer evaluation until run time. If used in a
constant expression, output a "sorry" message.
Casting from signed to unsigned types and vice versa is legal in SV,
as is casting from a larger to a smaller size. Obey Verilog rules
for expression bit width and signedness.
The unique, unique0, and priority keywords can decorate case statements
to tell the run time (or synthesis) to do extra tests (or make extra
assumptions). These tests are not implemented in the vvp run time, but
now the decorations make it to the code generators.
bison 3.4.2 complains when encountering '%pure-parser':
"warning: deprecated directive, use ‘%define api.pure’"
A quick google suggests this option has been around since at least
2012, maybe longer, so probably safe to replace.
Signed-off-by: Nicholas Sielicki <sielicki@yandex.com>
Explicit imports should always conflict with local declarations using
the same name. Wildcard imports only conflict if they are referenced
before a local declaration with the same name.
This also unifies the detection of identifier conflicts.
The '-i' option is there to allow the compiler to be used to check an
incomplete design for errors. With no top-level modules, nothing will
be elaborated, but at least will be checked for syntax errors.
As reported on iverilog-devel on 2018-10-12, a dimension size of zero
could case the compiler to go into an infinite loop. Further tests
showed that unsized or queue dimensions entered as packed dimensions
would cause the compiler to crash.
As discussed on iverilog-devel (2018-03-09), the existing implementation
(using Icarus-specific vpi functions) only worked with assignments to
simple variables, and could not be easily modified to work more generally.
So use the new vvp instructions added in the previous two commits.
This allows any always processes that are sensitive to the UDP output
to start first. This fixes a time 0 race that was found in a Lattice
Semiconductor simulation library (reported on iverilog-devel).
If the initial value is 'x', propagate the value to the UDP output
before the start of simulation, to avoid unwanted update events on
the z -> x transition on downstream nets.
In 64-bit Windows, an unsigned long is 32 bits, so initialising the num
member of the union did not properly initialise the ptr member. The num
member isn't actually needed, so eliminate it.
cfparse.h defines the YYLTYPE struct in case it has not been defined, and
also declares an extern YYLTYPE cflloc which is used in cflexor.
As cfparse_misc.h defines an extended YYLTYPE, the cflloc instance in
cfparse.c has this extended type, i.e. there is a type mismatch.
Changing the include order in cflexor causes both cflexor.c and
cfparse.c to use the definition from cfparse_misc.h.
This has been uncovered by GCC when using LTO:
---
gcc -flto=8 main.o substit.o cflexor.o cfparse.o -o iverilog
cfparse.h:105:16: warning: type of 'cflloc' does not match original declaration [-Wlto-type-mismatch]
105 | extern YYLTYPE cflloc;
| ^
cfparse.c:1162:9: note: type 'struct cfltype' should match type 'struct YYLTYPE'
1162 | YYLTYPE yylloc
| ^
cfparse.c:1162:9: note: 'cflloc' was previously declared here
cfparse.c:1162:9: note: code may be misoptimized unless '-fno-strict-aliasing' is used
---
- type is vpiPartSelect, not vpiMemoryWord
- left/right range is for part, not full word
- index is not valid for a part select
The user will now get a sensible error message if they pass part of an
array word to $dumpvars (GitHub issue #230).
This fixes the problem reported in GitHub issue #254, where if the
parser aborted on one compilation unit, spurious errors were reported
for the next compilation unit.
- make primitive redefinition a warning, not an error
- make edge-sensitive ifnone a warning, not an error
This allows Icarus to be used to simulate designs using third-party
cell libraries that contain such things.
bison 3.4.1 writes the header file before the c++ file. Our makefile
rules make the header files depend on the c++ files, so we need to
fix the timestamps accordingly.
The signed version of the power operation in vvp should only be used
if the exponent is signed. Both signed and unsigned versions will
produce the correct result regardless of the type of the base operand,
provided it has been appropriately extended to the result size.
When vpi_handle_by_name() iterates over the VPI objects in a scope, handle
the case that vpi_get_str() returns a null value. This currently occurs if
the scope contains an enum type definition, as vpi_get_str() is not
implemented for __vpiEnumTypespec.
Note we only want these enabled when building the compiler and runtime
binaries. If we included the ICARUS_VPI_CONST definition in the global
CPP_FLAGS, that would propagate to the flags used by iverilog-vpi, so
would affect compilation of user VPI code.
Currently $display et al. output nothing when the expression
corresponding to a %c format specification has the value 0. As
Verilog provides no other way to write raw bytes to a file, we
should allow 0 values to be written. Other simulators allow this.
- allow ICARUS_VPI_CONST to be pre-defined by the user
- use it for sizetf as well as for compiletf and calltf
- fix remaining warnings when it is defined as 'const'
When performing a signed division or modulus operation using native
arithmetic, trap the special case that the numerator is the minimum
integer value and the denominator is -1, as this gives an undefined
result in C++.
In traditional Verilog, each task_port_item must have an explicit port
direction.
In SystemVerilog, if the port direction is not specified, it should be
inherited from the preceding task_port_item for that task/function, and
only the first task_port_item should infer the direction to be 'input'.
Predefined macros get stored in the precompiled macro file that gets
read back in when processing library files. This means the predefined
macros get processed twice. We need to skip the check in this case.
A common use case (prior to the introduction of localparam) was to
use macros to define constant values, and to put global constant
values in an include file that gets included by each source file.
This will generate a lot of spurious warnings if we warn about all
redefinitions. Make this new option the default for -Wall.
In vvp, the __vpiSignal object holds a pointer to the scope containing
the signal. This was getting set to the current scope when the net was
finally resolved, rather than to the scope where the net was declared.
This implements and enforces the full set of rules for determining
timescales in SystemVerilog. The previous relaxation of the rules
that allowed timescales to be redefined within the compilation unit
scope has been removed. Time unit and precision redeclarations are
now recognised after a nested module declaration.
This relies on using the automatically generated name for the unit scope.
This could collide with an escaped identifier, so it would be better to
identify the scope by a reference to the PPackage object, but for now,
do it the easy way.
The compilation unit scope is now treated as a specialised form of
package (with an automatically generated name). All items declared
outside a design element are added to the current compilation unit
package. Apart from when searching for a symbol, once we get into
elaboration we can treat these just like any other package.
This adds a -u option to the driver to allow the user to specify that
they want each source file to be treated as a separate compilation
unit, and modifies the compiler to accept a list of files (either on
the command line or via a file specified by a new -F option). This
list of files is then preprocessed and parsed separately, causing all
compiler directives (including macro definitions) to only apply to the
file containing them, as required by the SystemVerilog standard.
Two fixes needed:
- when searching for a base class, we need to look in the root scope
if the base class isn't found in the scope hierarchy
- the classes in the root scope need to be stored in an ordered
list, not a map, to ensure they are elaborated in the order they
were declared. Without this, the compiler may try elaborating an
extended class before its base class is known about.
Verilog spec has a very nasty system of macros jumping from
file to file, resulting in a global macro scope. We abosolutely
MUST track macro redefinitions and warn user about them.
Signed-off-by: Andrew Andrianov <andrew@ncrmnt.org>
If a thread becomes detached due to a join_any statement, that
thread must not attempt to join its parent, even if the parent
is waiting on a subsequent join statement.
This occurs when tgt-vvp attempts to generate a C4<..> constant
value with a bit width >= 65536. The actual failure occurs in the
StringHeap class, which originally supported a maximum string length
of 65535. This fix enables the StringHeap class to support any size
string (provided the system has sufficient memory).
Normally there is at most one signal attached to a vvp functor, but
due to port collapsing, there can be more than one. If these signals
are array words, we need to trigger vpi callbacks on all the associated
arrays when the functor value changes.
If there is a syntax error in the source code, pform_makegate may be
passed a null list of port connections. The error is already reported,
so we just need to ignore it.
Return and print an error if iverilog is unable to open dependencies
file. User can pass e.g path to existing directory in '-M' option,
which makes fopen to return NULL followed by crash in fclose.
(* my_fancy_attribute *)
foobar1 foobar (clk(clk), rst(rst) ...);
- Modifies PGModule to hold the attribute map (can be verified with pform_dump)
- pform_make_modgate(s) bind the attributes from the parser to the above map
- The attributes from PGModule are inserted into the NetScope of that module
PGModule::elaborate_scope_mod_instances_
- Currently these attributes automatically make it into netlist
- These attributes are accessible via ivl_scope_attr_cnt and ivl_scope_attr_val
from ivl_target.h
This was already supported in command files, using the '-v' flag.
'-v' is already in use on the command line, so use '-l' instead,
and make that an alias for '-v' in command files.
Change cbReadWriteSynch and cbReadOnlySynch to interpret the passed
time value as a relative delay, not an absolute time. This matches
the behaviour of other simulators.
Replace explicit comparisons against generation_flag with calls to
the gn_system_verilog helper function, both for code clarity and
to fix a couple of bugs. Also simplify the implementation of the
function, as we already rely on the generation_flag enumeration
being an ordered list.
Arrays type match if they have a common parent, instead of the
element type. Now (un)signed & std_logic_vector types do not match,
as it should be in VHDL.
Pull request #116 added the ability for the iverilog driver to determine
ivl_root from the location of the iverilog executable (this is needed to
support relocation at the time iverilog is installed). However, the code
did not support the possible variations in the library path name.
An out-of-range constant bit select on the LHS of an assignment was being
treated as an error, whereas an out-of range constant part select would
only result in a warning. In any other context, either case would result
in a warning, so convert the error to a warning.
In addition, all warnings for out-of-range or undefined constant bit/part
selects should be controlled by -Wselect-range.
When emitting a design, all scopes must be emitted before emitting any
top level task/function/method definitions, otherwise hierarchical
references can't always be resolved.
SystemVerilog allows tasks, functions, and classes to be defined at the
root level or inside packages, so we can't rely on an enclosing module
being present to provide the timescale.
This just enables the compiler to parse path declarations that
contain part selects. As for bit selects, the part select is
discarded, and if elaboration of specify blocks is enabled,
the path declaration will be applied to the entire vector. If
elaboration is enabled, a warning message will now be output
when a bit or part select is discarded.
This does a better job of setting the intermediate expression types
and widths when calculating the canonical index into a packed array.
It still doesn't properly handle out-of-bound indices (br953).
The existing support for ``, `", and `\`" did not work in nested macro
definitions. Note that the new implementation only detects and replaces
these sequences inside the macro text (as required by the IEEE standard),
whereas the old implementation would detect and replace them anywhere in
the source files.
SystemVerilog allows a mixture of procedural and continuous assignments
to be applied to different parts of the same vector. The previous attempt
to make this work for non-blocking assignments was flawed (see preceding
fix for vvp_fun_part_pv::recv_vec4_pv). Instead, handle this case by
converting the non-blocking assignment into a delayed force statement,
which matches the way mixed continuous and blocking assignments are
handled.
Most vvp functors need to support recv_vec4_pv. Any that are strength-aware
also need to support recv_vec8_pv. Note the simplifying assumption that is
documented in the base class recv_vec4_pv_ implementation.
If all three rise/fall/decay delay values are constant, we can use
the vvp .delay statement variant that takes three literal numbers.
If not, we have to use the variant that takes three net inputs. If
some of the delay values are constant, we need to create constant
drivers for those delay inputs.
If a static variable declared in a task, function, or block has an
initialisation expression, SystemVerilog requires the declaration to
have an explicit static lifetime. This is supposed to be a compile
error, but for now just output a warning.
Implementing this required adding support in the parser for explicit
lifetimes in variable declarations. For now, just output an error if
the user asks for a lifetime that isn't the default for that scope.
A conditional clause that doesn't drive any bits of a particular nexus
should not affect the bitmask generated for that nexus. The completely
undriven case is handled by the enable signal.
Currently limited-length strings (e.g. string(1 to 4)) are
emulated using 2D array of bits (e.g. bit [1:4][7:0]).
Because of that, ivl treats them as standard vectors and
$display() does not show them as strings. Now, they are
wrapped with $sformatf("%s", ..) to fix it.
A compressed assignment statement should give exactly the same
result as the equivalent uncompressed statement. This means
that the type (signed/unsigned) of the LHS affects the type of
the RHS expression (unlike in normal assignments). We need to
take care that bit/part selects and concatenations are correctly
identified as unsigned values, even in the cases where they
reduce to a single whole signal.
The type of extension (zero/sign) is determined by the expression
type, not the operand type, so we need to cast to the expression
type before extending the value.
Added the ability to coalesce set/reset values to different parts
of the same vector. Also added a check that all bits of the vector
are assigned a value.
Enabled coalescence of asynchronous set/reset part-vectors
The destructor needs to delete the stored NetEvent objects. Failure
to do this was causing a compiler crash after synthesis if the
nodangle functor was disabled.
Synthesis could only handle relatively simple conditional constructs.
This rework aims to make it handle anything the user can throw at it
(or output a sensible message as to why it can't).
Flip-flops are generally modelled in behavioural code using non-blocking
assignments. This change makes the synthesised code behave the same as
the behavioural code. It's a more realistic model of a real flip-flop
too, which will always have some clock-to-output delay.
In case of a vhdlpp-specific () call, the timeformat suffix string was overridden,
therefore it has to be restored to the previous value after the call.
The .scope needs to be aware of return types so that the %call/vec4
function knows how to intialize the return value. We also need to
extend the %ret/vec4 to support writing parts of the return value.
Synthesis does not currently support some commonly used styles for
representing flip-flops, e.g.
q <= 0;
if (en) q <= 1;
or
if (clr) q <= 0;
if (set) q <= 1;
For now, output a "sorry" message.
The elaborator allows the RHS of assignment to be wider than the
LHS. When using an if statement to represent a mux, this meant the
mux inputs could be different widths, resulting in an assertion
failure during synthesis. The fix is to prune the RHS to match the
LHS for each assignment. This has the benefit of minimising the
mux width.
When a binary (in)equality comparison has a constant left operand,
the tgt-vvp code generator swaps the left and right operands to
allow the cmpi instruction to be used. The code for swapping the
operands was incorrect.
Create The %callf/* opcodes to invoke user defined functions in a
more specialized way. This allows for some sanity checking on the
way, and also is a step towards keeping return values on stacks.
Otherwise it is not possible to modify their values in subprograms.
Argument elaboration has been moved to a separate function, so now it is
common for procedure and function calls.
This way it is possible to have limited size strings. Previously they
were translated to unpacked array of bytes, which cannot be assigned as
it was a string.
Since glibc version 2.20, _SVID_SOURCE is deprecated, see
'man 7 feature_test_macros'. To be able to compile this code without compiler
warnings in new and old glibc versions, both _DEFAULT_SOURCE and _SVID_SOURCE
must be defined.
Before this patch, only literals on the right side of a < compare
(or left side of a > compare) would be blended into a %cmpi instruction.
This patch broadends the cases where the %cmpi can be used.
In generate blocks such as for loops, there may be many generated
scopes that have the same generated name. But in these cases, there
is an index number in the hname that can be used. So do so.
The bug report was for an assertion failure when a number contained only
a lowline (e.g. 'b_), but the standard says that a number can't start
with a lowline (e.g. 'b_1). The parser already rejected these cases for
decimal numbers, but allowed them through for binary/octal/hex numbers.
parse.y has been updated to allow declarations outside a module (legal
in SystemVerilog), but not all types of declaration are supported yet.
Output a sorry or error message as appropriate.
The reported problem was caused by a null statement in a case statement,
which caused the check for an infinite loop to fail. Further testing
exposed more problems with null statements in loop statements - these
caused crashes earlier in elaboration.
This is syntax permitted in 1364-2001 but removed in 1364-2005.
Also update the iverilog man page to document the anachronisms warning
class that warns about use of this feature when a later generation is
selected.
The compiler was emitting a "sorry" message and aborting compilation when
it encountered attributes on a wire declaration/assignment. Change this
to a warning, as most attributes are ignored anyway.
"# include <string>" was added so "Microsoft Visual Studio Express 2015 RC Web" could compile it without error. "static void operator delete[](void*); was preprocessed so "Microsoft Visual Studio Express 2015 RC Web" could link it without error for a function not yet implemented.
"child->delay_delete = 1;" was added, for when building with "Microsoft Visual Studio Express 2015 RC Web" in DEBUG mode, so that pr2909555.v would pass with -strict, otherwise it would cause memory access error will trying to access the previously deleted "child" variable.
First and second areas were changed for "Microsoft Visual Studio Express 2015 RC Web" so that gold files would match. For the third area of change, "Microsoft Visual Studio Express 2015 RC Web" wanted to print 6 zeros after the decimals for the values of 0.0 and -0.0, and then the gold files wouldn't match.
Changes so "Microsoft Visual Studio Express 2015 RC Web" could build it without a bunch of runtime errors and crashes during regression testing. When declaring an bitfield variable of type enum in a struct, the enum has to have an underlying integer type for MSVC++ when compiling a C++ file, and for these cases, it had to be unsigned integer for everything to work okay during regression testing.
Changes so "Microsoft Visual Studio Express 2015 RC Web" could build it without a bunch of runtime errors and crashes during regression testing. When declaring an bitfield variable of type enum in a struct, the enum has to have an underlying integer type for MSVC++ when compiling a C++ file, and for these cases, it had to be unsigned integer for everything to work okay during regression testing.
First area of Change for "Microsoft Visual Studio Express 2015 RC Web" was for compiling with error when NDEBUG defined. The second and third areas of change for "Microsoft Visual Studio Express 2015 RC Web", the dynamic_cast has to come first so parpkg_test.v, parpkg_test1.v, parpkg_test2.v would pass.
Changes for "Microsoft Visual Studio Express 2015 RC Web" to first check for a dereferencable iterator so pr1741212.v, and many others, will pass with a DEBUG build.
Implicit ports may be unnamed, either because the port expression
is not a simple/escaped identifier, or because there is no port
expression. To handle these cases, error messages should report
the port position as well as the port name.
In the special case that a net is attached to an island port, values
driven onto the net via the VPI must go to the functor, not the filter,
so that they propagate through the island.
When putting a value onto a wire, the value needs to be sent to the
filter, not the functor (the functor may be part of the expression
that drives the wire).
Force and release weren't implemented properly (or at all in the
case of real values). They need to behave the same as the force
and release operations in vthread.cc.
vvp_net_t::force_vec4 propagates all bits of the forced value passed
to it, regardless of the mask value. I can't see any way to fix this
directly, so instead make sure anything that calls force_vec4 sets
the unforced bits of the passed value to the correct value.
Conditions to detect rising/falling edges were incorrect.
VHDL standard specifies it has to detect the current value,
rather than compare against the previous one.
Although the IEEE standard doesn't explicitly state this is required,
the examples added in the SystemVerilog standard show that this is
expected.
Also add a preprocessor lexical rule to recognise `` inside a macro
definition when it is not immediately followed by an identifier.
When replacing macro formal parameters, the preprocessor should not
replace matching strings that are not complete tokens. The test for
this was incorrect, and failed when a match was found at the start
of the replacement text.
This forces <stdout> to be unbuffered. This is useful when using the
mintty terminal emulator in Windows (as used by MSYS2 and CygWin),
which identifies as a pipe, not a tty.
Removed obsolete -m32 and -ivl options from iverilog-vpi man page
and revised description of -mingw option. Also removed duplicate
descriptions of --cflags, --ldflags, and --ldlibs options. Updated
link to main iverilog web page in all man pages.
Defining __USE_MINGW_ANSI_STDIO=1 provides C99 compatible printf
and scanf routines, which avoids the need for workarounds for the
various failings of the Microsoft C runtime library.
The Microsoft C runtime does not support the %zu and %zd formats.
Previously these were replaced with %u and %d, but for 64-bit we
need to use %llu and %lld.
iverilog-vpi now automatically finds the IVL root directory,
eliminating the need for the -ivl option. Also, if the MinGW
root path hasn't been added to the registry, it now searches
the system path for it.
The -W option does not (currently) support comma separated lists and
silently ignores any string that doesn't match a known warning class.
Fix by outputing a warning message when the -W argument is unknown.
The compiler was correctly detecting and reporting errors in loop
expressions and statements, but then crashing when it tried to build
the sensitivity list. Fix this by not adding a loop statement to the
netlist unless all its components have been successfully elaborated.
It was required to make it possible to use typedefs in port types.
Types from packages are emitted in `ifdef..`endif instead of package..endpackage.
The purest solution is to keep package..endpackage and emit appropriate prefix.
Also, it would be great to have constants emitted in the same way.
__vpiVThrVec4Stack::vpi_get_value_int_ was always treating the thread variable
as unsigned, rather than observing the value of __vpiVThrVec4Stack::signed_flag_.
Not sure why this was done - none of the regression tests broke when I changed
this.
This causes vvp to evaluate all the input expressions for a user
function call before assigning any of them to the function input
variables. This stops the input variables being overwritten if
the same (non-automatic) function is used in one of the input
expressions.
When performing constant propagation, we need to take into account
values driven through a tran object. For now, be pessimistic, and
assume that all tran objects connect to a variable driver.
A disable statement can terminate a thread whilst it still has
local variables on the stack (e.g. the loop counter for a repeat
statement). We need to clear the thread stacks when this happens.
Using a UL constant in a unit64_t context does not work on a 32-bit
machine since UL is 32-bits. Instead create uint64_t constants using
static casts and the appropriate bit operators.
If either the index or part offset expressions generate an undefined
value then the assignment is skipped. This patch reworks the code that
handles the flags used to detect this. For some simple cases a global
flag is not needed, but for other cases one is needed since there are
two expressions that can generate an error and even when there is only
a variable expression this error state needs to be preserved if there
is a variable delay. An undefined delay value defaults to zero and is
not an error.
This should not change the functionality, but to save space trim any
unneeded bits from a binary constant. Also for the case of emitting
a signed undefined value when the allow signed flag is not set add
the width to the constant.
When generating code for a condition expression, i.e. directly
before a %jmp/X statement, try to generate the result into the
flag bit without passing through the vec4 stack. For example, the
%cmpX/X instructions generate results into the flag bits, so it
makes no sense to push these bits into the vec4 stack then pop
them back into the flag bit. So try to handle this case.
These bypass the vec4 stack in some common cases, saving instructions
and vec4 manipulations.
Also, minor improvement to the %flag/set/vec4 statement.
Kill a few warnings.
- Have %pushi/vec4 handle some special cases optimally.
- Eliminate some duplicated method calls in %load/vec4.
- Optimize the vvp_vector4_t::copy_from_ method by inlining
some parts.
Added various error/warning messages for behaviour not supported
in synthesis. Also give correct behaviour when multiple case item
expressions evaluate to the same constant value.
When unsized literals are used in case item expressions, it is likely
that the calculated expression width will be larger than necessary to
unambiguously select the correct case item (particularly when using
"strict" expression elaboration). This patch adds an optimisation
step that prunes the expressions to the minimum necessary width.
If an error is found whilst elaborating a range expression in a signal
declaration, create a dummy range and continue elaboration. This stops
the compiler reporting an error every time that signal is referenced.
When checking that an enumeration value is in range we need to cast it to
a 2-state value so that when we compare it we get a true or false value
instead of an undefined value. Undefined bits in the comparison return
undefined which is not logically false.
If elaboration of the msb or lsb expression in the range of a vector
type specification failed (due to an error in the Verilog code being
compiled), an assertion failure was being triggered when the compiler
attempted to evaluate the expressions. Bypassing the evaluation (and
using a default value) should allow us to recover from the error.
The code to get the correct modpath delay for a given edge had the X and Z
entries swapped.
When putting a delay from the VPI the 2 delay to twelve delay mapping was
incorrect and the to/from X delays were also not being calculated correctly.
Note: I could not find any info about the integer() function, but it is
used in the VHDL standard packages (e.g. math_real, see:
http://www.csee.umbc.edu/portal/help/VHDL/packages/mathpack.vhd)
Real numbers are rounded, this is compatible with ModelSim behavior.
VHDL does not allow to specify the size of returned std_logic_vector,
whereas Verilog requires the size to be known in advance. The size of
the vector is determined by checking the type of expression used in the
return statement.
This adds the runtime support for class properties that are classes
to be arrayed. Add a means to define the dimensions of a property
in the vvp format, and add functions for setting/extracting elements
of a property.
We need the scope where the class is defined so that it can find
types in that containing scope. Note that most definitions cannot
escape into the the lexical scope of the class, but some can.
This goes all the way down to the vvp level, where we create support
for arrays of objects, generate the new code in the -tvvp code
generator, and elaborate the arrays in the first place.
This patch fixes the following enumeration bugs:
When looking for an enumeration look in the current scope and then
recursively in any parent scope.
Add enumeration definitions to a package scope.
The parser always passes a single NULL argument for system tasks. For a
method call which will add a signal to call the method on we need to
ignore this NULL argument.
If an expression contains a division, remainder, or right shift operation,
set the expression min_width to UINT_MAX to flag that the expression width
cannot be pruned. Using UINT_MAX ensures that the min_width won't change
as we continue to elaborate the expression.
Internally, treat the "$" as a special expression type that takes
as an argument the signal that is being indexed. In the vvp target,
use the $last system function to implement this.
This works by translating it to a $size() system function call.
The $size function is already implemented for dynamic queues and
it is easy enough to expand it for queues.
Once a signal/variable of unbounded array type becomes limited in its size, it
is emitted as a packed array. Therefore currently it works only for
bit/logic/reg/wire types.
Like this:
... if (ce0) foo <= foo_in;
... if (ce1) bar <= bar_in;
Note that this is within a block, and represents multiple FF nodes
with different clock enables.
When for example assigning to foo[<x>] within a contitional, and
doing synthesis, we need to create a NetSubstitute device to manage
the l-value bit selects.
Testing with 32-bit clang 3.3, with additional compiler flags
-Wsign-compare -Wundef
this patch eliminates the following warnings:
config.h💯6: warning: 'UINT64_T_AND_ULONG_SAME' is not defined, evaluates to 0 [-Wundef]
vcd_priv2.cc:233:12: warning: duplicate 'extern' declaration specifier [-Wduplicate-decl-specifier]
parse.cc:6496:9: warning: comparison of 0 <= unsigned expression is always true [-Wtautological-compare]
parse.cc:6499:13: warning: comparison of 0 <= unsigned expression is always true [-Wtautological-compare]
parse.cc:6502:9: warning: comparison of 0 <= unsigned expression is always true [-Wtautological-compare]
parse.cc:6510:53: warning: comparison of integers of different signs: 'const unsigned int' and 'int' [-Wsign-compare]
Changing the vlltype elements from unsigned to int reconciles their
type with the native bison YYLTYPE structure.
Before this patch, WARNING_FLAGS applied to both C and C++,
and WARNING_FLAGS_CXX applied to C++ only.
This patch adds a WARNING_FLAGS_CC that applies to C only.
That change should be generally useful; in particular the C
code is almost ready for -Wstrict-prototypes, which does not
apply to C++.
-Wextra (or -W) used to only apply to C++ via WARNING_FLAGS_CXX.
This patch moves it to WARNING_FLAGS, to apply to both C and C++.
Unfortunately, that triggers a ton of warnings.
For now, cover most of the new warnings up by adding
-Wno-unused -Wno-sign-compare -Wno-type-limits
to WARNING_FLAGS_CC. In the long run, I want to change the C coding
style, and take off these disable-warning flags. But those changes
can dribble in as separate commits; this patch is big enough already.
Actually fix a couple missing-field-initializers in libveriuser/veriusertfs.c.
119 formal void parameters added to keep -Wstrict-prototypes happy.
Process found one real missing prototype in vpi/vcd_priv.h:
EXTERN void vcd_names_delete(struct vcd_names_list_s*tab);
8 such warnings left, all in Tony's code
The only known problems left are in files imported from gtkwave,
if not for them you could turn on -Wsign-compare.
Assumes c99 for c code, so the scope of for-loop indexes can be made sane.
This generates an EQZ LPM device that carries the case-z-ness to
the code generator.
Also add to the vvp code generator support for the EQZ device so
that the synthesis results can be simulated.
Account for the wildcard devices in the sizer.
It shouldn't be possible, but sometimes is, that a NetCondit is
missing input nets during async synthesis. Handle this by generating
a place-holder net and printing a warning.
Second try cleaning up cast-alignment problems surrounding need_result_buf().
Clang gave a bunch of warnings like
vvp/vpi_const.cc:196:34: warning: cast from 'char *' to 'p_vpi_vecval' (aka 't_vpi_vecval *') increases required alignment from 1 to 4 [-Wcast-align]
This version is verbose and changes the prototype for need_result_buf().
But it is semantically (c++) correct, and makes need_result_buf() feel like malloc().
" characters in strings must be escaped when the compiler writes a
quoted string to a vvp script. This patch fixes up a few places where
this wasn't being done.
Better handle the case where the output for some pins comes from
an earlier assignment. This allows for multiple ways to specify
default outputs for some cases: the default: case and pre-assignment.
When conditional ports are blending (by allowing NetPartSelects be
connected together to the outputs) make sure there isn't an accidental
overlap of drivers that invalidates the process.
When a mux (NetCondit) is only writing to a part of the output
vector (and using only a part of the inputs) then blend the mux
output with the previous statement output.
If both conditions of a NetCondit device assign to the same subset
of l-value bits, then generate a smaller NetMux device that only
switches the affected bits.
This is an error in traditional Verilog and a unsupported feature in
SystemVerilog. Fail gracefully with a suitable error/sorry message.
Do the same for task declarations.
In a design, there may be lingering NexusSet objects, or the
nodangle may itself use NexusSet objects. This creates links,
and this should not confuse the functor.
While we are at it, clean up some handling of events structures.
It is possible for an assignment statement to be part of a
grander complex that has lots of outputs, not all handled
by this particular assignment. In that case, the assignment
may need to figure out which output it is supposed to bind to.
This required keeping for-loops as actual things through the
netlist form so that the synthesizer can get at and understand
the parts of the for-loop. This may improve vvp code generation
in the future, but for now continue to present to the vvp code
generation the block-while form.
Some types, i.e. vector types with parameterized dimensions,
may have different elaboration results in different scopes.
Handle those cases in the elaboration caches.
When the clock enable is not generated, don't try to hook it
up then detach it. That will make a mess that needs clean up.
Instead, leave unused ce pins (Enable) unconnected.
Signals are collected in a link map that uses the Link class so that
it doesn't need to save Nexus objects. But naked uses of Link don't
set the node_ and pin_zero_ members. So initialize them to zero so
that Nexus scanners can skip these naked Links.
If statements within blocks can confuse the synthesizer when there
are outputs that are assigned ahead of the if statement. This patch
handles that case.
Some of the SDF warnings were mixing some of the scope path with the
instance name. These are now separated into just scope and instance name.
There was also a place where vpi_get_str() was being called twice in a
single print statement. This is illegal since vpi_get_str() uses a single
buffer and multiple calls will overwrite the buffer.
This function was apparently not well tested, because any use of
acc_handle_object() triggered a use of vpi_handle_by_name that was
buggy.
The implementation was awkwardly written, to parts of it were redone.
The tf_igetlongtime function may pass in any kind of object, so the
scale() function may need to convert an object handle to the handle
for the objects parent scope.
The netparray_t::slice_dimensions bug was the most insidious and
caused all manner of confusion. Also fix some other packed array
and unpacked array (and mixed) indexing calculations.
Get rid of the data_type, signed_flag, and range arguments to the
pform_module_define_port because they add no value within the
parse.y parser. Cleaning these out will hopefully ease the addition
of new functionality.
This can be handled entirely in the parser, where we rewrite the
syntax to me a begin/end block that contains the index variable
declaration and the for loop.
The root cause was that NetESignal::dup_exr() was not copying the calculated
type (signed/unsigned) of the expression.
In passing, found and fixed a similar issue when calculating a blended value
for a constant ternary expression.
%exec_ufunc assumed that because a function can never block, a call to
vthread_run() on the function code would only return when the final %end
instruction had been executed. This is not true if the function contains
a named block, which will be executed via a %fork instruction, allowing
the main function thread to suspend after a %join instruction. The fix
is to break %exec_ufunc into two instructions, the first setting the
function inputs and executing the function code, the second collecting
the function result. This provides the opportunity for the parent thread
to suspend after the %exec_ufunc instruction until all its children have
completed.
The vvp code generator was optimising away adds and subtracts where one
operand was a constant zero. This is not valid for 4-state arithmetic.
It was also optimising away multiplies by a constant zero - but in this
case getting it wrong and effectively multiplying by 1.
For shift operations evaluated at compile time, the compiler was converting
the right operand to a native unsigned long value. If the operand exceeded
the size of an unsigned long, excess bits were discarded, which could lead
to an incorrect result.
The fix I've chosen is to add an as_unsigned() function to the verinum class
which returns the maximum unsigned value if the internal verinum value is
wider than the native unsigned type. This then naturally gives the correct
result for shifts, as the verinum bit width is also an unsigned value.
I've changed the as_ulong() and as_ulong64() functions to do likewise, as
this is more likely to either give the correct behaviour or to give some
indication that an overflow has occurred where these functions are used.
When an expression is elaborated, the compiler converts multiplies with
one constamt zero operand into a constant zero value. This is only valid
if the other operand is not a 4-state variable.
Unsized expressions can expand to extremely large widths. Usually this
is actually a mistake in the source code, but it can lead to the compiler
temporarily using extremely large amounts of memory, or in the worst
case, crashing. This adds a cap on the width of unsized expressions (by
default 65536 bits, but overridable by the user), and causes a warning
message to be output when the cap is reached.
When performing the initial assignment for a procedural continuous
assignment, any previous continuous assignment to the destination
signal must be unlinked first, otherwise the initial value for the
assignment will propagate to any other nets that are driven by the
original source signal.
The verinum arithmetic operators now observe the standard Verilog
rules for calculating the result width if all operands are sized.
If any operand is unsized, the result is lossless, as before.
They also now all observe the standard rules for handling partially
undefined operands (if any operand bit is 'x', the entire result is
'x').
I've also added the unary '-' operator, and renamed v_not() to be
the unary '~' operator. This has allowed some simplification in
other parts of the compiler.
A procedural continuous assignment is supposed to be updated any time
a variable on the RHS changes. Currently this only happens if the RHS
is a simple signal.
In the case that the RHS of a procedural continuous assignment is a simple
vector that is wider than the LHS, changes to the RHS vector cause the
entire vector to be sent to port 1 of the LHS vvp_fun_signal object. This
vector needs to be coerced to the size of the LHS. Note that this is a
stopgap fix until vvp handles arbitrary expressions on the RHS of a
procedural continuous assignment.
Signed vector power operations were being implemented using the double
pow() function. This gave inaccurate results when the operands or
result were not exactly representable by a 64-bit floating point number.
During expression evaluation, the compiler attempts to optimise away
relational operations when one side is constant and all possible values
of the other side would result in the relation being true. This is not
a valid optimisation if the other side is a 4-state variable, as an
'x' or 'z' will result in the relation being unknown.
This changes the verinum pow() function to use the more efficient algorithm
used in the vvp runtime. It will still be slow if the left operand is unsized
and the right operand is large, as it will expand the result vector to avoid
overflow.
The vvp_vector2_t::pow() function is recursive, and performs a multiplication
operation on each step. The multiplication operator was expanding the result
vector to accomodate the maximum possible result value for the given operand
vectors, thus causing the execution time of the power operation to be
exponentially proportional to the exponent value. Both in this case and
in general, it is unnecessary for the multiplication result vector to be
expanded, as the compiler has already determined the required vector width
during elaboration, and sizes the operand vectors to match.
The vvp_vector2_t constructor that takes a vvp_vector4_t value was
documented as creating a NaN value if the supplied vector contained
any X or Z bits, but instead used the standard Verilog 4-state to
2-state conversion semantics (X or Z translate to 0). I've added an
optional second parameter to the constructor to allow the user to
choose which semantics they want, as both are needed.
The link was pointing to a page that said:
This page has been moved to http://iverilog.icarus.com, you will be forwarded there automatically in 3 seconds.
Please update your links.
So now it's updated
If the l-value is an unresolved wire, then elaboration can allow
the assignment as long as it is to bits that are not otherwise
driven. Handle this in some simple cases.
This means using some of the new vec4 infrastructure to get at the
data, instead of using the old thread bit pointers. In the process,
remove the vbit and vwid members that pointed to thread bits. Those
bits no longer exist.
When a module is instantiated multiple times, the enum
types contained within would cause trouble. This fixes
that by elaborating in proper scope context.
When creating a constant zero for implementing a unary minus operation
using a binary subtraction operator, the constant needs to be to exactly
the expression width.
Redsign the handling of the return value, including a rework of
the %vpi_func syntax to carry the needed information.
Add a few more arithmetic operator instructions.
This patchs adds support for the $dimensions() and $unpacked_dimensions()
array functions. Since the argument is only used to get the type information
these functions can always be evaluated at compile time.
For the following functions if the dimension argument is constant or omitted
and the first argument is not dynamic (a string or dynamic array) they will
return the specified information.
$left(), $right(), $high(), $low(), $increment() and $size()
Dynamic information and a variable second argument will be implement in a
future patch.
There were also some subtleties related to using enumerations
from typedefs and using them in multiple places. Fix various
bugs related to those issues.
The standard explicitly states that only object with a full name
can be searched for by name. A port does not have a full name and
hence should be skipped so that a different object (the signal,
etc.) can be returned. This patch adds code to skip ports when
searching for an object handle by name.
This patch fixes some leaks in the object stack when getting various
class properties. With this fix an assert can be added to verify that
the object stack is clean when a thread is exiting.
This allows for syntax like a.b.c where a is a class with member
b, which is a class with member c, and so on. The handling is mostly
for the support of compound objects like classes.
When a thread that has detached children is reaped the detached children
need to be fully detached so they can be reaped correctly. If they are not
fully detached then they may reference a parent that has already been
reaped (memory freed). Found with valgrind.
The code should only look at the real argument that exist any missing
arguments default to not being defined and hence needs to use the
default expression. Found with valgrind.
This gets nested l-values to (but just short of) the ivl_target API.
Now the elaborator can process nested l-values, but I haven't figured
out how to present that at the ivl_target.h API.
It is better to leave the handling of PChainConstructor calls to
the elaboration, instead of stripping them out early. This allows
for handling the arguments of the chain constructor in the correct
scope.
It is more common to find an unsized number on the right hand side
of a binary operator than on the left hand side, particularly for
comparison operations (e.g. x < 10 rather than 10 > x), so testing
the width of the right operand first is less likely to result in
the width needing to be retested. Counting the number of times an
operand width is retested when running the test suite confirms this;
before this change an operand width was retested 4869 times, after
the change an operand width was retested 99 times.
A BUFT is needed to allow a force to override the pull value. This had
already been done for pullup devices, so factor out the common code and
use for both pullup and pulldown.
Currently vvp only applies the pullup/pulldown for tri1/tri0 nets when
the net is not driven. The correct behaviour is to treat the pullup/
pulldown as an extra driver (with pull strength).
For synthesis we remove the output set of signals from the input set to
remove temporaries from the final sensitivity set. The @* construct also
uses the input sensitivity list, but because it can include statements
that cannot be synthesized we should not calculate the output set for this
case. Not find the output set is also a speed enhancement since the output
set was already being ignored later in the code for this case.
To be strictly compliant with the standard and compatible with other
EDA tools, unsized numbers should be treated as having a fixed size
(the same size as an integer). The -gstrict-expr-width option is
extended to allow the user to enable this behaviour.
This option is intended to make it easier to compare results from
Icarus with results from other simulators. For now, the only effect
it has is to change the default format for displaying real numbers
when no format string is supplied.
This includes adding support for returning strings from functions,
adding initializing new darray with array_pattern strings, and
assigning an array_pattern of strings to a preallocated darray.
Also fix up support for initializing array with simple string
expression.
When you have an expression like this (extreme example):
a[idx[1]][idx[2]*4 +: 4] <= #(idx[3]) 4'ha;
where a is a reg array and idx is a reg or net array. The retrieval
of idx[2] was clobbering index register 3, which was set before
evaluating the part offset expression, then used in the %set/av of the
array value. (likewise for idx[1] and idx[3]])
To avoid this issue, this patch adds and uses a new instruction
%ix/mov which simply copies one indexed register to another. When
necessary, expressions are first evaluated into temporary registers to
avoid clobbering, then moved in to place before the %*/av instruction.
Implements page 644 of IEEE 1800-2012.
`` is now overloaded with the Icarus-specific "stringify" expansions.
It is now used as indicated in 1800-2012 when appearing inside a macro
definition, and the Icarus way when not. To do so, it uses the fact
that istack->file is NULL iff we are processing expanded macro text,
which is a bit of hack but works as is.
`" and `\`" on the other hand are treated the same inside and outside
of macro definitions.
When a fork/join contains a task, the task completion may become
confused with the completion of another thread if any of the
threads are embedded in the main thread. So always create threads
for all the fork paths, and joins to match.
In the ASIC universe, it is (probably) OK to replace a DFF CE
with a mux of the D input with the Q output. The idea is that
if the CE is true, the DFF latches D, but if CE is false, the DFF
re-latches the current output.
Turns out that call to eval_expr is redundant, and in degenerate
situations can lead to so many wasteful calls to eval_expr that
elaboration performance suffers dramatically.
The signal bit numbering should be used for signals. This is
necessary for .model ports because the user specified numbers
are part of the interface, but once that is done, it is trivial
to follow it internally as well.
Instead of just translating a generate scope to a named begin/end scope
this patch creates a generate specific scope (vpiScopeGenerate) that is
of the vpiGenScope type. This may not match the standard 100%, but does
allow the FST dumper to denote generate scopes differently than the
other scope types. Most of the VPI code treats a vpiGenScope just like a
named block so only the FST dumper should have different behavior.
Add support for detecting when to add a $signed() or $unsigned() to
create a self-determined context. This makes the test in the test suite
pass, but there could still be issues
Since parameters are now passed by reference use that information to print
the parameter name in a select vs trying to figure it out by searching the
scope looking for a parameter with the same file, line and value information.
Only print the $signed() may need to be removed messages for a select
expression that will actually be cast to signed.
Use the actual parameter information to warn that -pallowsigned=1 is needed
for a parameter when the LSB > MSB.
For variable parameter selects (indexed and bit) pass the value being
selected as a parameter reference instead of just a numeric constant
so it is easy to get the underlying parameter information.
Move the parameter bit select code into its own routine and cleanup
the remaining general code.
This should not effect the VVP code, but the ivl_expr_parameter(<expr>)
routine can be used to get at the actual parameter information in the
vlog95 target.
Static properties are like variables in a named scope.
Detect these variables during elaboration so that the
code generator just sees them as variables.
This implementation works by detecting assignments
to constant properties in elaboration. Allow initializer
assignments to assign to the constant, error all other
assignments, and otherwise treat the constant like any
other property.
Class types that have both implicit construction and
an explicit constructor can blend the implicit and
explicit construction into the "new" function defined
by the user. This doesn't change the behavior any, but
removes a function call and related scope.
The actual signal code is trivial, but the emit expression code needed
to be enhanced to pass a flag that says if one of the arguments in a
binary (except the shifts) or ternary (excluding the condition) context
is unsigned. This information is used to prevent emitting an explicit
$unsigned() for a signal that is used in this context since it will be
implicitly cast to unsigned.
This patch adds support for finding and adding $signed() and $unsigned()
to procedural expressions for the binary, unary and concatenation
operators. Selects have partial support. The select implementation
uncovered limitations in the compiler that need to be fixed before they
will work 100%. Most of the limitations currently generate a message
about the issue.
We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
If constant functions are exited by a return/disable, fix
the leaked "disable" flag that causes blocks in the next
try at the function to not work.
There are also a lot of debug messages added to help find
this and similar problems.
The VHDL to_unsigned function with to arguments is best handled
in the ivl elaborator, so have it generate an $ivlh_to_unsigned
function call in the vhdlpp code, and implement it in the ivl
core.
Also, implement the 'length attribute as a $bits() call for
similar reasons.
The package emit of types and constants needs to know which names are
from the current type and which are imported from libraries. Rework
the scope handling of those names so that the information is preserved.
For constant bit/part selects, issue a warning if the select is out
of range or an undefined value. In any case, the RHS value should be
discarded, and the actual assignment should be skipped.
If a VPI call with real arguments has no calltf function, we still
need to pop the arguments off the vthread stack. Similarly, if it
has a real result, we need to push a value onto the vthread stack.
For constant word indices, issue a warning if the index is out of
range or an undefined value. In any case, the RHS value should be
discarded, and the actual assignment should be skipped.
Class constructors are the "new" method in a class description.
Elaborate the constructor as an ordinary method, but the only
way to access this method is to implicitly call it. The elaborator
will take the constructor call and generate a naked "new" expression
and implicit constructor method call with the object itself as the
return value.
The changes in COPYING are mostly cosmetic and use <year> vs 19xx, etc.
Also update the tgt-vlog95/Makefile.in copyright to match the formatting
in the FSF version.
If a logical pull device is converted into a CA then it is an assignment
with strength, so just emit the appropriate constant to get the correct
functionality (e.g. 1'b1 for a pull up and 1'b0 for a pull down).
Also add missing file/line information.
There was one section of code in the tgt-vvp back end that was using
deprecated functions. This patch fixes that. The functionality is still
missing (force/assign to part of a vector), but the code now compiles
cleanly (no warnings).
This patch finishes the code needed to translate a SystemVerilog package to a
module with a special name. It also adds code to report that class scopes are
not supported and treats both a class and package as a top level scope.
Rework lexical support for PACKAGE_IDENTIFIER so that the lexor
can help with package scoped identifiers.
Pform package types and package functions up to elaboration.
Add support for case, forever, and repeat statements in constant
functions. Also fix a bug in the constant function implementation
of NetESelect when used for zero/sign extension.
The compiler was treating case and case item expressions as
self-determined. They should be context-sensitive, just like
the operands of a comparison operation.
Emit the elaborated class methods. Also generate root scopes to
represent the classes in order to hold the methods. These scopes
can also in the future be used to implement static properties.
This patch implements the evaluate_function method for the NetDisable
and NetSTask classes. It also makes the checks for a function being
constant work when the function contains nested scopes (named blocks).
Pure functions with constant operands can be evaluated at compile
time rather than at run time. This patch provides a global control
to enable this optimisation. Until constant function support is
complete, by default it is disabled.
If a ternary expression with mixed logic and real operands is
short-circuited and the logic value is selected, that value
should be cast to a real value.
IVL_VT_NO_TYPE is now used to signal an untyped LHS in a parameter
declaration. The parser function that handles specparam declarations
needs to do this too. Also, although it should never happen, make
sure we don't set the expression width in a NetECast object to a
negative number. Make constant evaluation of NetECast objects
observe the expression width.
This patch fixes a few issues/bugs that showed up when testing the
fixes for implicit casts:
1. Make the compile-time implementation of $abs, $min, and $max match
the run-time behaviour (system functions can't be polymorphic).
2. Correctly set the type (signed/unsigned) of the result of an
assignment inside a constant user function (the LHS should not
inherit the type of the RHS).
3. Fix a bug in the verinum(double) constructor (insufficient bits
were allocated in the case where the double value rounded up to
the next power of two).
This patch adds support for bool/bit vector types on the LHS of
a parameter declaration and ensures implicit casts in parameter
declarations are performed where necessary.
This patch adds support for implicit casts to the elaborate_rval_expr()
function. This will handle the majority of cases where an implicit cast
can occur.
A package can have parameters, but it does not have specparams or
keep the order the parameters are defined. This patch skips these
items if the scope is not a Module.
There are limitations with this since the compiler does not pass all
the information that was present in the original source, but it is enough
to get a valid simulation result. It is not enough for timing analysis!
specparams are also incorrectly translated to parameters so they show up
in the wrong place.
If modules instantiations were always handled correctly this would not be
needed, but for now looking for the nexus driver outside the scope is
needed to make some of the tests work.
This was temporarily implemented to just copy definitions to the
local scope, but the better method is to create a PEIdent that has
the package attached to it.
In SystemVerilog a task or function can initialize a variable in a task or
function. In Icarus this is done by creating an initial block that does
the assignment. We can translate this by emitting the initial block in the
enclosing module scope. This is not 100% correct since SystemVerilog
requires the initialization to be done before the other initial/always
blocks are processed. For SystemVerilog the current Icarus behavior is
incorrect, but even if it had a new process type that ran before the other
ones the best I can do for vlog95 is emit it before the normal module
processes which currently works.
In the starting comment say if the conversion was done with signed support.
If there were errors then add a comment at the end of the file that says
how many errors occurred and add a line after this that prevents the file
from running with out an error. This requires the user to see that errors
occurred and remove the offending line if they want to use the file anyway.
For a LPM constant we need to pass the sign information so that the vlog95
code generator can create the correct constant. Also when using the
sub_net_from() routine the numeric constant should have the same sign as
the signal so that it can also be displayed correctly.
Since the vlog95 code generator needs the strength information we do
not want to hide it behind a concat-Z optimization. For now we abort
the optimization, but in the future we could add parts of this back
in (e.g. all the drivers have matching strength then replace with a
normal concat and a buf-Z if the strength are not both strong. The
original buf-Z should be removed to reduce the number of LPM devices).
The Verilog-A abs(), min() and max() functions can be converted if the
expressions do not have side effects. Also note the new, null and class
property operators from SystemVerilog are not supported.
SystemVerilog allows a function to be called without an assignment for
the return value. This patch adds a warning that Icarus does not currently
support this and provides a place to add this functionality later.
This patch implements the evaluate_function method for the NetEBBits,
NetEBDiv, NetEBLogic, NetEBMinMax, and NetEBPow classes. It also
factors out some common code into the NetEBinary class.
Currently, when a variable expression is passed to a system task,
the expression value is stored in thread memory. Values stored
in thread memory cannot safely be passed to $strobe or $monitor,
because the thread memory may get reused or deallocated before
the $strobe or $monitor task actually executes. As a temporary
measure, we just trap this case and terminate with a "sorry"
message. A proper fix would require the expression value to be
calculated at the time the $strobe or $monitor executes, not at
the time it is called.
This is rather a pointless sort of thing, but it does turn from
from time to time, for example when constant literals (with no x or
z bits) are given strengths. So handle .net8/2s and .net8/2u the
same as .net8.s and .net8 objects.
If a strength aware net has an unambiguous HiZ1 strength, VVP treats
it as a logic '1'. It should be treated as a logic 'z'. An ambiguous
HiZ1/HiZ0 strength should also be treated as a logic 'z'.
L-value bit selects were incorrectly converting an undefined index to 0.
L-value part selects were asserting if an undefined index was given.
This patch unifies how all these are handle (including indexed part selects).
The base is set to an undefined value and an appropriate width is used.
A warning message is always printed since this is not a simple out of
range issue. It is the responsibility of the code generator to skip the
assignment, but we always want to execute the R-value since it could have
a side effect.
When VVP compiles a .array statement for a net array, it does not
know the data type, so initialises the array signed_flag to false.
We need to set the signed_flag to the correct value once we know
the data type, to allow the VPI routines to correctly format the
data.
When checking with valgrind clean up the following:
The arguments for invalid task/function calls.
The simulation callback queues (only needed when the runtime aborts).
Call pthread_exit(NULL) just before exiting to cleanup dynamic loading.
The vvp_darray_real class cal be used for static arrays as well
and this is a more general solution anyhow. Kill the now useless
vvp_realarray_t class.
If a signal s driven by multiple non-overlapping NetPartSelect(PV)
objects, then combine them into a single NetConcat object. This
eliminates the need for resolvers in the target.
This provides the ivl_target.h interface for class definitions
and expressions, the vvp code generator support for class objects
and properties, and the vvp run time support. Trivial class objects
now seem to work.
Add properties to the classes, and elaborate expressions that
have class properties. Describe class object property references
all the way down to the stub target.
Create stub class objects at the vvp level and generate the code
to invoke that stub. Implement the routines needed to implement
a test for null object references.
The code that calculated the canonical index for a multi-dimensional
array access did not correctly estimate the index expression width
in the case that the first index value was a constant zero. This
patch fixes the problem, and, in passing, also makes the expression
calculation more efficient if any of the indices are constant zeroes.
This will hopefully improve performance slightly, but also this
intended as a model for what to do when I get around to doing the
same thing to other data types.
Strings, when put into dynamic arrays, are treated as first class
types much line reals. Add the code generator and vvp support for
this situation. Also fix a bug distinguishing between character
selects from strings and select form arrays of strings.
This involves working out the code to get the base type of a select
expression of a darray. Also added the runtime support for darrays
with real value elements.
Clean up the vector4_to_value to use templates and explicit
instantiations. This makes the interface much cleaner for a
wider variety of integral types.
This patch updates the vvp code so it will compile with the valgrind hooks
again. There are still new constructs that need to be cleaned up correctly
and some old constructs were changed enough that the old code no longer
works, but the rest of this can be done as an incremental improvement.
In generate for blocks, there is a genvar that can be used in
expressions within the generate block. Generate this genvar in
the generated output, matched to the generate scope.
Windows and hence mingw does not follow the standard regarding the return
value of vsnprintf(). The mingw code needs to iteratively search for a
buffer large enough to print the output.
The second call to vsnprintf() needs to have a copy of the argument list
so it can run correctly. On some system vsnprintf() destorys the original
argument list.
When sending a string to a system task/function allocate the space needed
to avoid truncating the string vs using a large fixed buffer.
In vvp allocate and use an exactly sized buffer for the MCD print routine if
the fixed buffer is not large enough. Using a fixed buffer keeps normal
printing fast.
defparam assignments found inside a generate block were being stored
in the enclosing module scope. They should be stored in the generate
block scope.
Also removed the genvar list from the PGenerate class, as this is
already declared in the base LexicalScope class.
This patch updates the code to translate the SystemVerilog assignments with
an opcode to the appropriate vlog95. This includes ++ and -- when used in
a statement context. The ++ and -- operators are not currently translated
in an expression context. This translation only occurs in two places:
A simple assignment statement (foo += 2;) and the increment of a for
statement. I still need to check if there are other places where these
operators are allowed.
These two typedefs exactly matched earlier ones in the same scope and
gcc was complaining that they were shadowing the previous definitions.
Since the definitions matched exactly just deleting the second
typedef was acceptable.
SystemVerilog supports using assignments with opcodes (e.g. +=). This
patch checks for these in a few common places and prints a warning
that they are not currently supported. Eventually the simple cases
will be converted.
We can not convert SystemVerilog strings or dynamic arrays to valid vlog95.
This patch adds an error message that they are not supported. There are still
issues with converting some of the dynamic array constructs (the compiler
crashes), but the message is printed before the crash.
When built with MinGW, pow() may not always generate an exact integer
result when supplied with integer operands. Converting the result to an
integer before we use it seems to be enough to work round this issue.
This patch adds support for SystemVerilog packed arrays and adds sorry
messages for generate blocks as well as the new SV final and
fork/join_any/join_none statements.
The compiler doesn't currently check that the width of an indexed
part select is non-zero. If code contains this erroneous case, the
compiler can crash (with an assertion failure). This patch causes
the compiler to output a suitable error message and recover. It
also fixes a potential crash if an illegal expresson is encountered.
The parser does not distinguish between module and UDP instances, so
a UDP delay is handled by the rules used for parsing module parameter
overrides. Although these rules had been relaxed to accept the case of
a simple decimal value (e.g. #10), they did not allow a simple real
value (e.g. #0.1).
This patch implements the $countdrivers system function. It does not
yet support wires connected to islands (and outputs a suitable "sorry"
message when this is detected).
To implement the $countdrivers system function, we need to be able to
find all the driver values for a given wire. Currently, if a wire has
has more than four drivers, the compiler builds a resolver tree out
of 4-input nodes to resolve the driven values, and there is no way at
run time to work back from the output node to the original driver
values. This patch moves the implementation of the resolver tree into
a single vvp functor (using a mechanism similar to wide functors to
support more than 4 inputs), thus gathering all the driver values into
a single place.
Implement through the ivl core to the ivl_target.h API.
Also draft implementation of creating and storing arrays
in the vvp runtime and code generator.
When string[x] is an l-value, generate code to implement something
like the string.putc(x, ...) method.
Also handle when string[x] is the argument of a system task. In that
case resort to treating it as a calculated 8-bit vector, because that
is what it is.
This also advances support for string expressions in general.
Handle assignments to string variables in the code generator by
trying to calculate a string expression. This involves the new
string object thread details.
In vvp, create the .var/str variable for representing strings, and
handle strings in the $display system task.
Add to vvp threads the concept of a stack of strings. This is going to
be how complex objects are to me handled in the future: forth-like
operation stacks. Also add the first two instructions to minimally get
strings to work.
In the parser, handle the variable declaration and make it available
to the ivl_target.h code generator. The vvp code generator can use this
information to generate the code for new vvp support.
The parser had been changed to support null statements in sequential
and parallel blocks (a feature introduced in SystemVerilog), but was
not supported in elaboration, leading to a compiler crash. This patch
fixes this by discarding the null statements during parsing.
Currently, localparam declarations inside generate blocks are
elaborated after any nested generate constructs are elaborated.
This prevents the localparams being used by the nested constructs.
Reversing the elaboration order fixes this bug.
Added: basic vpiPort VPI Objects for vpiModulkes
vpiDirection, vpiPortIndex, vpiName, vpiSize attributes
Since ports do not exist as net-like entities (nets either side
module instance boundaries are in effect connect directly in
the language front-ends internal representation) the port information
is effectively just meta-data passed through t-dll interface and
output as a additional annotation of module scopes in vvp.
Added: vpiLocalParam attribute for vpiParameter VPI objects
Added: support build for 32-bit target on 64-bit host (--with-m32
option to configure.in and minor tweaks to Makefiles and systemc-vpi).
The fork/join list did not adequately support the tree of processes
that can happen in Verilog, so this patch reworks that support to
make it all more natural.
Making the scope type NESTED_MODULE was just plain wrong, because
it didn't really encapsulate the meaning of program blocks OR
nested modules. So instead create nested_module() and program_block()
flags and use those to test scope constraints.
An important advantage of program blocks is its ability to nest
within a module. This winds up also allowing modules to nest, which
is legal but presumably less used feature.
It is common for typedefs of complex types to use further typedefs.
Emit the type definitions depth first so that the types that are used
are defined first. This reduces the need for pre-declaration of types.
When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
Elaborate records and emit them as packed SV records. Also handle
record members so handle name prefixes.
While we are at it, handle some cases of array aggregate expressions.
When signals/variables are records, they are often referenced by
their members, using a prefix.name syntax. Parse that syntax and
generate "sorry" messages in elaboration.
A NetScope object currently has two lists of parameters, 'parameters'
and 'localparams'. However, user-declared localparams are stored in
the 'parameters' list, and 'localparams' is only used for adding
genvar values to the parameter list. There seems no good reason to
maintain separate lists, as the lists are merged before being passed
to the target DLL. This is most likely a hang-over from older code.
This patch extends the compiler to support all specparam declarations
allowed by the 1364-2005 standard. For compatibility with other
simulators, it allows specparam values to be used in any constant
expression, but outputs a warning message and disables run-time
annotation of a specparam if it is used in an expression that must
be evaluated at compile time.
SystemVerilog allows a variable to be used as a variable OR
as an unresolved wire. The detection of this case was checking
the references to the affected value, instead of the l-value
references.
(cherry picked from commit cceeaa30f27260cd444015cb39b04353cb858768)
The final step of expression elaboration is to reduce the width of
lossless/unsized constant expressions to the minimum needed to hold
the resulting constant value. This leads to unexpected results if
the user supplies a literal number with redundant digits that gets
passed to a system task that is sensitive to the width (e.g. $display).
This patch prevents width reduction occurring in this case.
When a conditional statement is unnamed, it doesn't create a scope
and we get into "direct" generate scheme elaboration. This direct
elaboration needs to handle case generate schemes.
The IEEE standard does not specify the behaviour of a tranif primitive
when its control input is an 'x' or 'z'. vvp currently treats these as
if the tran was turned off, but it would be better to propagate the
uncertainty to the tran bi-directional ports. For compatibility with
other simulators, we adopt the behaviour specified for MOS primitives.
This is a cleanup in preparation for better support of range lists.
(cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68)
Conflicts:
PTask.h
elab_scope.cc
elab_sig.cc
parse.y
pform.cc
pform.h
pform_types.h
Signed-off-by: Stephen Williams <steve@icarus.com>
The SystemVerilog unbased literals (e.g. '0, '1, etc.) are expected to be
used standalone and cannot take a size. This patch modifies the parsing
code to give a good error message when this is done.
The standard specifies that the size of a vecval should be calculated as
(size - 1)/32 + 1. When size is a PLI_INT32 this is needed to prevent an
overflow, but when the size is unsigned this can be simplified to
(size + 31)/32 since the size must fit into an integer, but we have an
extra significant bit in an unsigned so no overflow can happen.
This patch changes the code to use the correct version of the equation
depending on the context.
The previous patch does this in vvp/vpi_priv.cc
When vpi_put_value() is asked to delay the assignment any pointer data
needs to be duplicated so that the caller can clean up the locally
allocated memory without causing memory access problems.
Also update word calculation to match the next patch.
If a tranif gate has a delay, the vvp code generator needs to generate
a unique label for the island port used for the tranif enable, to
prevent a name collision if the undelayed signal is also connected
to the island.
Also add an assertion in vvp to catch bugs like this.
Class methods belong in a class scope, not the containing module.
So create a lexical scope that carries tasks and functions and
create a PClass to represent classes.
Tasks call arguments may be dropped in favor of default values.
Allow for that in the syntax. This requires a little handling
of the non-SystemVerilog case during elaboration.
Class names can be declared early, before definitions, so that the
name can be used as a type name. This thus allows class definitions
to be separate from the declaration. This creates some complexity in
the parser, since the lexor knows about the class names.
This adds the vector_type_t and real_type_t types to handle
vector and real types in tf_port items. This cleans up a lot
of the parsing for these items.
During parse/pform processing, convert increment statements to
the equivalent compressed assignment statement. This is less weird
for elaboration processing and better expresses what is going on.
The clang compiler does not like using struct to reference a class object.
This patch removes all the struct keywords for __vpiNamedEvent objects
since they are now a class and can be called without a struct/class
qualifier.
This patch also removes all the extra class qualifiers from the rest of
the source code.
This handles a few cases where the non-constant bit selects are
in the final index. This doesn't handle all the cases of packed
arrays, but it handles some common cases.
This gets me to the point where the parser stashes a defined type,
and the lexical analyzer uses the type names to differentiate
IDENTIFIER and TYPE_IDENTIFIER.
Parse typedefs with structs and enums, but give a sorry message,
because they are not yet supported. Rearrange some of the parse
rules for variables in order to increase comonality with the
typedef rules.
When looking for a value change on a part select of an array word,
the callback handle has to save the current value and test it with
the new value to see if there is an actual change. If not, then
suppress the callback.
The clang compiler does not like mixing class and struct references. This
patch updates all the struct __vpiHandle, etc. to use class since that is
how they are now defined.
All the methods that this structure supported are now pulled
into the __vpiHandle class as virtual methods. This includes
the vpi_free_object_ method, which required some extra trickery.
Instead of C-like data structures where the __vpiHandle base is a
leading member, make the __vpiHandle a derived class. Give the base
class a virtual destructor so that dynamic_cast works reliably, and
now pretty much all of the junk for testing if an object really is
of the derived class goes away. Also, problems with casting up to
a vpiHandle become trivial non-issues.
Full vector assigns are able to short circuit the propagation of
the value if it finds that there are no value changes. This patch
supports that behavior in writes to parts as well. Put this change
to use in logic devices as well.
Not all the lex/yacc (flex/bison) targets were using a consistent syntax.
This patch fixes that and explicitly serializes the *.c/*.cc and *.h build.
Not doing this was causing problem when using make -j. The issue appears to
be that if two targets are specified for a rule (e.g. file.cc file.h: file.y)
make does not realize they are both built by the same call so the rule is
executed twice. Once for the .cc target and once for the .h target. This is
not a problem for a serial build. To work around this only use the .c/.cc
file in the main target and then make the .h file depend on the .c/.cc file
as a sub-target.
Rework the nexus emitting code to correctly translate most I/O ports.
Fix a few other expression issues uncovered when port translation was
done correctly. Ignore and warn that the SV ++/-- operators and enum
types are not translatable. More updates of the nexus debug code.
When a black-box item requests a specific footprint, we need to
read a file (<footprint>.fp) that contains the actual details
about that footprint. Support parse of that file and use the
loaded Element to generate the footprint for the item.
On some systems having both %.o: %.c and %.o: %.cc rules confused the
make system. This is directory only has C++ code so remove the %o: %.c
rule. Also the C++ compiler should be used to link C++ object code.
On Ubunto 10.10 (32 bit) tgt-pcb would not build because there were
include file issues. This patch fixes those and uses the C++ include
version where appropriate.
The main .pcb file contains elements, and basic PCB status.
Write out a .pcb file with stub Elements for each of the devices
in the design.
Rearrange the way the files are reported to the code generator
so that we can sensibly express where the output files are.
This is a pretty trivial fix for the code generation of compressed
assign to a memory word. We generated incorect code for the stash
of the calculated word index, causing the assign of the result to
not work properly.
This same change was done in the vpi directory. This patch fixes the
issues in the libveriuser directory. This fixed a fail in the vpi
timescale test under MinGW.
A declaration of the form "parameter signed a = 1.0" causes a
compiler crash. The standard is somewhat contradictory on what
type "a" should have, but testing with other compilers shows a
majority in favour of it being a real value.
The standard allows a parameter (or localparam) declaration of the
form "parameter signed my_param = ...". The parser currently rejects
this. A small adjustment is also required in the parameter evaluation
code to correctly apply the type.
Now we have a code generator that can handle compressed assignments
as they have been re-imagined in elaboration. There are some cases
that are not yet supported, we'll patch them up in due course.
Most people doing real modeling don't want to bring in the whole
Verilog-AMS infrastructure to use wreal nets. This patch adds the
wreal keyword to the xtypes generation so that wreal is available
by default.
This patch adds wreal support when in Verilog-AMS mode. It doesn't add
everything that is shown in the Verilog-A standard.
It adds the following:
Declaring a wreal net.
Declaring a wreal net with an initialization.
Declaring a wreal input/output using ANSI syntax.
Declaring a wreal input/output using the old style.
Declaring wreal inout ports are also allowed and parsed, but the
compiler does not know how to handle this. There are other deviations
from what is shown in the Verilog-A standard, but this should get most
of the syntax people actually use.
An @* with no sensitivities should be treated as something that will
never trigger vs something that will run continuously. This patch makes
this change and adds a warning when an @* has no sensitivities since
this is almost certainly a coding bug.
It is legal for a named block to contain variable definitions and
no statements. This patch fixes this for both style of blocks. It
also organizes the block parsing code to be a bit more clear, adds
an error case for fork/join and changes on check for size() > 0 for
the more efficient ! empty().
To avoid a variables not initialized in the construct this patch modifies
the PSpecPath class to take the polarity and full_flag as arguments to
the constructor.
The --always flag to git describe is harmless in the normal case,
and helpful in some special cases. Also add the --dirty flag to
get extra interesting details.
If a wired and/or net has more than four connections all the other
resolution branches must also be wired and/or. All other nets can
just be tri since tri0/tri1 only needs the final resolution to be
an active pull up/down.
Since synthesis is not currently supported we do not support/generate
sync/async set or clear control inputs. This is further complicated by
the fact that the VVP DFF primitive is not fully implemented.
This patch fixes a compile problem in Cygwin where there are two
definitions for abs() that do not match so the C++ code doesn't know
which one to call. To avoid the whole mess replace the call to abs()
with the appropriate ?: construct.
In a specify block a full connection is defined to only support a single
source and destination path. This patch adds an error message when this
is found, except we skip the error if all the paths are a single bit
wide. This exemption was added to match the functionality found in
NC-Verilog and presumably Verilog-XL.
A message was also added in place of an assert if the source signals was
not found in the current scope.
Both UDPs and system functions use the wide input functor. This patch
modified the code generator to create a local net declaration for the
output net if we have either a delay or modpath connecting the output
to the true output. This is needed so that the wide input can be
cleaned up correctly.
Local real nets were also added to the local net pool when testing with
valgrind. This allows them to be cleaned up at the end.
For a delay we do not know exactly what type we will be propagating
until the initialization event has happened. Because of this we
allocate both a vec4 and a vec8 value. Once the initialization event
has happened we can free the unneeded element(s).
This patch uses the full_flag to verify that the input and output have the
same width for a parallel connection. Icarus always uses a full connection
so this is just a portability issue with other simulators.
The pform dump code was also modified to correctly display the polarity
and full/parallel connection type.
In MinGW, when parameters are passed to vhdlpp by ivlpp, single quotes
are treated as ordinary characters. Use double quotes instead, as is
done in the driver.
Also, MinGW does not have a standard mkdir() function, so we need to
convert calls to mkdir() into calls to _mkdir().
When scaling a time value we would often use the power operator to
create constants 10**-N that were then multiplied with the original
value. The problem with this is that there is some errors in the
representation of the fractional number. It is better to create a
integer value 10**N and then divide the original value by this
exact constant. You still have the calculation error, but the scale
value is now an exactly real value.
Add support for %m, suppression '*' and a maximum field width along with
a number of other fixes/enhancements. There is still no support for
%u, %v or %z.
The fix to get a C99 compliant strtod() in MinGW mistakenly set the
LDFLAGS value rather than appending to it. This meant that a LDFLAGS
supplied by the user on the configure command line would be ignored.
MinGW has reverted to using the Microsoft msvcrt0 implementation
of the strtod() function. This implementation doesn't accept "INF"
"NaN". MinGW does provide a C99 compliant implementation of this
function called __strtod(). We need to force the linker to replace
all references to strtod() with references to __strtod().
This patch adds error messages that forcing a word to/from a variable
array is not currently supported. This is because variable arrays no
longer are fully populated and don't have an access functor for each
word. Forcing a word from/to a net array does work as expected since
each word in a net array is created.
Technically forcing a variable array word is not supported in 1364-2005.
Reading from an array word, which is supported, will be fixed in
development once the expression rework is finished.
The error message printed when forcing a bit/part select l-value was
also improved.
Promote the unsigned values to long to get a good comparison and on a
machine where an unsigned is the same size as a long (32 bit) assert
that the unsigned values are constrained to fit into a long. It's unlikely
the values needed to create invalid results would ever happen, but this
patch makes sure it doesn't go undetected.
Some of the last changes I added to the enumeration next()/prev() code
introduced a memory leak under some situations. This patch fixes the
leak by freeing the iterator before the new one is created.
The name is not currently used, but when it is it makes sense for it to
be in the base class. Also the name cannot be deleted after compiling
since it may be used later.
The VPI object data model diagrams show a one to many relationship
between the "mod path" and "path term" objects. This means that the
correct way to obtain handles to "path term" objects is to use the
vpi_iterate and vpi_scan functions.
Support for the old method of obtaining handles to "path term" objects
using the vpi_handle function is retained for backwards compatibility.
Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.
Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
Add an implementation for the enumeration name() method. This currently
only works if the context defines the return width (e.g. the result is
assigned to a variable). It does not work in a self-determined context
(e.g. as an argument to a system function or in a comparison). This is
a limitation in the compiler/code generator/run time not the method
implementation provided here. We may need full string support to make
this work 100%.
The standard defines how to calculate the name for an access function
or iterator if one is not given. It is supposed to be vpi followed by
the words in the name with each word capitalized. For the one to many
(iterator) interface from the enumeration typespec to the individual
constants this is vpiEnumConst not vpiMember.
Rework the actual next() and prev() methods to correctly process the
numeric count argument. Also rework the compiletf routine to give better
error messages and combine the call routine for the two methods.
Add a compiletf routine that checks the arguments and then report that
the name() method is not currently implemented.
We don't currently have the information needed to correctly provide the
base typespec, but in the next() and prev() methods I need to know if
the enumeration is two or four state. This patch sets the base typespec
for four state enumerations to vpiReg and to vpiBitVar for two state
enumerations. This provide enough information to get next() and prev()
working correctly.
This patch adds vpiEnumTypespec to the list so that vpi_get_str(vpiType, ...)
returns an appropriate string when an enum type is passed.
It also adds the initial hook to allow iteration (global) over the UDP
definitions. This along with table traversal will be needed to free the
memory allocated when the UDP definition is created. Ultimately this
will all the UDP test to be valgrind clean.
The PLI tf_getlongsimtime() function is a non-standard function provided
for compatibility with some commercial simulators. To match the behaviour
of those simulators, it should return the raw simulation time, not a
scaled time.
The vpiDecStrVal case for the get_numeric() function needs to use the
existing string width as the minimum result size. -1 can be represented as
a signed value with a width of 1. This gives a display width of -1 which
is too small for the -1 string value. This was creating valgrind issues.
In general the string value should be the minimum so this is a safe change.
If a constant is padded the original constant will be freed and replaced
with a new one. This results in the ce pointer pointing to freed memory.
In reality the second check only needs to be done if the first one is
false so avoid the whole issue by only performing the second check if
the first on is false.
If a wait statement has a constant argument then the mode must be defined
before test_width() is called since the current mode is used in the
PENumber test_width routine.
Add code to allow an enumeration method to be called as a function.
This is only the compiler support. The runtime support is still missing
so only an empty argument call will succeed (e.g. next(), etc.). For now
the rest get a warning message.
Update the line number for a couple cppcheck suppressions and add one for
the pool variable in the vvp directory.
Also move a check for null to the correct place.
This patch makes the code consistently use struct/class in the C++ files,
it removes a couple shadow warnings and where a class pointer is passed to
the C routines, it defines the pointer as a class for C++ and as struct for
C and it removes a namespace std duplication.
This patch updates the $scanf and $printtimescale routines to work with
two-state variables. It also updates the general is_numeric check to
recognize two-state variables as numeric.
Modify the $random code to allow the seed to be either an int, long or
bit that is 32 bits or longer. The 32 bit check is new and also applies
to reg/logic variables.
This patch fixes a few more bugs in the enumeration code.
It add support for saving the file and line information to make
diagnostic messages better.
It updates some of the compiler warning messages to use the file
and line information.
It passes if the enumeration type is signed all the way to the
code generators.
It fixes the parser to correctly have the range after the signed
designation for the vector types.
It adds a warning that vvp does not currently support a negative
two state enumeration value.
We need to print a message and fail if the two \\ characters are not found
in the executable path.
Also update the generation warning to include -g2005-sv.
This is caused by a bug in some simple pattern matching the VHDL target does to try
and produce more idiomatic code in common cases (e.g. FFs with asynchronous resets in
this case). This patch just restricts the kinds of if-statements we use this
optimisation for.
The patch adds necessary error checking to verify that the operands of
increment decrement operator is not number.
Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
Type cast expressions and some function calls are syntactically
identical to array element select, so we can only tell the difference
by looking up the name of the identifier being selected. If it is a
type name, then create an ExpCast instead of an ExpName object.
Also, parse and emit vector part selects.
Add a new IVL_PR_FINAL process type.
Add a flag to NetScope in_final_ which is set when elaborating the
statement of a final procedure.
Add checks during statement elaboration for invalid statements in a
final procedure, similar to checks for statements in functions.
Do a final check to make sure no final blocks have delays.
In the vvp runtime, use "$final" as the flag for the thread created by
the final procedure. During compilation, instead of adding such a
thread to the sched_list, add it to a new schedule_final_list that
mirrors the schedule_init_list, but is run at the end of simulation.
This patch adds support for increment/decrement operators as an
expression. The operations on real and vector slices have been
disabled for now.
These operators can be used as in independent statements. However, the
corresponding support is not added in parser.
Changes since V2:
- Additional error checking in elaboration to deny operation on vector
slices and real (suggested by Martin)
Changes since V1:
- Use 'i' and 'I' for increment (suggested by Cary)
- Evaluate sub-expression once (suggested by Cary and Stev)
- Add necessary checks during elaboration to ensure that the
expression is valid (suggested Stev)
- Proper width handling with vectors (suggested by Martin)
Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
Icarus uses 'i' in the net expressions for a cast to integer. Replacing
it with 'v' would free the character 'i' that can be used for increment
operators. This changes cast operators to become 'v', '2', and 'r'.
Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
Suggested-by: Cary R. <cygcary@yahoo.com>
The vvp target code generator may not elide a BUFZ if the output of
the BUFZ is connected to a net that is the subject of a procedural
force statement.
Named libraries are similar to the work library, but they are not
written to implicitly, or imported implicitly. They are only brought
in by a "library" clause, the the packages within the library are
brought in by a "use" clause.
Technically the sized function is not currently needed by Icarus since
the SFT file handles this type of information, but lets define this so
that things work correctly if we ever switch to using the standard VPI
interface. Also mark this as a system defined function.
Presumably, the user will want the ability to explicitly set the
working library location, so create a +vhdl-work+ plusarg setting
for exactly that purpose.
Port map aspects were held in std::maps. Because
of that, in case of multiple assignments to the same
port, some assignments were lost and in effect vhdlpp
produced correct verilog code from a buggy VHDL.
Std::map was replaced by std::multimap. Thanks to it
we can gather this multiple assignments and detect them
in the elaboration phase.
This patch introduces in ScopeBase separate containers
for declarations coming from the current scope and from
the previous scopes.
Until now, in one scope, all objects were kept in an stl map.
When a scope was created inside other scopes, a shallow
copy of the map was made. This solution was nice for
name shadowing (in new scopes, when a name was
encountered, the old objects were overridden by a new
one), but didn't allow for distinguishing where the objects
were allocated. As a result, it is impossible to know who
the owner is and who should delete them.
In this commit ScopeBase gets two containers: for old
and new objects. If a ScopeBase is made from another
ScopeBase object, all objects from the copied object
go to an old_XXX container, where XXX depends on the
type of the copied objects. When a ScopeBase object
is deleted, the objects from new_XXX are deleted and
the ones from old_XXX are not touched.
This patch adds some complexity to the internals
of ScopeBase, but leaves its interface unchanged.
This is rather a cosmetic change. The patch changes
the container used for stack of scopes from std::list
to std::stack. It suits this particular application
a bit better.
Thanks to valgrind analysis it turned out that
there were objects in the parser that were not being
deleted in a proper way. This patch fixes them all.
Instead of using automatic variables for global
types, I allocate them dynamically. Thanks to it,
all type objects can be treated in the same way,
as all of them are pointers allocated with `new'.
Now we will be able to remove all scopes in the same
manner, no matter if it is a global or local scope,
by deleting all carried pointers.
When writing arrays to the work library, handle the special
case that it is an array of std_logic and write a std_logic_vector
declaration instead. This makes for a more compact description.
When a "use" clause tries to pull a package from the work library,
put together a file name and try to find that package in the
work library directory. If found, parse the package file and
try again to find the package.
Bison and Flex generate different interfaces for reentrant
parsers, so handle that different API. We need this change
because library support is going to reuse the parser to
read in library packages.
This patch adds code to check for a negative or undefined value used in
an enumeration sequence name, it verifies that the count in an enumeration
sequence name is not zero and allows more decimal constant values in the
enumeration sequence name..
isprint() is defined to take an int and if it is defined as a macro then
you can get a warning that a char is being used as an array index. This
patch fixes this warning in tgt-vlog95/msic.c
SystemVerilog extended the assignments operator support to C-like
assignment operators and special bitwise assignment operators.
For example:
a += 1;
a -= 1;
The list of these operators can be found in SV LRM (1800-2009)
section 11.4.1.
NOTE: I fixed a few parts of this. In particular, the PEBShift
class is used for shift operators.
Acked-and-Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
This function is for the time being used in the
component instatiation. It is checked, whether
an expression is a correct r-value.
To be a correct r-value, it must be either
port name or signal name.
pow(int, int) is ambiguous since it could use the double version from
the math library or the verinum version. This patch makes it obvious that
we want to use the double version.
Build up a work library by writing a VHDL representation of the
package header into a source file. This representation needs to
be accurate enough that later invocations of vhdlpp can read them
with the VHDL parser.
SystemVerilog has support for time literals. The time literal for
example #10ns, adds a delay of 10ns no matter the time unit currently
in effect. For more details please refer to
http://iverilog.wikia.com/wiki/Projects#SystemVerilog_Style_Time_Literals
Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
A bit/logic output type in a module initially is defaulted to as a
variable. Depending on how they are used in the module, the type
changes accordingly.
For example
module test(output logic l);
assign l = '0;
endmodule
The variable 'l' would be promoted to a Net data type, when the
'assign' statement is encountered.
Acked-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
The module declaration should allow initialization of the bit and
logic data types.
For example:
$ cat clkgen.sv
module clkgen(output logic clk = 0, output bit p = 1);
initial begin
#200;
$display("p = %b", p);
$finish;
end
initial forever #10 clk = ~clk;
endmodule
$ iverilog -g 2009 clkgen.sv
$ ./a.out
p = 1
Suggested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
SystemVerilog allows passing the 'bit' and 'logic' arguments to a
function. The patch adds support for parsing these function
definitions. The 'bit' data type is treated as boolean, whereas 'logic'
data type remains as logic.
Acked-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
This patch removes the space between -L and the directory in the vpi
Makefile. It also fixes the line to use the correct variable name
for the LDFLAGS.
The patch allows parsing of function definitions which do not have
explicit data type or range. The default return data type is assumed
to be reg unsigned and the default range is 0.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows returning variables of 'reg' type. The icarus verilog
implicitly assumes the default returned type of the function as
'reg unsigned'. The patch allows to explicitly specify the 'reg' return
type.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows user to define variables of primitive types. The patch
adds support for defining variables of type 'logic'. The data type
'logic' is the only primitive data type which supports defining ranges.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows user to define variables of primitive types. The patch
adds support for defining variables of type 'bit'. The data type 'bit'
is the only primitive data type which supports defining ranges.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Remove an unused variable (desired_vector_width) in elaborate.cc.
Reduce the scope of spin to make it obvious it is only used locally
in elaborate.cc. Initialize sel_type_ in the NetAssign_ constructor
(net_assign.cc). The code doesn't currently require this since
sel_type_ is only used when the base is not zero and it is always
defined when base is not zero, but giving this a default value in
the constructor hedges against accidentally using an undefined
value if someone checks the select type when the base is zero.
The $ivlh_attribute_event system function helps the Verilog runtime
support <name>'event expressions in VHDL. The vhdlpp generates a
call to $ivlh_attribute_event, which in turn uses callbacks to handle
the support.
This is also the start of the vhdl_sys vpi module. This module should
by included whenever VHDL code is parsed.
The compiler was handling bi-directional pass switches using the default
case for primitive gates, where the first port is treated as an output
and the remaining ports are treated as inputs. This patch adds a special
case for pass switches, so that the first two ports are treated as
bi-directional.
When a signal (or port) is assigned by a sequential assignment,
the signal or port becomes a reg, instead of a wire(net). Detect
this distinction during elaboration and generate the correct
signal/port declaration.
The -gno-specify flag should only control the delay and timing checks.
It should not also remove the specparams since they can be used outside
of a specify block.
The IEEE standard states that the port expressions used for arrays
of primitive gates must be the exact width required, but is silent
about the requirements for single instances. The consensus among
other simulators is that for input ports of single instances, the
expression is silently truncated to a single bit.
This patch also fixes a compiler crash if an error is found when
elaborating a primitive gate port expression.
Keep the entity/component/module port declarations in the module port
list of the generated code. This clarifies the generated code and
fixes a couple bugs for more complicated types.
R-value expressions are more general then L-value expressions, in that
the expression type may be a bit more complex. If the R-value expression
is part of an assignment, then elaborate with the constrained type from
the L-value. In other cases, where the expression type is not as obvious,
use expression type probes to figure out the type of the expression and
elaborate using that calculated type.
This patch adds code to properly calculate the type and width of a
specparam when it is used in an expression.
This patch also fixes a compiler crash when an unknown identifier is
used in a delay expression.
Icarus is not actually fast enough to run into this issue in a
reasonable amount of time. I discovered this by thinking about
the algorithm and verified the fix with custom code.
If a relative path name is passed to the Windows LoadModule function,
it is applied in turn to each path in the DLL search path. For the
ivl_dlopen function, we actually want to mimic the Unix behaviour,
where a relative path is relative to the current working directory.
On systems where the KB2264107 security fix has been applied, the
CWD is excluded from the DLL search path, so we no longer get the
required behaviour. This patch reworks the ivl_dlopen function to
give the correct behaviour under Windows.
This patch also adds a flush of the stderr stream after reporting
VPI call errors. This fixes a race between the stdout and stderr
streams when running the regression tests in a MinGW shell.
VHDL doesn't have a direct way to express "always @(posedge...)"
statements, but we do want to detect common paradigms that naturally
translate. This makes for a better translation.
Entity output ports may be used as l-values in a process within
the bound architecture. Detect that case during elaboration and
adjust the signal declaration so that it works in the Verilog pass.
Infrastructure for debug and emit of sequential statements in processes.
This does not properly handle the actual semantics of the behavioral
code, but it provides an infrastructure where we can handle all the
tricky elaboration to come.
Get to the point where our sample program parses completely, and
the sequential statements generate SequentialStmt objects and a
process object in the architecture.
Also add a few missing expression types.
The code should be able to correctly parse any command string and
assign the appropriate values from the file to a structure that will
be used to add the information to the table structure.
snprintf() copies at most N characters, but the string may not be
terminated correctly. This patch uses sizeof() so that the snprintf()
call matches the size of the buffer and adds code to insert a NULL as
the last character of the string.
Added an explicit option prefix="yy" to files that were generated
without an explicit -P.
This makes the lex-generated symbol names self contained without any
help from from build system.
The const fixes for lxt_write.c were never pushed to GTKWave so
they were lost in a later sync with GTKWave. These changes have
now been pushed to GTKWave.
If there are attributes attached to a module port declaration them
pform_bind_attribute() which is called from pform_module_define_port()
will delete the attribute list. They do not need to be deleted locally.
To get the correct definition for _FILE_OFFSET_SIZE we must include
the header that loads this before calling the other system headers.
This patch also fixes a minor spacing issues.
After some more thought I believe it is better for $q_full to return
'bx instead of 2 when $q_full is given an invalid id. This will make
the typical full/not full checks both return false. We still return
an error code in the status variable.
This patch adds preliminary support for implementing the $table_model()
function for Verilog-A. It is not currently functional, but the VPI
interface routines and data file parsing are mostly complete. The big
things left are building the data structures and adding the interpolation
and extrapolation routines.
We also need to fix vvp to identify constant strings/parameters in a
structural context.
This patch adds the ability to print a constant string in a
structural context. It also fixes the argument order for
structural function calls and makes a few improvements in
nexus identification.
This patch adds code to the compiler so that a constant string
in a structural context can maintain the string property. This
is needed but not currently implemented in vvp (it's still
converted to a number). A pending patch for the vlog95 target
does use this new information.
This patch adds support for calculating the average queue wait
time. This is accomplished by keeping two 64 bit values that
represent the high and low total wait time for all previous
queue elements. The current wait time for any elements still
in the queue are added to this total. The wait time total is
then divided by the total number of items added to the queue.
Significant rework of scope management to unify the handling of
types in the ieee library and types/constants/components in packages.
This involved adjusting the parser rules to manage a stack of scopes
and rewriting the IEEE library support to not use global maps for
the loaded types.
If the right hand operand of a shift is a signed vector value, it
is coerced to an unsigned value. This needs to be allowed for when
estimating the width expansion caused by a shift in a lossless
expression.
The power operator defines 2**-1 and -2**-1 to be zero. This patch fixes
both the procedural and continuous assignments to work correctly. It also
fixes a problem in the compiler power code so that the one constant value
always has at least two bits.
This patch adds support for calculating the queue mean inter-arrival
time. This is just the latest add time minus the first add time
divided by the number of intervals (the number of adds minus one).
This patch adds full support for the stochastic tasks/functions except
the mean inter-arrival and average wait statistics are not currently
available. These will be added in a later patch. This implementation
goes a bit beyond the standard and supports the following:
1. The job and inform arguments support 32 bit four state values.
2. The id for all routines, the job and inform arguments for $q_add(),
the statistic code for $q_exam() along with the queue type and
maximum length arguments for $q_initialize() can be less than or
equal to 32 bits. The argument will be sign extended if needed to
fill the internal 32 bit value.
3. The job and inform arguments to $q_remove() and the status argument
for all the routines must be 32 bits, but do not have to be an
integer variable (e.g. a 32 bit register or part select is OK).
4. An undefined bit in the id argument for any of the routines will
return a status of 2 (undefined queue id). Undefined bits are not
automatically converted to zero.
5. Undefined bits in the $q_initialize() queue type and maximum
length arguments or the $q_exam() statistic code argument are also
flagged as an error (are not converted to zero).
6. The $q_full() function returns 2 on error, the other routines that
return a value $q_remove() job/inform arguments and the $q_exam()
statistic value argument will usually return x on error.
7. An invalid statistic code will set the $q_exam() status to 8.
8. The $q_exam() statistic value argument can be 32 bits or larger.
This allows returning large statistical time values.
9. All time values are internally saved in simulation time units.
They will be converted to the calling module's time unit (with
rounding) before they are returned.
10. If a $q_exam() statistical value is too large to fit into the
variable the maximum positive value will be returned and the
status code will be set to 9 (value is too large).
11. If a statistical value is currently undefined $q_exam() will
return 10 (no statistical information) (e.g. using code 5 on an
empty queue).
This patch allows the compiler to perform early elaboration
of functions if they are encountered in expressions that are
elaborated before the function would normally be elaborated.
This makes the function available for constant evaluation.
Suitable error messages are generated if a function that is
used in a constant expression is not a valid constant function.
For now Icarus doesn't support a UDP instantiation with a range.
Instead of generating a warning about the port count being wrong
this patch adds code to calculate the range and print a message
if a range greater than one is found.
This creates the Package class to represent packages, and the
Scope class to represent scopes in general. The library functions
are worked up to support scanning scopes for declarations that are
imported by "use" clauses.
Make sure in a conponent instantiation that the instantiated
component is really declared, and that the ports of the binding
really do match the ports of the declared component. This requires
that we create and save component declarations, and that components
have methods for mapping the ports.
Certain types of expressions involving only constants would produce
ambiguous VHDL output. Fixed by qualifying one of the arguments. E.g.
('0' or '1') = '1'
Which is ambiguous becomes
(std_logic'('0') or '1') = '1'
This fixes the xnor_test test.
Reduce XNOR was implemented incorrectly because of trivial typo
Fixes regression of simple_gen test.
Also extended ivl_lpm_size API call to support all LPM types. This
simplifies some of the VHDL LPM generation code a little.
When a user or system function is called on the RHS of a continuous
assignment, and one of the function arguments is an undeclared
identifier, the compiler reports the error correctly but then
crashes. This patch fixes the crash.
This patch changes the method used to signal that a constant expression
is being elaborated from flags stored in global variables to flags
passed down the call chain. It also generates more informative error
messages when variable references are found in a constant expression.
There has been added additional default attribute to
all 'dump' function calls which is in all cases equal
to 0. Now one can specify how much this debug dumping should
be intended. This should allow people to dump smoothly whole
designs (as it was now) as far as separate units.
This is now the parent who specifies the base indentation
for all components (children). For example, architecture
"decides" how much their signals should be indented.
During elaboration, it is sometimes efficient to collapse a
collections of PV drivers to a net to a single concatenation.
This removes a bunch of resolutions and other nodes, and also
is the only way that 2-value logic should work.
During elaboration, it is sometimes efficient to collapse a
collections of PV drivers to a net to a single concatenation.
This removes a bunch of resolutions and other nodes, and also
is the only way that 2-value logic should work.
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
Up till now only "global" use clauses were parsed
and as a result libraries were loaded.
Since use clauses can appear not only in global context,
parsing of non-global clauses has been introduced and
selected names are now handled (like name1.name2.name3).
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.
In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).
I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
The bison grammar has been extended in order
to parse configuration statements. Parsing
remains very primitive but principal constructs
can be now recognized.
IEEE 1800-2005/9 says "each fixed-size dimension shall be represented by
an address range, such as [1:1024], or a single positive number to
specify the size of a fixed-size unpacked array, as in C. In other
words, [size] becomes the same as [0:size-1]."
This patch implements that translation in the parser. It issues a
warning when doing so when the generation flag is less than 2005-sv.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.
In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).
I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
This patch adds code to make sure a double (Verilog real) constant
is printed correctly. It also adds code to trim any leading escaped
NULLs from an expression string.
In VHDL it is allowed to have multiple architectures
per one entity. The proper architecture should be then
chosen in a configuration block. Now, if many architectures
will be found, then there will be a warning message printed.
FIXME notes are added in order not to forget about changes to
be done
This patch uses the new function (ivl_logic_is_cassign) to determine
if a logical was really the base of a continuous assignment. This
allows creating code that more closely matches the original.
This patch adds code that allows the targets to determine if a logical
gate came from a continuous assignment. This helps some of the targets
generate code that more closely matches the input.
It also reworks/simplifies the synthesis of && and || since the
compiler has already converted the two operands to single bit form
and fixes a mismatched delete from a previous patch.
This patch adds support for correctly handling most unconnected ports.
Most important is top level ports that are the root of the conversion.
This patch also adds support for emitting more signed constructs when
they are requested. $signed() and $unsigned() are still not supported
or recognized as an error when not emitting signed constructs.
This patch changes the module elaboration slightly to allow passing
the appropriate information for unconnected and top level ports. This
allows the vlog95 generator to get the basic structure correct.
These go into the architecture/block of their scope and will be
used by component instantiations to make sure the bindings are
correct and complete.
Also handle signal declarations. The elaborator will use these
to generate module local variables that are used by the architecture.
Also include support for "sorry" messages so that we have a place
to hang unsupported but properly parsed constructs.
In the process of doing this, I also encountered and add parser support
for indexed names. And matching "sorry" messages.
This patch adds a flag -pallowsigned=1 to the vlog95 converter that
tells it to allow signed signals. There is currently no code to check
for and warn/emit the $signed() and $unsigned() system functions. I
need to determine if >>> emitting should also be controlled by the
allow signed flag.
This patch adds support for emitting escaped identifiers and adds
code to correctly emit most module port expressions/definitions.
There are some minor code optimizations/cleanup included as well.
There was a single message when the expression width was larger
than the port width. This patch makes it a bit more clear by
saying that the expression was pruned.
Currently the compiler coerces input ports to inout ports whenever
there is an internal driver connected to the internal port net.
This generates an error if the port is externally connected to
something other than a structural net. This patch modifies the
compiler to ensure port coercion only occurs in valid cases.
This patch ensures that the result of a shift is an undefined value
if the right operand is an undefined value. It also improves the
code generated for right shifts where the right operand is constant
and optimises away shifts where the right operand is a constant 0.
It also fixes a few places where the expression type (signed/unsigned)
was not being set correctly.
The logic_lpm.c file uses the nexus private data pointer as an
unsigned counter. This patch makes the value unsigned long to
avoid a compilation warning on 64 bit systems.
This patch adds support for emitting fixed CA selects (zero based
variable bit and array selects also work), emitting a for statement
as a single statement and fixes for numerous little bugs. It also
adds the start of emitting module port information.
This patch adds some preliminary module port information to the ivl
interface. This may change as I investigate exactly what is needed.
It also fixes a few minor bugs (a missed local variable and spacing)
This patch adds a trace command to the interactive prompt that can be
used to control statement tracing when the code is instrumented (has
%file_line opcodes).
A valarray of an enum does not initialize to 0 so explicitly specify the
value to fill the array with. This was causing the compiler to incorrectly
report that fixed width elements in a concatenation had no size.
The following was done to remove compiler warning when using the native
compiler on OpenSolaris.
Remove the anonymous unions in tgt-vlog95/stmt.c and tgt-vvp/vvp_process.c.
Use UINT_MAX for the maximum unsigned unsigned instead of -1 in
tgt-vvp/draw_net_input.c.
Even though lex defines yywrap() to have no arguments when %option
noyywrp is used it generates a define that takes an argument that is not
used. The compiler warned about this so remove the option and add a
dummy yywrap function.
This patch adds a check on the expression type before adjusting an
unsized expression width up to integer_width. This adjustment should
only be performed for vectorable expressions.
The patch also fixes a few compiler warnings that only show up on
32-bit builds.
This patch adds support for tracing procedural statement execution in vvp.
This is accomplished by adding a new opcode that is inserted before the
code that represents a procedural statement. These opcodes also trigger
a message whenever time advances. By default these opcodes are not added.
To add them, pass the -pfileline=1 flag to the compiler. In the future we
may add support for turning the debug output on and off once the opcodes
have been added with a system task or from the interactive prompt.
The 1364-1995 version of Verilog does not support non zero based
parameters. This patch removes the comment requesting the parameter
MSB/LSB information to denormalize the expression and replaces it
with one stating that we need to keep the compiler normalization.
This patch removes the code that was deleting the signals in an L-value
concat if the concatenation failed to elaborate. This is incorrect since
the signal could be used in another context that is processed later. The
error message when an output/inout port fails to elaborate was also
improved to give the expression that is connected to the port.
This patch adds the rest of the functionality needed to correctly
emit both L-value and R-value procedural variable indexed part
selects as a concatenation of variable bit selects.
This patch modifies the compiler and the ivl interface to pass the
type of indexed part select that is being represented (up/down) in
a procedural L-value or R-value. This is needed by any back end that
wants to correctly denormalize the (zero based) base expression.
This patch adds support to the compiler/ivl interface for getting the
original UDP definition port names. ivl_udp_port() was added to get
this information.
This patch adds partial support of procedural variable indexed part
selects (both R and L-value). The restriction is that this currently
only works on a zero based little endian vector. I need to know if
the select is an up or down select to correctly denormalize the base
expression for the general case.
This patch adds copyright information for the Icarus generated UDPs
(lesser GPL version 2.1). It also prints a note to let the user know
that this copyrighted code is being included in the output file. They
can then remove the primitives if needed. These are likely only
needed when the output is from synthesis. At the moment we only have
a positive edge D-FF. In the future a negative edge FF and D latches
will also be needed.
Add a preliminary gate name and range (zero based) for logic primitives.
Also assert that a logic gate in a continuous assignment has the correct
number of inputs/outputs.
This patch adds code to emit variable real procedural delays by
removing the scaling that is added by the compiler. It also
recognizes that all variable continuous assignment delays are
scaled at run time.
This patch reworks the delay emitting code to handle delay expressions
better. It also encloses the emitted unary operators in parenthesis to
make sequenced unary operators work properly.
It was incorrect to extend emit_expr_signal() to handle a local signal
(a continuous assignment). The only way this should ever happen is
when evaluating a variable delay expression. It is better to do this
checking in the delayx evaluation where we know if we are processing
a delay for a statement or a continuous assignment. This keeps the
emit_expr_signal() routine cleaner and we only allow a CA delay for
a continuous assignment.
This patch fixes the following bugs in the vlog95 converter:
When emitting a signal as an expression, if the signal is local then
emit the expression that is driving the local signal.
The casts need to emit the expression.
When emitting pull devices they have different default strength rules
(pull is the default).
For compatibility pull devices should only have a single output net.
Extend the code that searches for the <var> = <delay> <value> pattern
to also check for an <event>. The previous event code only looks for
the repeat event pattern.
In principle, some of these should be handled by overloaded operator
functions, but these are built in types with natural translations so
do the obvious things.
Implement the parser infrastructure for handling library use clauses,
and use that to handle specific packages of the ieee library. Make
the numeric types come from the numeric_* packages instead of being
built in.
There are internal types that are unbounded arrays. Allow subtype
syntax that creates bounded versions of these arrays, and elaborate
them as vectors at port boundaries. This makes some interesting types
work out.
Also start replacing vhdlint and vhdlreal with int64_t and double,
which are reasonable values for universal_integer and universal_real
from the VHDL standard. I need these cleaned up because the ints in
particular are used for the literal expressions in array index constraints.
Rather then just relying on comparing type names all throughout
elaboration, create type description data structures and use them
during elaboration to handle proper types.
So translate them to lower case so that internally I don't have to
constantly worry about it. Note that even keywords are case insensitive,
so do the translation BEFORE the keyword check.
Rather then leave net types to implicit declarations, write
declarations explicitly. This will become necessary when more
interesting types are supported.
Separate elaboration from code generation in the Entity, and add
to Architectures a code generator to handle some simple cases. At
this point we have the basic structure for the VHDL compiler.
Elaboration will need a parse tree for expressions. Create one for
the expression types that are currently supported. Also add rules
and the keywords for all the remaining binary logical operators.
This patch adds a flag that emits file and line information for
most lines. This can help the user understand where the various
lines came from in the original code. They are printed as
comments so the generated code still runs correctly.
This patch fixes a bunch of objects to have the correct file/line
information. It also adds support for getting file/line information
for events (named events have a definition line).
When emitting a logical device as part of a continuous assignment
we need to use the actual inputs (not the output). We also do not
need to emit anything if the nexus is NULL. Also skip logical gates
that have a local output since they are part of a continuous
assignment and the inputs to a logical gate can be an expression
so emit them as a continuous assignment.
This patch adds the following to the vlog95 converter.
Add support for emitting and calling UDPs.
Generate a UDP for a synthesized DFF.
Add the ability do emit a constant assigned to a net.
This patch adds/fixes the following:
Adds file/line information to a UDP definition.
Prints an error message if a UDP is passed signals wider than 1 bit.
A UDP should supports a range, but the compiler currently does not.
Add scope information for constants.
Fix the Icarus extension UDP table entry element 'h' to use h.
The ivl_udp_init() value is a char not unsigned.
Add FILE_NAME() for a bunch more of the ivl interface objects.
This patch adds code that when it find a select of a constant it looks
for a parameter in the enclosing scope and the module scope that has
the same line, file and value information. If it find one that is
used to rebuild the expression. A more exhaustive search is need to
make this 100% clean.
It also uses the named scope when emitting statement inside a named
begin or fork instead of the enclosing scope.
This patch moves the logic and lpm code to a new file. It refactors
the strength emitting routine and adds support for emitting the
standard tran style of gates.
This patch adds the ability to translate the code produced by the
compiler for a wait statement back into a wait statement. It also
reworks the strength emitting code to only emit a single strength
for the pull gates and fixes a bug in the strength emitting code.
Currently the vvp target emits multiple single bit %mov instructions
to perform sign extension. This patch adds a new %pad instruction
that allows sign extension to be performed with just one instruction.
A NOOP at the end of an existing statement can be represented as ";\n"
(a simple line termination). In general a NOOP represents an empty
begin/end pair.
This patch add the following functionality to the vlog95 generator.
Add support for most CAs. Selects still don't work correctly.
Emitting a named event as an expression.
Enhance the ability to find a signal in a nexus.
Add code to emit a nexus driven by a constant.
Rework the delay/strength code for logic gates/CAs
Refactor some of the number code.
Refactor the variable emitting code to support named blocks.
Translate the compiler code back to <var> = <event> <value>
In the standard a pull device can be given both a 1 and 0 strength.
Only the appropriate one is actually used. This patch adds support
for giving both pull strength to a pull device.
This patch adds support for emitting an array as an expression. This is
used as a system task/function argument.
It partially reworks the real display code to print an appropriate
expression for NaN, inf and -inf. To get other real numbers to always
display correctly we need to build a custom printing routine that adjusts
what is displayed based on the actual bits in the double.
Add the ability to print a real variable delay. They are not scaled by
the compiler.
Since a delayx delay may be variable we must always enclose this type of
delay with parenthesis.
Fix the L-value concatenation to be in the correct order.
Handle the special case that an if with a single if as the true statement
does not loose any associated else clause to the enclosed if. Basically
add a begin/end pair as needed to make things work out correctly.
This patch fixes the following problem in the compiler:
An integer task argument should be marked as an integer port.
An implicit register can be converted to either a reg or an integer.
An old style task port should default to <no type> unless reg or some
other type is provided. ANSI style is always defined. For example:
input ri;
output ro;
inout rio;
real ri, ro, rio;
should define all three task ports to be of type real.
This patch updates the make clean target and modifies the vpath search to
match what is done in the main ivl Makefile since this one has the same
issues it does. It also adds a cppcheck target and removes the redundant
libmisc build target since the vpath already handles this.
This patch adds the ability for the user to change the spacing increment
from the command line using the -pspacing=<num> flag. The is restricted to
be a value between and including 1 and 16.
This patch fixes the ivl build to find files in libmisc using vpath instead
of a separate target. The existing constructs caused build problems after
running a make clean. It also adds an empty checking target to vhdlpp.
This patch adds preliminary support for finding the correct name for
a nexus at a given scope level. It also does the following.
Report that real modulus is not supported.
Fix a bug in the generation of concat expressions.
Add missing generation of unary ! operator.
Add ability to generate > integer delays.
Refactor some of the support code.
Make some of the error messages more descriptive.
Ignore the ALLOC and FREE statements (only used with automatic tasks).
If the left power operator expression is a numeric constant that has a
value 2^n n>0 then we can use a left shift to calculate the result. This
patch adds code to do this. All other power expressions are flagged as a
compilation error.
This patch adds significantly more functionality to the vlog95 back end.
The following are the major additions:
Display unsigned numbers without undefined bits in hex.
Add support for both L-Value and R-value bit and part selects.
Added support for out of scope references.
Added support for emitting logic gates (range not finished, name is invalid).
Added support for emitting initial/always blocks.
Add support for event inter statement delays.
Convert a blocking inter statement delay assign back to the original form.
Added support for rescaling variable delays.
Added support for the disable statement.
Added support for an event trigger statement (event name is missing).
Added support for calling a user task (calling arguments are missing).
Added support for an event based delay statement (@) (event name is missing)
Not all of these are working as expected since there is not currently a
routine to find a nexus name as a function of scope (needed for event names,
logic gate ports, etc.). Since the Icarus compiler generates structural code
the arguments to modules, module instantiations and calling user tasks are
also still missing.
Include the compiler infrastructure to vhdlpp for collecting the
file and line information and attaching it to entities and ports.
Make the parser store the file name during parse.
Create a libmisc library where I can put source files that are
used by multiple programs within the source tree.
Add enough rules to parse a simple VHDL program:
Parse library and use clauses,
Parse entity declarations, and
Parse architecture bodies.
Add some parser infrastructure:
Handle syntax errors with useful error messages,
Include file name and line numbers in parse errors,
Add some parser debug aids.
The original message talks about an unresolved net which may be
something different/more encompassing. This patch explicitly adds
uwire to the message to make it clear to the user that a uwire
could cause this message.
This patch doesn't completely fix the problem, but with it the problem
is at least manageable. The issues was that when the lexor_keyword.gperf
file is updated and you are building outside the source directory the
Makefile would create a local lexor_keyword.cc as expected. The problem
is that it always looked in the source directory for the file. This
patch adds a special vpath rule that says to look in the build directory
first and then in the source directory for lexor_keyword.cc.
This works as expected except for the first time the lexor_keyword.cc
file is generated locally. During the make invocation it compares the
source lexor_keyword.cc file to the gperf file and notices it is out of
date. It then generates a new file in the build directory, but the make
rule is still using the source file which didn't change so it doesn't
rebuild as needed. To get the new file to compile you need to run make
a second time to get the rule to execute using the local version of the
file. This extra make invocation is only needed when the local file is
first created since after that the rule always uses the local file.
I plan to look at resolving the remaining issue, but there is much
subtlety in this since you effectively need to break/rebuild the make
dependency tree to get this to build correctly in a single run.
This patch adds support for using a scope in an expression and calling
a user function. It also fixes an issue in the module name mangling
and calling a system task/function with multiple arguments.
This patch adds support for the various case statements and adds
preliminary support for instantiating modules. The module instantiation,
just like the module definition, is still missing ports. Adding this
will require modification to the compiler to get the port order correct.
Because of defparams and passed parameters any module that has a
parameter must be generated uniquely for each instance since they may not
all be the same. Modules without parameters are only generated once.
For diagnostics and to know what is really going on in the compiler
we need to keep any NULL that is in a verinum string or when
displayed as/converted to a string.
When padding a verinum string if the padding is in multiples of eight
then keep the string property.
This patch fixes a small bug found with the vlog95 back end. A root scope
should define is_cell instead of leaving it undefined. Normally I would
expect a root scope to not be a cell, but I don't think the standard
prohibits this from happening, so copy the value from the definition.
This patch adds the ability to print a delay expression (it is rescaled
to the module timescale) and adds support the following statement types:
nonblocking assignment with a delay (event control is still missing)
condition (if/else)
forever
repeat
while (Icarus translated for loops to while loops)
fork
procedural continuous assign
deassign
force
release
This patch adds support to the vlog95 convert for the ternary operator,
the concat/repeat operator and calling a system function. It also adds
the `celldefine information when appropriate.
This patch adds more support to the Verilog 1995 converter. There is
still a lot that is missing and there is still some implemented
functionality that is not 100%.
It was documented that ivl_scope_port(s)() could be used with tasks,
but the code did not support this. This patch adds that functionality
as documented. It also removes the documentation for ivl_lval_mem()
since that function no longer exists.
It was a poor choice to only add -g2009 for 1800-2009 and ignore the
previous version of System Verilog 1800-2005. This patch adds a
generation for 1800-2005 and also adds `begin_keywords support for
1800-2005. The previous SystemVerilog keywords have been put under
the 1800-2005 generation and the new one from 1800-2009 have also
been added.
When a verinum is displayed as a string we need to make sure that any
character that will be displayed as an octal constant must be converted
correctly. Also change to isprint() instead of isgraph() since it is the
same as isgraph() plus a space.
Cadence allows an ifnone with an edge-sensitive path. Until we understand
exactly what this is and how to implement it this patch adds a warning
that an ifnone with an edge-sensitive path is not supported.
Constant user functions aren't currently supported. A suitable
error message should be output when a user function call is
encountered in a parameter expression. This got lost in the
parameter expression rework.
The compiler currently performs parameter expression elaboration before
performing parameter overrides. This means that the information needed
to correctly determine the expression type and width may not be available
at the time elaboration is performed. This patch reworks the code to
delay elaboration until after all overrides have been performed. It
also provides a new -g option that controls how the width of parameter
expressions is calculated when the parameter itself is unsized.
This patch fixes a few compilation warnings introduced by the
enumeration code. It also updates the ivl.def file so that the
proper routines get exported under windows.
Using reg real [1:0] var you can define a real variable with a
range. This was crashing the run time. This patch catches this
in the compiler and prints an appropriate message.
This gets the enumeration type through to the ivl_target API so
that code generators can do something with it. Generate stub
output with tgt-stub, and generate the proper vvp run time to
make simple enumerations work from end to end.
With warnings turned sufficiently high in gcc, I get:
.../vpi_user.h:568: warning: function declaration isn't a prototype
when building VPI modules. Patch is trivial.
At the moment we only support one real driver. This patch adds a
combined error routine for a uwire or a real net with multiple
drivers. We display the top level net in the hierarchy. It also
reworks the nexus data_type calculation.
System tasks and functions can be defined to have NULL arguments.
This patch makes the @* sensitivity list calculation skip these
NULL (constant) arguments.
This patch adds asserts after new to verify that memory was allocated
correctly and adds a warning if some of the routines are called with
an invalid function name.
Create the v2009.vpi module to include SystemVerilog core
functions, and start out with some of the enum methods.
Add to vvp support for creating enum types, including some
vpi access methods.
The pform propagates the parsed enum base type information
to the elaborator so that the base type can be fully elaborated.
This is necessary to get the types of the enumeration literals
correct.
This patch covers more than it should. It removes many of the -Wextra
warnings in the main ivl directory. It also makes some minor code
improvements, adds support for constant logicals in eval_tree (&&/||),
adds support for correctly sign extending === and !==, it starts to
standardize the eval_tree debug messages and fixes a strength bug
in the target interface (found with -Wextra). The rest of the warnings
and eval_tree() rework will need to come as a second patch.
The files we get from GTKWave are not under our control so we need to
ignore the cppcheck style warnings for them. The random routines are
from the standard so they should not be changed to fix style warnings
either. We also have some weird, but correct pointer subtraction that
cppcheck warns about. This patch adds suppression files for all these
warnings. You must have the latest cppcheck from git since I submitted
a patch that adds the ability to place comments in the suppression file.
In ivl_alloc.h we redefine malloc(), realloc() and calloc() to have
standard error checking. We don't want to do this for anything that
comes from the standard headers. This specifically doesn't work if
a C++ header files does std::malloc, etc.
Also change to -W instead of -Wextra since that is more portable. I
plan to add a check from -Wextra and use it when available since it
is more descriptive.
This patch changes all the iterator code to use a prefix ++ instead
of postfix since it is more efficient (no need for a temporary). It
is likely that the compiler could optimize this away, but lets make
it efficient from the start.
When enum names are used as r-values in expressions, use their
values. Treat the enum names similar to (but not exactly as)
localparams so that they fit into the rest of the elaboration
flow naturally.
I'm adding more uses of the make_range_from_width function, so
it seems like time to get rid of its use of the svector template.
This thread led to a lot of other uses of svector that had to
also be removed.
BOOL values have a specific cast from LOGIC, this node takes care
of it. Also arrange for the elaboration to insert them in the right
planes and for the code generator to generate them.
This patch adds -Wextra to the compilation flags for C++ files in
the vvp and vpi subdirectories. It also fixes all the problems
found while adding -Wextra. This mostly entailed removing some of
the unused arguments, removing the name for others and using the
correct number of initializers.
This patch adds support for running cppcheck from the Makefile. It also
standardizes the order of some of the targets. It renames vpip_format.c
to vpip_format.cc and fixes the size of the array tables to make room
for the trailing NULL. Found when using a C++ compiler.
This patch adds a few missing initializations to various constructors
in the vvp directory. It also enhances the array alias code to copy
more values from the aliased array.
Starting in autoconf 2.68, "the macros AC_PREPROC_IFELSE,
AC_COMPILE_IFELSE, AC_LINK_IFELSE, and AC_RUN_IFELSE now warn if the
first argument failed to use AC_LANG_SOURCE or AC_LANG_PROGRAM to
generate the conftest file contents."
IVL_VT_BOOL variables at the code generator should generate
.var/2x records so that the run time can do 2-value optimizations
and otherwise support atom2 values.
SystemVerilog allows variables to be either variables or unresolved
nets, depending on how they are used. If they are assigned by
procedural code, then they are variables. If they are assigned
by a continuous assignment, they are unresolved nets. Note that
they cannot be both, and when they are unresolved nets they can
only be assigned once.
Create the .var/2u and .var/2s variable records and give them
basic implementations. Make available to VPI the proper types
for the SystemVerilog types that these variables represent.
Follow-up to "Brainless start to const-correct changes"
Still actually does nothing, but now if the #define ICARUS_VPI_CONST
in vpi_user.h is changed to const, Icarus is almost const-correct,
as checked with gcc flags -Wcast-qual -Wwrite-strings.
Choosing when to #define ICARUS_VPI_CONST const is left as an
exercise for the reader.
With these two patches applied, and the const define, there are
still about a dozen const problems left.
Results of running
cd vpi
for f in *.c *.h; do sed -i \
-e "s/_calltf(PLI_BYTE8/_calltf(ICARUS_VPI_CONST PLI_BYTE8/" \
-e "s/_compiletf(PLI_BYTE8/_compiletf(ICARUS_VPI_CONST PLI_BYTE8/" $f; done
and a trivial patch to vpi_user.h to, among other things, make
ICARUS_VPI_CONST blank.
Thus, this patch does absolutely nothing. Will be followed by a
(much shorter) patch that makes it do something. :-)
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
For example:
-- Generated from Verilog module child (vhdl_tests/generics.v:30)
-- MY_VALUE = 3
entity child is
To make it clear which values were used for this entity.
Conflicts:
tgt-vhdl/scope.cc
This changes the implementation of $display/$write to use VHDL
report statements rather the the std.textio functions. The code
produced is simpler and more like what a real VHDL designed would
write. However it no longer exactly matches the Verilog output as
most VHDL simulators prepend the text with simulation time, entity
name, severity level, etc. There is a corresponding change in
ivtest to support this.
Conflicts:
tgt-vhdl/cast.cc
tgt-vhdl/display.cc
tgt-vhdl/vhdl_syntax.cc
tgt-vhdl/vhdl_target.h
Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).
An example:
begin
x = 5;
if (x == 2)
y = 7;
end
Becomes:
x <= 5;
wait for 0 ns; -- Required to implement assignment semantics
if x = 2 then
y <= 7; -- No need for wait here, not read
-- wait for 0 ns (previously)
end if;
Conflicts:
tgt-vhdl/process.cc
tgt-vhdl/stmt.cc
tgt-vhdl/vhdl_target.h
Add code to print a warning if the user tries to use the -S flag.
We need this warning since synthesis is not currently being actively
maintained or supported in any branch after V0.8.
An unsized signed constant that is smaller than integer_width needs
to be resized up to either the integer_width or the expression width
whichever is smaller.
Fix all the Icarus files that can be so that we do not have any
signed/unsigned compare warnings. It also removes const as a
return qualifier for two routines in discipline.h.
This patch mimics what was done for vectors, but is simpler since
arrays don't use the endian information. It also needs to address
the fact that .array/port assumes the expression is unsigned so
any signed expression must be padded to make it larger than the
maximum array word when it is converted to unsigned.
This patch modifies all the variable bit and indexed part selects
to use a common routine. This routine determines the minimum
width needed to calculate the result correctly, pads the expression
if needed and then converts the expression to signed if required to
make the calculation correct.
The Cygwin man command requires that you have a / in the path
if you want to avoid looking at the normal search path. This
patch addes ./ before the manual page file name. Which should
work on any system. It also makes the vvp generation create a
PS file like is done in the other Makefiles.
By default we generate normal manual pages. You can then
create PostScript version and from these you can generate a
PDF version.
While checking for an infinite loop in an always block I missed
the case where an if statement does not have a statement. This
was resulting in a segmentation fault.
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
If someone accidentally makes a parameter depend on itself
we need to report this not crash. This patch fixes the crash
and prints an appropriate string of messages to figure out
the loop. Icarus currently supports forward references of
parameters so more complicated loops can be created. These
are also caught.
To prevent a force from back propagating we need to keep a BUFZ
that represents a continuous assignment between two nets. This
only effects continuous assignments of the form assign out = in.
In general these are fairly rare so keeping them has minimal
impact on the simulation speed.
Add code to print a warning if the user tries to use the -S flag.
We need this warning since synthesis is not currently being actively
maintained or supported in any branch after V0.8.
For example:
-- Generated from Verilog module child (vhdl_tests/generics.v:30)
-- MY_VALUE = 3
entity child is
To make it clear which values were used for this entity.
This changes the implementation of $display/$write to use VHDL
report statements rather the the std.textio functions. The code
produced is simpler and more like what a real VHDL designed would
write. However it no longer exactly matches the Verilog output as
most VHDL simulators prepend the text with simulation time, entity
name, severity level, etc. There is a corresponding change in
ivtest to support this.
Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).
An example:
begin
x = 5;
if (x == 2)
y = 7;
end
Becomes:
x <= 5;
wait for 0 ns; -- Required to implement assignment semantics
if x = 2 then
y <= 7; -- No need for wait here, not read
-- wait for 0 ns (previously)
end if;
This patch adds a check in the vvp back end that a uwire has
at most one driver. Previously this was just converted (with
a warning message) to a wire just after elaboration.
This patch adds the ability to call a system function as a task for
the SystemVerilog generation (-g2009). The return value is really
calculated, but it is ignored.
E.g. $signed(x) > y with x, y different sizes should be
resize(signed(x), N) > y
Not
signed(resize(x, N)) > y
As this does not treat the sign bit correctly. Was causing
the signed5 test to fail.
Added 'expr_wid' parameter to calls to 'eval_expr()' within
PEBinary::elaborate_eval_expr_base_()'. This makes a specific problem
go away and may even be the correct thing to do.
This patch adds support for a UDP with variable delays. In the process the
intrinsic support for delays was removed from the UDP functor and replaced
with a call to the .delay functor. Both a normal gate and a UDP now use the
same code to generate the delay.
This patch adds checks that the delay count is correct for the
various gates and adds support for a missing variable decay
time. For this case the decay time is the minimum of the rise
and fall times. This is denoted by setting the decay variable
to 0 in the vvp file. vvp notes this and sets an ignore decay
time property in the base delay. This turns off the ability
to set the decay time and the minimum delay calculation will
also update the decay time.
These checks are not needed since we have already verified that
we have a 64 bit immediate value. This is likely old code that
should have been removed when the original functionality was
changed.
This patch pushes delays for tranif gates to the code generator.
We still need to add checks for the number of delays, etc. For
now an error message is printed when a tranif gate is given a
non-zero delay.
This patch modifies the real ternary operator code to support
unlimited tail recursion without overflowing the thread
registers. Head recursion is still limited by the available
registers.
It fixes the thread word checks to use a new define that has
the correct number of thread words (16). It adds a message
instead of just an assert if the thread words are exhausted.
And it also changes some of the error messages to use vvp.tgt
in the message to be consistent with the other messages.
Elaborate conditional assignments with BUFZ devices that do *NOT*
preserve strengths. Add a BUFT (transparent) device that can be
used in those cases where I really need a transparent buffer.
We only need to set the width of a multiple if the width is greater
than zero and if the expression is vectorable. This matches what is
done for addition.
A real delay must be scaled and rounded using the local precision
before it is finally scaled to the simulation time units. This
patch fixes the compiler to do this correctly or generate the
correct code for run time calculated delays. Delays in a CA
already worked correctly. The run time was also fixed to scale
modpath (SDF back annotation) delays correctly.
This patch modifies the vvp main code to cleanup if there was an
error compiling the input file. There are still a few issues, but
this takes care of most of them.
The error routines for task and function definitions were incorrectly
popping the scope. This should not be done since no scope was pushed.
Also assert that the current_task/function is 0 to catch that kind of
error like the other definition rules.
This patch adds two new opcodes and the infrastructure needed to call
system functions as tasks. The normal %vpi_call will generate an error
if a system function is called as a task. %vpi_call/w will generate a
warning and will ignore any value returned by the function. %vpi_call/i
will ignore the system function return value and will not print a
message. Adding this is a feature request and is supported in
SystemVerilog. Next I need to add flags to control this depending on
the compiler generation and possibly other flags.
I may leave the cast to void (%vpi_call/i) functionality unimplemented
for now.
This patch caches the vpi_call error messages (task/function does
not exist, task being called as a function and function being
called as a task). This allows us to display the file name and line
number information for the invalid usage.
When pushing the current file path we need to get past any `define
expansions that have been pushed onto the stack to find the real
file path.
This patch is partially based on a patch submitted by Steve Tell.
This patch avoids a crash when trying to use a parameter/localparam that
has been assigned a value from a constant user function. Icarus does not
currently support constant user functions so it creates a parameter with
a NULL value. This patch fixes a few places where this could crash the
compiler.
You need to probe the expression width before trying to elaborate and
evaluate an expression. The eval_path_component() routine was missing
this and was causing an assert.
The functions (malloc, free, etc.) that used to be provided in
malloc.h are now provided in cstdlib for C++ files and stdlib.h for
C files. Since we require a C99 compliant compiler it makes sense
that malloc.h is no longer needed.
This patch also modifies all the C++ files to use the <c...>
version of the standard C header files (e.g. <cstdlib> vs
<stdlib.h>). Some of the files used the C++ version and others did
not. There are still a few other header changes that could be done,
but this takes care of much of it.
gcc on OpenBSD reported shadow warnings for variables, arguments named
log, time and exp. This patch renanes those variables to logic, timerec
and expr.
This syncs fstapi.c to the latest from GTKWave CVS. This cleans up
most of the issues. I still have two to track down, but I think they
are cppcheck bugs not fstapi.c deficiencies.
The fstHandle is only a uint32_t so to avoid compiler warnings on 64
bit systems cast this to long before casting to a pointer.
Also reformat some of the code to match the rest of the Icarus code.
This patch documents that the lxt2/lx2 dumper supports -speed and
-space options. It adds -speed, -space, -space-speed and
-speed-space options for the fst dumper. Here are results for a
gate level back annotated design using the fst dumper.
<none> 12.88 seconds 3.5 Meg dump file.
-space 12.89 seconds 2.9 Meg dump file.
-speed 12.36 seconds 4.6 Meg dump file.
-<both> 12.84 seconds 3.2 Meg dump file.
We keep a scope list that is checked to verify that we do not try
to dump duplicate scopes or variables. Since the scan_item routine
can not add duplicate scopes we only need to sort the list after
the scan_item routine is called. Calling it every time a scope
was added was creating a significant startup delay for gate level
simulations since the sort routine is called for every scope in
the design (possibly thousands of times).
This mostly matches what was done for the LXT dumper except the
LXT dumper was incorrectly sorting before not after scan_item
was called. This would not catch a duplicate variable just
after a scope was added in a $dumpvars call.
The lxt2 routine was referencing the lxt not the lxt2 versions
of the space/speed flags. This also adds the lx2 version of the
flags. These were already supported in the sys_table.c file.
This patch is a slight modification to files Tony Bybell (the author of
GTKWave) send to me. We still have a few more changes we plan to make,
but this should be functional enough for initial testing. Multi-treading
and speed/size flags will be added shortly.
The make_pair() routine has a PExpr* as the second argument. Not all
compilers can promote a child correctly, so just assign the child type
to a PExpr* when they are created solves this issue.
vpi_config.h defines _FILE_OFFSET_BITS. This must be defined before
any system includes files are processed, so vpi_config.h must be
called first. This patch puts vpi_config.h first. It also removes
direct calls for both vpi_config.h and vpi_user.h when sys_priv.h
is included since it already includes these two files.
It also updates the code to always include vpi_user.h using double
quotes.
Using -xMD generates dependencies for all files including the
system files. This could point to some system .cc files and
was causing GNU make to try to build these files if the
dependency files existed. Using -xMMD generates only the
dependencies outside the system directories.
It's possible that the OpenSolaris make knows how to deal with
this correctly, but Icarus needs GNU make.
This is generating an octal constant but there is no reason to have
three '\' characters. You need two to get the leading '\', but the
last one is not needed.
The SunPro compiler does not support struct definitions inside an
anonymous union. This patch moves the struct definition so that both
gcc and SunPro 12.1 compile this without issue.
gcc supports creating an array with a run time defined size. The
SunPro compiler for OpenSolaris does not. This patch converts the
array creation to use conventional (malloc based) array creation.
This patch is similar to the previous patches and cleans up a single
place in the vvp directory where an enum had a trailing ',' and a
place where a C++ routine needed extern "C".
Some new shadow issues have crept in. This patch fixes these new
issues and adds -Wshadow to the normal warning flags to keep any
new occurrences from happening.
Since the base lxt_write.c and lxt2_write.c files reference <config.h>
instead of "vpi_config.h" all their definitions need to be moved to
the main config.h include file.
This patch updates all the Makefile.in files and configure.in
as follows:
Do not use the -Wall warning flag when using the SunPro compiler.
The SunPro compiler uses -xMD instead of -MD.
There are still more fixes needed before Icarus will compile
on OpenSolaris.
Tran islands must do their calculations using the forced values,
if any. But the output from a port must also be subject to force
filtering. It's a little ugly, but hopefully won't hurt the more
normal case.
The comparison and reduction operators only have a single output bit
that can be delayed.
The comparison of real values always produces a logical value so the
delay type is not dependent on the arguments type.
The repeat expression is evaluated in a self determined context
(expression width == -1). It needs to call probe_expr_width() to
figure out the width needed by the expression before calling
elab_and_eval() to elaborate the expression.
This patch updates the lxt_write.h and lxt2_write.h header files
to the latest ones from GTKWave CVS. It also adds HAVE_INTTYPES_H
to the vpi_config.h.in header.
This patch fixes two places where Icarus under certain conditions
would try to free a NULL iterator value in $dumpvars(). $dumpvars()
can have a NULL argument to indicate that all variables should be
dumped. Under two error conditions the code was trying to free
this NULL argument reference.
The standard does not define if vpi_free_object() can support a
NULL reference. Icarus does not currently allow it (it asserts).
This patch adds support for converting bit based ports to real signals.
You can only do this for single instances. Arrayed instance would
create multiple instances driving the same real signal.
Any real port can be connected to a bit based signal. The only limitation
is that the signal width must be an integer multiple of the instance
count since all the real conversions must have the same width.
Also add an error message for an arrayed instance with real to real
output connections. Again multiple drivers.
This patch also adds errors for inout real and bit based inout ports
driving a real signal. There is no logical way to deal with the full
capabilities of inout and real ports/signals. So for now they are not
allowed.
This patch remove the old VAMS $log function. It could create confusion
with the Verilog $log task. Recent versions of VAMS and 1364-2005 use
$log10 for the base 10 logarithm.
Comparison expressions have sorta-self-determined arguments.
Handle the special cause that some of the arguments may be
themselves unsized, and so expecting to be even wider then
otherwise.
Operands to reduction unary operators are self determined, so
evaluate the operands that way. But this means that binary expressions
in this context should take pains to use their test_width tested
expression width.
This exposed a case where the test_width methods were not called
for self-determined expressions. Fix that too.
It is acceptable to call delete on a NULL object. It's also acceptable
to assign the value to zero if it is already zero. Removing the
superfluous if should produce slightly better code since there is no
conditional to deal with except for what is likely in the delete
implementation, but that should be highly optimized.
This patch cleans up some style issues: no need to check that a value
is defined before freeing or deleting it, use C++ style casts, make
sure to NULL terminate strncpy(), empty() is faster than size() for
size == 0 or size >= 0 checks, re-scope some variables, etc.
When searching for a symbol we do not want to search up the
hierarchical stack if the symbol we are searching for was
prefixed with a hierarchical path.
This patch adds support for iterating over the list of vpiUserSystf
tasks/functions that have vpiUserDefn set. The vpiUserDefn property
is true by default, but you can call vpip_make_systf_system_defined()
to set this property false (will hide the vpiUserSystf object). All
the normal system tasks/functions have been modified to call this
procedure to remove them from the list of vpiUserSystf objects. Only
user defined system tasks or functions should appear in the list.
vpi_compare_objects() is just a simple are the two pointers the
same. This works correctly for the vpiUserSystf objects, but the
other handle objects have not been checked.
This patch changes system tasks and functions to use the vpiUserSystf
property and returns this information when vpi_register_systf() is
called. It also adds the vpiUserDefn property for system tasks and
functions which for now always returns 1 (true). System task and
functions can now get a handle to this information using the
vpiUserSystf property. vpi_systf_info() returns pointers to the
real data so the user will need to be careful when using the pointer
fields (e.g. tfname, user_data, etc.). This is a shallow copy. A deep
copy would require the user to free the various fields and I'm not
certain it is even possible or desirable to copy the user_data for
all cases.
A stub for vpi_compare_objects() was also added since I will need
that when testing the second half of the patch (add iteration over
all the vpiUserSystf objects and add a method to control vpiUserDefn).
The latest gcc with the latest Cygwin complains when passing a char to
the toupper, tolower, isspace, isalnum, isprint, isdigit or isalpha
functions/macros. These functions are defined to take an integer. This
patch adds cast to int as needed to remove the warnings. After this
there are still two warnings related to signed/unsigned comparison in
yy_get_next_buffer() (part of flex).
To ensure the initial propagation of 'x' values at time-0 does not
trigger any events, the propagation of these values needs to be
completed before any statements that wait on events are executed.
vvp has a pre-simulation event queue to handle this, but some
functors defeat this by postponing their output propagation using
the stratified event queue. This patch fixes this by using the
pre-simulation event queue to schedule functor output propagation
until initial value propagation is complete.
To match the behaviour of other simulators, delayed bit-based signals
should have the value 'x' and delayed real valued signals should have
the value 0.0 until the true initial value has propagated. This patch
provides this behaviour.
Under certain circumnstances, the vvp code generator can generate
a .part/pv that directly feeds an input port of a .concat. This
patch adds a recv_vec4_pv method to the vvp_fun_concat class to
handle this case. It also changes the initial value of the stored
vector from X to Z to correctly handle bits which are not driven.
If a net is driven by a simple variable, an initial 'x' value is
propagated to the net at time-0. The same thing should happen if
a net is driven by a variable array word. This patch makes this
happen by scheduling an initial event for each array port attached
to a variable array.
The SDF file format supports zero or more timing specs. Previously
the parser was one or more. Things like tie high/low cells do not
have any delay information so zero or more is needed and matches
the standard.
When building a modpath the source for the modpath must have the
same scope as the modpath. This is required to make the back
annotation work correctly (have the correct names).
This is the initial commit in an effort to build a 1364-1995
back end for Icarus Verilog. It is expected that this back end
will allow the user to write 1364-2005 RTL and then using this
back end (converter) generate functionally equivalent 1364-1995
compatible code. This can be used to support older tools in a
work flow. The primary focus will be simulation equivalence,
though I expect to verify logical equivalence as well.
The vpi_get_value() function should not crash when called during
the compiletf phase. This patch fixes this by returning 'bx for
any vectors in thread space. It also fixes some other minor things
that my test code uncovered. Most of the other objects work as
expected.
This patch enhances elaboration to drop/ignore zero replication
count constants. Not doing this was causing problems later in
the compiler. We still pass non-constant expressions since
both user and system functions must be run for their possible
side effects. Constants can never have a side effect so just
dropping them is acceptable.
This patch adds support to $sdf_annotate to ignore RECREM constructs
in the SDF file. It also adds the ability to not specify all the
values in a rtriple (e.g. 1.1::1.6).
This patch adds support for passing the delay selection to the
VPI interface. It adds a new property to both the vpi_get and
vpi_get_str calls to return the current delay selection. It also
defines three constants for minimum, typical and maximum
delay selections.
This patch adds support for passing the delay selection to vvp.
It adds a new header :ivl_delay_selection "<value>"; that has
the values TYPICAL, MINIMUM or MAXIMUM depending on the -T
flag to iverilog. This information is needed by $sdf_annotate
to select that appropriate value for a triplet when
"TOOL_CONTROL" is specified (default).
This patch mimics what was done for normal assignments to get the
width correct for nonblocking assignments when converting a real
r-value to a l-value vector.
A named event does not have an edge so taking a posedge or negedge
is illegal. This patch adds an error message for this. Before the
edge was being ignored for named events, but this is incompatible
with other tools.
Generate schemes may nest freely, but generate regions
(an anachronistic concept from 1364-2001) cannot nest,
not within schemes or other regions. Have the parser detect
the nesting and print an error message.
Move check of the value $fatal is called with from the compiletf to
the calltf routine, since the value may not be known at compiletf
time. If the value is invalid, it just prints a warning that $fatal
was called with a bad finish_number, and resets it to the default 1.
Changes the compile time check for a numeric argument to a warning.
Also, fixes bug where $fatal called without an argument causes problems.
When selecting bits from unsized literals, we do not put a limit
on the size of the literal, so there is no top above which we
stop getting literal bits.
Icarus does not support interconnect delays so INTERCONNECT is
currently ignored. The SDF parser does not currently support a
bit select as a port_instance. Since we are already ignoring
the INTERCONNECT I added support for bit selects there. This
is probably the most common place to find them.
This is part of the 1800-2009 standard (Section 23.3.2.3) and allows
ports of module instances to be declared like:
modname instance(.foo, .bar);
instead of
modname instead(.foo(foo), .bar(bar));
The only tricky part about this is the implicit port connection shall
not create an implicit net declaration. To make this happen, the path
of least resistance was to add a bool to PEIdent indicating that it
should not implicitely create a net.
This does not rely on the generation flag to be 2009, following the
trend that new port naming convention (like ANSI style ports) work
regardless of the generation.
Added generation flag -g2009 which enables support for 1800-2009
constructs. Added related support such as "1800-2009" in the
`begin_keywords directive.
Keeps 2005 as the default generation for now.
Removed the -gsytem-verilog flag and folded the 1800-2005 stuff into
1800-2009. The rationale behind this is we have so little of
1800-2005 actually implemented that it does not make sense to
distinguish between 1800-2005 and 1800-2009 SystemVerilog extensions,
so we just count them all as the new 1800-2009 Verilog language.
When using MinGW, routines registered via atexit() inside a
DLL are only called when the DLL is detached. If not detached
manually, DLLs are automatically detached *after* all remaining
open files are closed. This meant that by the time the LXT or
LXT2 close_dumpfile routine was called, the dump file handle
was no longer valid, so any remaining output was lost. This
patch fixes the problem by manually detaching the VPI modules.
Like I did for SystemVerilog the other day this patch adds all the
Verilog-AMS 2.3.1 keywords. This necessitated adding one my byte
to the gperf -k argument (byte 9) to make the laplace_?? tokens
have a unique hash.
This patch adds the SystemVerilog keywords to Icarus. This allows
use to easily verify that out plain Verilog does not contain any
SystemVerilog keywords. The keywords are not parsed in any way.
When parsing a Verilog file using -gsystem-verilog any identifier
that is a keyword will cause a parse error. It is the users
responsibility to figure out the problem since bison does not
give nice error message when it finds a keyword instead of an
identifier.
When handling the $signed/$unsigned system functions, the compiler
was applying the new signed/unsigned property to the NetExpr object
representing the input argument. This caused the input argument to
be evaluated incorrectly. This patch fixes this by applying the new
property to the NetExpr object created to pad the result to the
required size.
In testing this fix, it was also discovered that the width of the
input argument expression was not being calculated correctly. This
patch also fixes this issue.
Creation of implicit nets requires knowledge of whether an identifier
has been declared before it is used. Currently implicit nets are
created during elaboration, but by this stage the order of declaration
and use is not known. This patch moves the creation of implicit nets
into the parser stage.
After changing an array word, vvp propagates the change to every port
attached to the array. The code did not properly handle the case of
an array port declared in an automatic scope with an associated array
declared in a static scope.
The process of inverting and copying can be collapsed into a single
operation that should run a little faster. Also, inverting readily
vectorizes itself. I've also possibly reduced useless vvp_not_fun
iterations.
Also, include some minor tweaks to the vvp_vector8_t handling of
vector copies. This is more to clean up code, although it should
slightly improve performance as well.
The zero element was already returned so it can not be reused a
second time. This was crashing when things went off the end of
the list since the do all functor was off by one.
In a typical debug simulation run, a user tracing all the signals
in the simulation may wind up creating millions of these. Rework
the vcd_info structure to be more compact and possibly faster to
scan.
The scope thread rework broek --with-valgrind builds due to the
different handling of the list of threads. Rework valgrind enabled
handling of the thread set within a scope.
Rather then lock/unlock the work queue ring for every item, save
tons of pthread lock manipulation by allocating to the producer
in batches. Over the long run, this doesn't change the CPU balance
or hold up either thread, but it eliminates almost 3/4 of the
lock/unlock episodes.
The time change is usually a trivial operation, so instead carry
a timestamp on all the work items and let the work thread decide
on its own when to do a SET_TIME operation. This reduces some
pthread overhead and thus gets us some better performance.
The scope contains the threads running within. The rework of this
patch allows all threads to know their scope, and cleans up the
handling of threads listed in the scope.
The padding for a signal select was using the signal to determine
if the padding should be singed or not. In reality this should be
unsigned padding unless the select was enclosed in a $signed().
dlltool which is used by both MinGW and Cygwin to create dynamic
libraries must have the name of the executable it creates the
library/information from exactly match the installed executable
name. If we have a suffix then it must be used. This patch adds
that to the build process for vvp since it can be installed with
a suffix. It also modifies the check routines since you must run
vvp with a suffix if the library it links to was built for a
suffixed executable.
In combination with the patch to make all operations on thread words
operate on 64-bit values, this patch ensures casts between real values
and large vector values work correctly.
The vvp thread word storage had previously been changed to always store
64-bit values, but some instructions still only operate on native long
values. This patch ensures all instructions that modify thread words
support 64-bit values.
When passing an argument to a user function in a continuous assignment
we need to sign extend the value if it is signed and too short. We need
to crop an argument if it is too long.
When evaluating a function argument expression we need to use either
the expression width or the argument width which ever is larger. This
matches the way normal assignments work. We then only take the bits
needed at the end.
Newer versions of GHDL seem to be stricter when checking this than
older versions. ModelSim still accepts an incomplete with-select,
however.
This patch makes the output 'U' if none of the conditions match.
We do have one C program in the vvp directory so add CFLAGS to
the Makefile. This patch also modifies the two local programs
tables and version to use -Wall.
The function draw_scope was extracting the input/output parameters
just by looking at the (unordered) list of signals in the function
scope rather than using the ivl_scope_ports list.
The Cygwin compiler is a bit picky. This patch adds some casts
to remove compilation warnings. In the past I have had warnings
off because of problems with the STL, but for C directories
like this it makes sense to enable the warnings. It also does
not recognize that an assert(0) or assert(false) ends a routine
so it complains about no return at end of function or variables
not being defined.
The Cygwin compiler is a bit picky. This patch adds some casts
to remove compilation warnings. In the past I have had warnings
off because of problems with the STL, but we may as well get
rid of the warnings we can. It also does not recognize that an
assert(0) or assert(false) ends a routine so it complains about
no return at end of function or variables not being defined.
The Cygwin compiler is a bit picky. This patch adds some casts
to remove compilation warnings. In the past I have had warnings
off because of problems with the STL, but for C directories
like this it makes sense to enable the warnings. It also does
not recognize that an assert(0) or assert(false) ends a routine
so it complains about no return at end of function or variables
not being defined.
The Cygwin compiler is a bit picky. This patch adds some casts
to remove compilation warnings. In the past I have had warnings
off because of problems with the STL, but for this directory we
may as well squash as many warings as we can. It also does not
recognize that an assert(0) or assert(false) ends a routine so
it complains about no return at end of function or variables
not being defined.
The Cygwin compiler is a bit picky. This patch adds some casts
to remove compilation warnings. In the past I have had warnings
off because of problems with the STL, but for this directory we
mas as well remove the warnings we can. It also does not
recognize that an assert(0) or assert(false) ends a routine so
it complains about no return at end of function or variables
not being defined.
Currently the compiler only applies defparam statements that are
found in the initial root module hierarchy. This patch ensures that
defparam statements within scopes created by generate constructs or
instance arrays are also applied.
The NetEvent::find_similar_event method should limit its impact
on the netlist (and Nexus objects) by reducing the candidate event
list as it goes, instead of collecting data and testing later.
It turns out that although there was all kinds of code to manage
these members, there were no uses anywhere. It must have been a
legacy from a previous era. So remove the dead code so that it
doesn't confuse me again.
Remove some wasteful and excess scans of the Nexus of some links,
and remove dead code so we can see what we're doing. Also inline
some commonly used and trivial functions.
Child scopes need to be accessed quickly, so use O(LogN) maps for
the children instead of O(N) lists.
Also, ivl_net_const_s objects exist in huge abundance for some kinds
of designs, so put some effort into reducing their memory footprint.
Once code generation starts, the Nexus structure no longer needs to
support fast insertion/connect operations. So have the code generator
lock down the Nexus structures and adjust the Link lists for optimal
access during readout.
When netlists get very large, the Nexus::connect() method tickles
the O(N) performance and elaboration gets very slow. Rework the
connect method to be O(C), for a drastic performance boost for
large designs.
This simplifies and reorganizes this function in order to improve
the performance of this function by a constant factor. I think we
really need to improve this by an entire order (and not just a
simple factor) but this helps.
The MinGW executable should be able to support a path with mixed
separators, but to make things consistent all the path in the main
driver program (driver/main.c) now always use a '\' or convert a
path to use '\' (e.g. getenv() returns a path with a '/').
The fix for pr1830834 causes vvp to only delete a completed thread
when the simulation time next advances. If a procedural model is
being simulated which makes many task or function calls within a
single time step, this can lead to excessive memory use. This patch
modifies the behaviour so that thread deletion is only delayed if
that thread has caused a sync event to be placed in the event queue.
This should catch all cases where the thread private data can be
accessed after a thread has terminated.
The functionality of the integer power operator is specified in
1364-2005 on page 45-46 and specifically Table 5-6. This patch
fixes the verinum pow operator to work as specified in this
table. It also fixes an error in the == operator when both
operators are signed and only the left argument is negative.
These explicit dependencies are not normally needed (because they
are covered by automatic dependency generation) but when the "-jN"
flag is passed to gmake, they help gmake schedule parallel builds.
(cherry picked from commit 5479aaf721)
This patch updated the four file lxt_write.{c,h} and
lxt2_write.{c,h} to the latest ones from GTKWave. This
required adding the wavealloc.h include file and an
update to configure.in and vpi/vpi_config.h.in to add
checks/definitions for ALLOCA and FSEEKO.
This patch adds support for spaces in the path to the temporary files.
Adds support for spaces in output files and in library paths.
A space in the installation path is only supported under MinGW
(windows) at this time.
This patch converts a few sprintf statements to snprintf
to protect against buffer overflow.
It also converts a few sizeof calls from sizeof(x) to
sizeof x like other places in the code.
Add driver-vpi to either SUBDIRS or NOTUSED depending on if we
are building for MinGW or not. This is more logical and allows
the clean and distclean targets to be simplified.
During startup it is possible for input port to not yet be
initialized even after some other input ports trigger the
function to be evaluated. Handle this case by substituting
a vector of 'bx for the uninitialized inputs. This will shake
out when the simulation gets going, and only matters for user
defined functions in continuous assignments.
While we're at it, have vec4_unfiltered_value return a reference
to reduce copying of vectors.
This patch adds support for spaces in the install path on MinGW.
It does this by converting the Long version of the iverilog path
into a Short version that does not have spaces in it. If we don't
do this then we can not add support for other arguments with
spaces in the path or filename. It also modifies the driver-vpi
program to support spaces in the saved ivl path. This is done by
just enclosing the include and library path argument in double
quotes.
The issue on MinGW is that if you put the executable argument to
system in double quotes to escape embedded spaces then you can
not put the arguments in double quotes as well. If you convert
to a Short name then the spaces are removed and we can in the
future escape the arguments as needed.
This patch fixes a few more issues related to building
in a remote directory. The start of the problem was
that the version file was not getting built correctly.
This necessitated using vpath instead of VPATH to only
allow the %.cc files. After that a few other places
needed to have $(srcdir) added.
The distclean target was also enhance so that when
building from a remote directory (srcdir != .) we
remove all the extra files and directories.
Try to put all the version stamps into common version_base.h
and version_stamp.h header files. All the source programs then
get their version from these header files.
Also handle the version stamps in the man pages by using the
version_*.h header file contents to edit the version strings
in the man page title bar markers.
If the source and destination of a subvector to be moved in the
vvp_vector4_t::mov method is nicely word aligned, and the transfer
size is a full word, then we ar much better off handling that as
a special case. This makes the move faster, and also avoids some
shift overflow errors.
If the delay has an event pending for the current time, then use
that as a reference for calculating the next delay. If that is not
done, then the delay calculated against the wrong reference might
result in zero, and bad results.
For the %mov instruction, implement a vvp_vector4_t::mov method to
manipulate the thread vector directly.
For the %load/v instruction, rework the vec4_value() methods to
avoid creating vvp_vector4_t temporaries, and therefore reduce the
copy overhead.
If a function in a continuous assignment is passed an array word as
an argument, syntactically incorrect vvp code is generated. This is
because the code calls draw_net_input to generate the input labels
part way through writing out the .ufunc statement. If an input is
an array word, draw_net_input causes a .array/port statement to be
emitted, which gets written out in the middle of the .ufunc statement.
This patch fixes the problem by collecting the necessary input labels
prior to starting writing the .ufunc statement.
The $setuphold and $recrem timing checks can create delayed signals
that are needed to get a model to work correctly when negative timing
check values are used. Since we do not support timing checks and just
ignore them this can create simulation problems when a user tries to
use these delayed signals since they are not driven.
This patch adds a waring when the circuit is being compiled that these
delayed signals will not be driven. This will be needed until we get
time to add the real timing checks are mimic the delayed properties of
the timing check.
Minor fixes and code reorganization to remove a few more issues
that cppcheck is complaining about. It has a few false warnings
and some issues that need more investigation.
Apparently, the vpi_user.h definitions for vpiStop et al were added
before they were standardized by 1364-2000, and never corrected.
Change the values to be standard. (Submitted by Matt Trostel.)
I also added some binary compatibility for existing .vpi modules
that were compiled with the older constant values.
This patch removes bin32 from the clean targets since it is no
longer user/created. It adds autom4te.cache to the distclean
target in the main directory. It removes the files in driver
that are not created (lexor.c parse.c, etc.). The *.cc.output
files are no longer created so removing them is not needed.
The local "memory.h" file is no longer used in V0.9 or development,
so it does not need to be included in vvp/codes.h. The VHDL target
does not use the system <memory.h> header file so there is no need
to have a define for it in the vhld_config.h.in file.
This patch modifies the iverilog -M command line option to allow
the user to specify an optional output mode that controls which
files get added to the dependency list. This allows the user to
either get a list of all files that contribute to the design,
or a list of the include files, or a list of the module files.
The .delay (x,y,z) functor and the get_number_immediate() function
only supports 32 bit delay values. This patch adds an error message
if the user passes a larger, but valid value.
- Add missing dependency of configure on aclocal.m4.
- Remove config stamp files in make distclean (and fix another for
loop in base make distclean that I missed)
- Add stamp files to .gitignore
Use the time stamp file technique recommended by the autoconf manual
to prevent unneccesary rebuilds because of an unchanged config.h.
Uses the automake trick of generating the stamp files in the
_AC_AM_CONFIG_HEADER_HOOK macro instead of littering the source
directory with stamp-h.in files.
Add an extra ./config.status run after ./config.status --recheck
because with --recheck it doesn't actually try to remake the generated
files (and thus doesn't make the timestamp files). Thus without the
extra run, each stamp-*-h target would need to independently run
./config.status to make sure it wasn't changed by the configuration
change.
An orthogonal fix of how config.status is called in subdirectories.
When in a subdirectory and config.status is called with
../config.status and $(srcdir) is a relative path, config.status gets
confused. Fixed by replacing '../config.status --file=Makefile.in'
with 'cd ..; ./config.status --file=<dir>/Makefile.in'
Instead of calling make in subdirectories using a sh for loop, use GNU
make's $(foreach ) to create a string of commands connected with &&.
This way an error in a subdirectory will stop the build, instead of
continuing on to the next subdirectory, which the old version does.
Also added rules to regenerate configure when configure.in changes,
and to run config.status --recheck when that happens.
This patch adds code to cleanup system functions driving a
continuous assignment. It also modifies the user function
cleanup to not interfere with this. It also adds a count
of the nets and signals that were not cleaned up that is
pnly printed when running valgrind. They are not flagged
y valgrind since they are pool managed objects. There are
a few signals that need to be cleaned up and local nets
are missed so there are a lot of nets.
Even open nets have a driver for HiZ. The BUFZ is needed as something
to hang .net objects. This is another step closer to not needing the
"create_constant_node" hack in vvp/words.cc.
In the olden days, the .alias was necessary to create a net name
that is an alias to an existing net in the netlist. But now that
the .net no longer creates a node in the netlist, ALL .net objects
are aliases of a sort, so this (mis)feature gets in the way.
This patch adds cleanup code that cleans up the memory that is
allocated by the of_EXEC_UFUNC command. This knocks a few more
files off the valgrind list.
The constant $clog2() was returning a value that had an integer
width, but it did not have the sign bit set. This could result
in incorrect math expressions. This patch sets the sign bit for
the constant $clog2() result.
In the MinGW version of iverilog-vpi (C version located in driver-vpi)
we must only look at the first word of the IVERILOG_VPI_CC definition.
A recent change to the configuration process made this equal to
"gcc -std=gnu99" which will not be found when looking for the
gcc executable. We nee to look for "<path>\\bin\\gcc.exe". This
patch modifies the driver to only use the first word when looking for
the compiler, but uses the full value when compiling.
The tranif input pins are normally nothing special, but sometimes
they are fed back from the switch body. In this case, the control
needs to see the current *output* from the fed back port, in order
to get the results that people expect.
Control inputs (i.e. the control input to tranif switches)
are not driven in any way by the island, so use .import records
instead of .port records to bring them into the island. Properly
handle the now potentially different bindings within the island
and outside the island. This means the draw_net_input_x function
is a little more sophisticated, and the node data more complex.
When AC_PROG_CC_C99 was added recently we created an implicit
requirement for autoconf version 2.60. This patch makes that
implicit requirement and explicit requirement.
This is needed to get vvp to compile under MacOS 10.6 and possibly other
64 bit systems that define uint64_t as unsigned long long vs unsigned
long (both are 64 bits).
It turns out that it is possible for an otherwise constant net
mux to be non-constant if there is a force that can drive the
net. This can be detected as an l-value reference to an otherwise
constant selector.
Add a configuration check that says we would like to use C99 if the
compiler supports it. Also change the lround(), nan(), fmin() and
fmax() checks to look in the default libraries as well as the math
library.
Update the iverilog-vpi sh script to correctly quote CC since it
may now have two words (gcc -std=gnu99).
Add a missing int for main in draw_tt.c.
Local nets that have no (zero) drivers are dead weight. Since
they have no drivers, they are not being used anywhere. Since
they are local, they are not force-able.
This doesn't have any significant runtime consequence other then
to create a functor that is otherwise stable. But this does connect
to .net nodes more naturally, and gets me a step closer to banning
Cx<> labels as arguments to .net records.
Nets that are created after being put off for later processing to
allow the vvp_net to be created, need to be more carefully placed
in the correct scope.
Under some situation the optimized repeat expression can get out
of sync while it is being processed this causes the code to
reference freed memory. This happens when the repeat expression
is converted to an unsigned integer, but the repeat expression
is used in a different path. It was easier to just remove the
optimization then track down the convoluted call sequence that
was causing this and then figure out what needed to be fixed.
The repeat expression must be constant, so is likely not too
complicated so this optimization is very minor and should not
be missed.
When releasing a net, the release method must force that the
filter propagate the released value to the output. Use the
needs_init_ flag to do that force.
The vpi_callback base class is parent of the filter object of nets,
and not the functor. The good news is the clear_all_callbacks method
can now be got at without casts.
If the part select is too wide in both the top and bottom ends,
this patch fixes the calculation of the top pad. The compiler
was generating too much pad if the select also extended below
the expression.
(cherry picked from commit 2c0b105de7)
If the part select is too wide in both the top and bottom ends,
this patch fixes the calculation of the top pad. The compiler
was generating too much pad if the select also extended below
the expression.
If a signed signal is driving a part select in a CA and the width
is less than 32 bits. the value will be zero extended and will
not work for negative values. This patch adds a warning that this
could happen. This will be fixed in development.
This patch adds an optimization when a constant indexed part
select covers the entire L-value. It also fixes a few issues
in the code generator related to part selects.
When reading from thread space only read the first 32 bits
(sizeof int) for the part select base. This matches the other
parts of the PV_get_base() code.
In auto scopes, nets cannot work and probably are are artifact of
elaboration. So elide local nets in auto scopes.
Also, get net inputs from the inputs of nets. This is a step
towards eliminating the label on nets altogether.
We do not want to check an array word scope to see if the scope
was already included since a scope does not include array words.
They must be explicitly specified.
This patch fixes a problem in the .part/v select when the index is
undefined. The default value needs to be INT_MIN, so when the long
is cast to an int the value is in range.
To get better functionality in V0.9 and development until we
add a select that is sign aware to .part/v this patch uses
a 32 bit integer (int) for the select value. This allows a
normal Verilog integer to produce the correct results. A
warning for smaller signed index vectors is planned, but it
needs more input.
The first input through a net needs to be propagated, since this
is used as an initialization for the net. This patch also cleans
up wires to not need the width_ member, instead inferring the
width from the saved bit value.
Whether and what to propagate after a release of a part needs to
match the behavior of the full-vector release. Nets need to restore
their driver, and regs need to hold their forced value.
filters need to be able to cope with parts of vectors moving through
the net. It makes the most sense to handle every filter as a part-
selected filter.
&PV<> was just using vpi_get_value() when a signal was driving
the select. This incorrectly returned 0 for 'bx or 'bz. This
patch adds a check for an undefined value and returns INT_MIN
for this case.
This patch adds file and line number information to named events.
It also modifies the draw_eval_expr_wid() routine to fail with
an appropriate message for named events. This checking needs to
be pushed into the elaboration stage, but this will give a better
message than we had before.
This patch adds two new warning classes that can be enabled or
disabled via the -W command line option. The first controls
whether a warning is generated if a part select within an
always @* statement causes the entire vector to be added to
the implicit sensitivity list. The second controls whether a
warning is generated if a word select within an always @*
statement causes the entire array to be added to the implicit
sensitivity list. The first class is not automatically enabled
by -Wall, the second class is.
Now that .net nodes are references to filters into vvp_net_t objects
and are no longer functors on their own, the .alias node becomes
exactly the same as a .net itself.
When releasing a net, the release needs to propagate the driven
value. When releasing a variable, the driven value must be set
to the previously forced value.
IVL_LPM_CONCAT should use ivl_lpm_size() instead of ivl_lpm_selects.
This is a requirement in development so add a warning and make using
ivl_lpmp_selects() with a IVL_LPM_CONCAT fatal.
It was documented that a IVL_LPM_CONCAT would use _size() instead
of _selects(). This patch adds the functionality to _size() and
converts all the Icarus provided code generators to use _size().
_select() will be kept for compatibility in V0.9.
The old readline library was causing problem. I updated the mingw.txt
file to use the gnuwin32 version of readline (5.0-1) which works. I
also mentioned that I plan to rewrite the directions using a newer
version of MinGW.
This patch is a major rewrite of the indexed part selects (+: and -:).
It made the following enhancements:
1. Make indexed part selects work correctly with both big and little
endian vectors.
2. Add a warning flag that warns about constant out of bounds/or 'bx
indexed selects.
3. Moved the -: parameter code to its own routine.
4. Added support for straddling before part selects in a CA.
5. Added more assert(! number_is_unknown) statements.
6. Add warning for &PV<> select with a signed index signal that is
less than the width of an int. This will be fixed later.
7. Add support for loading a 'bx/'bz constant into a numeric register.
8. Add a number of signed value fixes to the compiler/code generator.
9. Major fix of draw_select_expr() in the code generator.
These opcodes need to return 'bx or 0.0 for the real opcode when
the array index is undefined.
The patch also documents the auto incrementing of the bit
index register done by the %load/avx.p opcode.
When a part select is driving another part select any bits outside the
original select must be 'bz instead of 'bx. If we initialize the temporary
buffer to 'bz this should work as required. It there are multiple drivers
then a resolver comes into play and this should not matter.
The %shiftr/i0 and %shiftl/i0 opcodes are used for some part
selects and if we have a negative shift we want the value to be
padded with 'bx. This patch enhances the two %shift/i0 opcodes
to work with negative shifts and for negative shifts pad with
'bx instead of 'b0.
It also fixes %ix/get/s to use a uint64_t instead of a unsigned
long to avoid problems with sign extension on 32 bit machines.
This patch adds support for a -Wselect-range warning class to the
driver and ivl programs. This is part of -Wall. The actual checks
will be added in a later patch.
When checking for name collisions, the compiler looks for genvar
declarations in the enclosing module rather than in the current
scope, which leads to false positives. The compiler also places
all genvar declarations in the enclosing module scope, even when
the declarations are inside a generate block which has its own
scope. This patch fixes both these faults. It also fixes some
typos and outdated information in comments.
There was a small memory leak in parm_to_defparam_list where space for
"key" and "value" was being allocated via strdup and never freed.
This was fixed by freeing them at each return point.
In that function, key and value were defined to be const char* but
were later mutated. gcc4.4 is more strict with const-ness in some
functions than previous versions (see
http://gcc.gnu.org/gcc-4.4/porting_to.html section "Strict
null-terminated sequence utilities"), so this caused compilation to
fail. Fixed by removing the const modifier in the declaration of
those two variables and related nkey variable. This also necessitated
malloc'ing room for value in one path through the code, which made
memory management easier as well.
Handle the case where the input to a net is a constant. Since nets
do not exist anymore as nodes in their own right, we need to create
a driver to drive a net from a constant.
Handle forward references of net inputs.
pr2827132 changed the val_ field in vvp_fun_part_sa to only store
the bit values for the selected part, not the entire source vector,
but omitted to modify the recv_vec4_pv method to handle this change.
This patch rectifies that omission.
This patch is based on one from "bruce <bruce1914@gmail.com>".
I've applied all but the elaboration code, which I rewrote to
properly work with the elaboration work queue. I also constrained
the implementation so that the parameter name must have exactly
two components: the root scope name and the parameter name. This
is necessary to keep the defparm processing sane. The comments
from bruce's original patch are as follows:
--
This patch would provide function to define parameter from command
line. This serves the same functionality as 'defparam' in Verilog
source code, but provide much more ease for using. Parameter
definition can be write in command file, with following syntax:
+parameter+<scope>.<parameter>=<val>
*Do not apply any space between them*
The scope name should be full hierachical name with root name at
the begining. The following example would override test.T1 with
new value 2'b01:
+parameter+test.T1=2'b01
'test' here is the root module name. The parameter value here
should be constant. Parameter definition can also be write in
the command line:
iverilog -Ptest.T1=2'b01
This serves the same functionality with the previous example.
If we define the same parameter in command file and command line,
the one in command line would over-write all others.
A while ago we changed how variable arrays were accessed. This change
did not get propagated to the non-blocking assignment for real array
words. This patch adds a warning that this is not currently supported.
We can add this to development, but not V0.9 (interface change).
Two small fixes: Threads should load signal values from signal_value
objects, not signal functors, and the force method should not run
its value through the filter.
This patch adds $ferror() support. This is enhanced over what the standard
says needs to be supported. All file I/O routines set/clear the errno flag,
This allows $ferror() to check when an invalid fd/MCD is passed to a
system task. The $ferror() fd is only checked if errno is not set since
all the other routines will set EBADF when they are called. This allows us
to test the output from $fopen() which sets the fd to zero (an invalid fd)
when it has a problem.
The following bugs (changes) are also fixed:
Fix $fdisplay*, $fwrite*, $fstrobe*, $fflush, $fclose to not accept 0 as
a valid MCD.
For the $fdisplay*, $fwrite* and $fstrobe tasks an invalid fd/MCD is now
a warning instead of an error like the other file I/O routines.
Modify $fputc() to be a function and return a value like $ungetc().
Modify $ungetc() to return a value like the standard dictates (-1 on
error else 0) and pass the value as a full int to get EOF as an error.
Remove some extra checks that could not happen in $fseek() and to
be safe convert the numeric codes to the system symbolic values.
Skip $fstrobe callback when the fd/MCD is closed. The standard says
we need to cancel the callback, but we currently do not have the
ability to do that so just skipping this will work for now.
Free the argument handle when $fscanf() is called with an invalid fd
(memory leak).
It's not too likely we will ever reach this, but we should be nice
and print a message instead of just failing. We could set errno,
but for now the warning will have to be enough.
Very minor issues dosify was not closing files so memory leaks could
show up and vpi/sys_readmem.c was passing the file after it was
closed to the lexor cleanup code. The lexor cleanup code does not
need an argument.
The LXT2 writer allows for splitting the output file into multiple
output files. The size of that output file was fixed, but needs to
be controlled by an environment variable.
This patch adds genvars to the elaboration process. It adds checks
that a genvar is defined for a generate loop and that a genvar does
not conflict with any other items in its name space.
Currently, edge event functors declared in automatically allocated
scopes that are used to detect edges on signals declared in static
scopes are unable to correctly determine edge information for the
first signal delta they receive because they do not know the old
state of the signal. This patch causes the state of static signals
received by these event functors to be recorded as static state in
the functors, so the old state of the signals can be initialised
to the correct value when a new automatic context is created.
Currently a part select functor will send updates to nodes connected
to its output whenever any part of its input vector changes. This
patch ensures updates are only sent when the selected part of the
input vector changes.
This patch fixes a CA to evaluate and ignore a replication of zero.
It also fixes a minor glitch in the data type calculation code. This
was causing a problem if a zero width replication was the first
element in a concatenation/replication since the data type was hard
coded to the first element of the concatenation/replication. It now
uses the first defined element in the concatenation/replication to
determine the data type.
This patch evaluates the whole concatenation expression and
makes the concatenation padding sign aware. This is needed
when $signed({...}) is passed as an argument.
A repetition is just N copies of the base expression not N
evaluations of the base expression. This is only a problem
when functions have side effects. It's also faster to copy.
The evaluation must also be done when the replication count
is zero (see 1364-2005).
When a C-style comment /* */ is being skipped because it is in a
skipped `ifdef, `ifndef, etc. directive then we need to output a
'\n' at any comment end of line.
This patch modifies the original SystemVerilog timeunit/timeprecision
patch in the following way:
Removed trailing space.
Reworked some code to use standard spacing rules.
Added some comments.
Combined some code.
Major rework of local/global timeunit/timeprecision logic.
Major rework of timeunit/timeprecision declaration/check code.
This was needed to remove the shift/reduce warnings.
Add a number of checks for invalid combinations.
Take wires out of the signals/variables and move them into a filter
instead. This is a big shift, and finally starts us on the path to
divide wires out of signals.
We want the entire force/release subsystem to only reference the
vvp_net_t or vvp_net_fil_t objects in a net. This gives us the
latitude to take wire implementations out of the vvp_net_fun classes.
Make the code smarter so it can keep fewer items in the lists.
Scopes and explicitly given variables are all that is kept.
Includes a few other refinements.
This patch adds support for dumping named events to the VCD
dumper only. The LXT and LXT2 will be added once this has
been tested more. It also reworks the $dumpvars routine
to be more consistent concerning warning messages for duplicate
signal dump requests and fixes some bugs.
For events you will get extra events at T0 and at $dumpon. I
plan to fix this, but that is much more involved.
For duplicate signal warnings. Implicit duplicates loaded
automatically from a scope will not display a warning. Only
an explicit signal request will print a warning if it was
already included. All other will be silently ignored. This
should limit the warning to only what the user cares about.
For example:
$dumpvars(0, var, scope_that_includes_var);
Will work without a warning message.
$dumpvars(0, scope_that_includes_var, var);
Will generate a warning since the var was already included
by the scope request.
Other enhancements include the start of including type
information in the output. For now integer is added, the
other type information will require changes to the code
generator and hence will only be done in development.
This was incorrectly using the expression sign not checking if
the two sub-expressions are both signed. This likely used to
work, but in the context of $signed which sets the expression
to signed so we can have a signed expression without both
sub-expressions being signed.
These methods are type specific, but the code that invokes them
get at them from pointers to filter objects, so it makes sense to
make them abstract methods of the vvp_net_fil_t class.
An implicit sensitivity list that has selects (bit, part, indexed
part or array) will include more than the user expects so print a
warning to let them know what will happen. Other simulators have
the same behavior, but I believe this is incorrect and needs to
be fixed to only include the appropriate parts. The warnings can
go when we fix this functionality, but we need them now to warn
the user that they may not be getting what they expect. One other
simulator warns for array selects.
This patch also adds the array index to the sensitivity list.
This patch fixes a number of bugs related to real variable and net
arrays. Specifically the following:
1. When iterating over (scanning) a net array start at base index 0
not index 1.
2. Don't fail when iterating over (scanning) a real variable array.
3. Run the array_word_change() routine when a real variable array
word is changed. This allows array ports and value change
callbacks to work correctly.
4. Update the array_word_change() routine to work with real variable
arrays.
5. Update the array port code to support real variable arrays.
6. find_name() needs to also iterate over net array words just like
memory array words.
7. Initialize all real array words to 0.0 when the array is created.
This patch removes some of the unneeded differences in the
various dumper routines. This is the start of a complete
refactoring, but the first task is to make them as common
as possible and this is the start of that.
When processing procedural real expressions we need to evaluate
non-real sub-expressions as bit based expressions and then
convert the result to a real value. This is particularly import
for integer division.
This patch changes the initial buffer size when displaying results
to 512 from 256. This initial buffer is used as the default for the
floating point results and failed when %f is given a large, but
valid value. To make this even more safe we add the precision to
the size to make sure we do not overflow the buffer.
This patch cleans up some unneeded code. Releases some allocated
memory before the compiler quits and fixes a couple minor memory
leaks in the compiler and vvp code generator.
Added support for the -N option, which causes $stop and ^C to behave
like $finish with an exit code of 1.
While I was at it, I noticed that the summary line in the man page for
vvp was missing a couple of options, so I fixed that.
The fd table used to be statically allocated with only 32 entries.
Three of these were preallocated for stdin, stdout and stderr
leaving only 29 for the user. This patch makes the allocation of
this table dynamic with a hard limit at 1024 total fds. The table
is increased in 32 bit chunks.
Someone got a bit too creative in reducing the original equations
I wrote to handle this. This patch reverts the previous code and
uses my original equations. This passes for both wide and narrow
vectors. The equations are slightly more complicated, but the old
z2x conversion had some overhead. I would expect the time to be
about the same, but you now get the correct results.
This patch adds code to parse and ignore the following timing checks:
$nochange 1364-1995
$skew 1364-1995
$fullskew 1364-2001
$removal 1364-2001
$timeskew 1364-2001
The other checks were already supported. These have not been tested,
but they use the same basic terms as the other checks. We can fully
test these when we actually implement them.
This patch adds -g2001-noconfig command line flag. The compiler
already supported this with `begin_keywords. Document this in
the manual page and fix a few other issues.
Fix endgenerate to be a 2001 keyword and add a few missing
keywords at the appropriate standard level e.g.(unsigned).
Add uwire and deprecate wone. wone used to just convert without
a warning to a wire. uwire will display a warning that it is
being converted to a wire without a check. wone is converted to
a uwire with a warning and then prints the uwire message. The
uwire message will be replaced with a real check fairly soon.
During macro expansion (with arguments), there is one global buffer
(exp_buf) that keeps getting reallocated to fit all the macro's text
that's currently being expanded. The problem with this scheme is that if
a macro with arguments needs to be expanded from the macro text of another
macro with arguments, it may happen that the second expansion forces
the above exp_buf buffer to be reallocated. Which is fine until the
previous macro processing resumes where (struct include_stack_t *)->str
now points to uninitialised memory. Basically, the code that can trigger
such behaviour is as follows:
`define FOO(a) (a+3)
`define BAR(b) (`FOO(b)+2)
`BAR(x)
Ofcourse, you need to get lucky to get the exp_buf to be realloced at the
right point, but it's possible.
I don't see the advantage in keeping all the expanding macro's text
together, so my solution is to simply allocate a new buffer and pass it
as (struct include_stack_t *)->str to the flex parsing function and free
it at the end.
Icarus has recognized this directive, but it did not do anything
with the information. This patch adds the functionality for most
common cases. It adds this by changing the input net type from
wire/tri to tri1 or tri0 depending on the pull. The issue is that
if the input net is not a wire or tri this is not safe and should
really be done as an external pull gate connected to the input.
We will need to handle this is it ever comes up. For now a sorry
message is printed.
Previously Icarus only supported a default net type of wire or none.
This patch adds the rest of the supported net types (all except
uwire and trireg) to the `default_nettype directive. It also fixes
make_implicit_net_() to use the default_nettype instead of always
using implicit (the same as wire).
This patch reworks the `timescale directive to do a better
job of parsing the line, it refactors some of the code and
should produce better error messages. It also tightens up
parsing the numeric constant, etc. to better match the
Verilog standard.
The parsing of `line has been enhanced to only allow 0, 1 or
2 for the level and a single line comment at the end of the
line is ignored.
The vvp_fun_force node converts its input to a call to the
force method of the target node. This eliminates the need for
linking a net to a force input of a signal.
The vvp_net_t port 2 was used to implement force behavior, but that
is no longer how we plan to implement force, so remove it from the
implementation of signal nodes. This currently breaks much of the
force/release functionality, but we'll get it back by other means.
This patch adds support for the `resetall directive.
It also changes `celldefine, `endcelldefine and `resetall
to no longer grab text following them. These directives do
not take an argument so they should not be grabbing any
text and silently discarding it.
The `timescale processing was reworked to handle being
reset and hooks were added to easily change the default
time units and precision when we add that feature request.
This patch adds real functionality for `celldefine and pushes this
property to the run time which can access this with vpiCellInstance.
This is technically only available for a module, but all scopes
have the property and only modules should return true when the
'endmodule' is between a `celldefine and `endcelldefine directive.
These are not leaks in the true sense of the word, but it is
memory that is not being freed before the program finishes
so valgrind will complain about this.
It looks pretty stupid and non-c++-y, but it does remove two compiler warnings
vvp/stop.cc: In function 'void stop_handler(int)':
vvp/stop.cc:492: warning: deprecated conversion from string constant to 'char*'
vvp/stop.cc:493: warning: deprecated conversion from string constant to 'char*'
The wire base class cannot carry all the overhead for handling all
the different net types, so split it out into derived classes. This
will also move me closer to splitting wires away from variables.
This patch modifies the real parameter get_value routine to use
the standard vpip_real_get_value() routine. This routine has
support for an integer and a decimal string value.
The standard allows an output declared as "output reg" to be
given an initialization assignment in the output declaration.
this patch adds that functionality. Specifically:
output reg out = 1'b0;
works as expected.
Icarus support returning a string version of a macro ``<MACRO>.
The problem was that it did not escape '\' or '"' so if the
macro to be escaped had either of these it would create an
invalid string. This patch fixes this by translating these two
codes to their octal equivalent when the macro is converted.
This patch fixes the three %assign/v0/x1 operators to correctly
notice that the select has fallen off the start of the vector
for the case that the negative offset equaled the width.
There is no use implementing the release and deassign methods as
port commands. It's confusing and a waste of vvp_net_t functionality.
It also obscures what needs to be done to more force/release into
the filter object.
This is moving towards moving force/release out of the signal
class. The end-game is to remove all of the wire implementation
out of the functor and into the filter. Variables will remain in
the functor.
When dumping an array word the name is implicitly converted to
an escaped identifier. If this implicit name conflicts with an
explicitly created escaped identifier this patch will print a
warning message warning that the array word will conflict with
an escaped identifier.
Move the vvp_vpi_callback to the vvp_net_sig.h header file, and
collapse some useless hierarchy. (Specifically, all callbackable
items are also wordable.)
Move the run_vpi_callback invocation for wires/variables from the
output generator to the newly implemented filter object. This is
starting to get the filter class working.
This patch adds code to automatically dump the output stream
including any dump file when entering interactive mode. When
the user typed ^C or $stop was executed.
Dumping array words is an enhancement that we have added to Icarus.
The problem was that if you wanted to dump the whole array you would
like to use a for loop as follows:
for (lp = 0; lp < max ; lp = lp + 1) $dumpvars(0, array[lp]);
This used to work, but some of the VPI rework broke it because it
counted on the word select to be constant. This patch restores the
functionality by converting the variable word select into a constant
word select in the calltf routine. This is done without warning and
only for the $dumpvars() routine.
Adding this functionality necessitated adding support for vpiIndex
to the &A<> routines.
In 1364-2005 it is an explicit error to take the select of a scalar
or real value. We added the checks for real a while ago. This patch
adds the functionality for scalar values. In the future we may want
to push the scalar property to the run time.
This patch add code to print a warning message if it finds both a
default and `timescale based delays. The -Wall or more specifically
the -Wtimescale flag can be used to find the module with the missing
`timescale directive.
This patch adds interactive support for $stop and $finish.
$stop displays a message that the simulator is already stopped.
$finish acts exactly like (calls) the interactive "finish"
command. Having $stop do nothing and $finish not finish until
you exit interactive mode is not very intuitive.
This patch adds better error messages (compiletf) for the optional
system tasks and functions (Annex C 1364-2005). Doing this also
makes calling them fail more gracefully (it is no longer a RE).
This patch add a new system function $readmempath. It accepts
a ":" separated list of directories that $readmem{b,h} will
use when trying to open a given file. If the file given to
$readmem{b,h} starts with a '/' (an absolute path) the search
list will not be used. A new call to $readmempath will replace
the previous search list with the given list. The search list
elements are check to see if they exist and are directories.
If not a warning will be displayed and they will not be added
to the list.
the vvp_net.h header file is getting pretty huge. This divides
the obviously separable signal functor code out into its own
header and source files.
Also, fill out the use of the filter member of the vvp_net_t
object. Test the output of the vvp_net_t against the filter.
This patch adds support for recursive module loops if the
loop contains a generate block. The assumption is that the
user is doing the right thing in the generate block to make
the loop terminate. For this case there is also a check
that limits the number of loops (default 10). This prevents
the system from crashing when the user did not correctly
terminate the looping structure. The limit can be changed
by the user if needed.
When adding history (add_history) use both the existence of the
library and the header file to determine if history can be
supported. Add a new USE_HISTORY that is the and of these two.
Only sign extend the operands for division or modulus if
both of them are signed. Previously only the individual
operand signedness was being considered.
The standard does not allow this, but it appears that other
simulators do. This patch adds the functionality, but prints
a warning message for the invalid task definition.
The out pointer of a vvp_net_t object is going to be a bit more
sophisticated when we redo the handling of net signals. Take a step
towards this rework by making the pointer private and implementing
methods needed to access it.
This patch fixes the code generator to correctly create three value
constant delays. It also fixes a bug in the compiler related to the
precalculation of the high-Z delay when only two delays are given.
Previously if was using a pointer not a value comparison to find
the minimum value.
Variable delays should work when one or three values are given.
For the two value case we need to do a comparison at run time and
that will require changing the compiler/run time interface so that
can only go into the V0.10 branch. This patch can be applied to
both development and V0.9. I have added a sorry message and an
assert for this case. I will add the variable two delay case at a
later time. We also do not support mixing constant and variable
delays on a single statement. That is a much bigger change and
can wait until someone asks for it.
When a PGAssign is driven by (r-value) a bit, part or indexed
select and the strength is not the default (supply). Then
we need to create a driver (BUFZ) to convey the strength
information.
When displaying a verireal constant value force the display
of the decimal point and trailing zeros. This prevents 2.0,
etc. from being display as "2". which can be confused with
decimal two.
The previous code looked for more than one array word to determine
if the given signal was an array or not. The problem with this is
that a single word memory was considered a signal. This is fixed
here by looking for an array_dimension to be greater than zero.
This patch fixes the following problems in the right shift code.
The >>> result is only signed if the l-arg is also signed.
The r-arg is always unsigned.
Only sign extend the l-arg when the >>> operator is used.
This relates to an optimization for certain constant shifts.
Removed some obsoleted/outdated code.
When the VAMS math functions were originally built we did a
straight copy of the log() function to $log(). This can
conflict with other Verilog-D definitions of $log. We
need to deprecate this function and remove it before the
next major release.
This patch adds the $fread() system function. Icarus does not
currently allow missing arguments in functions so the following
standard specified functionality is not supported:
res = $fread(mem, fd,,count);
It also fixes a memory leak in fopen related to the get_filename
refactoring I recently did.
(cherry picked from commit 036c176e8b)
This patch adds support for virtualized register arrays to the
tgt-stub back end.
Based Cary's patch, but with a slightly different style.
Both work fine.
This was cherry-picked from the v0_9_1 branch commit:
"Get ready for the 0.9 first release"
and modified to reflect that this is now the new devel branch
headed for the future 0.10 release.
To get the correct print format for a 64 bit value it is much
better to use <inttypes.h> (when available) than building our
own value. This allows MinGW to use the non-standard I64.
(cherry picked from commit d237e35076)
It is valid to have a repetition of zero inside a concatenation
that has other elements with a defined width. This patch adds
this functionality to the synthesize method. It also prints
an error if you try to synthesize a zero width constant.
The Multiword division was not handling some degenerate high
guesses for the intermediate division result guess. The end result
was an assertion. Recover from this case.
(Does the addinb back of bp need to be optimized better?)
The arithmetic operands are signed only if both operands are signed.
If the expression is unsigned, then the expression as a whole needs
to be processed as unsigned in order to get padding right.
When a pin array is virtual, dll_target::signal() doesn't need
to make a corresponding set of stub nexa.
This patch includes new detection of oversized arrays, configurable
with the ARRAY_SIZE_LIMIT flag. This limit only applies to devirtualized
arrays; virtual arrays are only limited by your architecture's
unsigned int type.
The concept and earlier versions of this patch have been successfully
stress-tested by multiple people. This one causes no testsuite
regressions on my machine.
Closes: pr2023076
Reduces resource usage when compiling large memories.
Normal usage patterns still create large nexus arrays
in t-dll.cc:dll_target::signal().
This patch is extensively tested; it shouldn't break anything.
The existing debug "optimizer" flag is (ab)used to control
message printing when large (>1000 element) arrays are
devirtualized or nexus-ized.
The new global variable disable_virtual_pins is available
to force allocation of Pin arrays when they are declared,
but no user interface is provided.
See extensive discussion on iverilog-devel, March 4-5 2009,
title "pr2023076: large memories".
Limit memory sizes to whatever fits in unsigned; crash if
the conversion from unsigned long to unsigned overflows,
instead of just wrapping. I don't know what happens on
a 32-bit machine if you ask for an 8 Gig memory, but with
a 64-bit machine and this patch, it crashes with an assert.
Set direction on PartSelect Links before connecting them.
May or may not be considered orthogonal to upcoming
memory virtualization patches.
This patch adds messages in various places to warn that constant
user functions are not supported. It uses a global variable to
indicate when we are in a constant context. This is a bit of a
kludge, but works well without needing to change a bunch of code.
It is interesting to note that ports are elaborated late enough
that if we had the constant function evaluation code they would
evaluate correctly. This also applies to the function return
range, the concatenation repeat, specparams and initial values.
Signal definitions are early enough that elaboration is what is
failing because the function body is not available (has not been
elaborated). The same thing applies to both parameters and
localparms.
This patch adds compiletf routines for the $sscanf/$fscanf
functions. It does not enhance the conversion routines it
only adds better error/warning messages.
It also removed the redundant IS_MCD in some of the fileio
calltf routines. This is already checked in vpi_get_file().
I also added the vpiNetArray type to allow us to distinguish
arrays of nets from other arrays (memories). Much more is
needed here, but this solved the problem of the day. The
problem was that we needed to make sure we could assign to
the word of a variable array, but not the word of a net array.
It's actually probably not needed since Icarus converts the
net array word reference to just the net, but I thought it
prudent to make sure things didn't slip by.
This patch adds compiletf routines for the mti random functions
and adds a common routine to check for extra arguments. It also
adds file and line information to the rest of the compiletf
routines that were missing them.
This patch adds compilef routines for the readmemb/h and
writememb/h system tasks. It also fixes some errors related
to arrays with negative range values. You can not specify a
negative address in the file, but arrays with negative range
values or negative start/finish argument to the tasks are
supported. It also generates an error when reading invalid
character from the input file.
A significant amount of the code is common between the two
styles of tasks so this has been grouped into common
routines.
It also adds a common routine for getting a string that will
be used as a file name. This routine is used by any task
that requires a file name value. If a filename has a
non-printable character it will be displayed as a \octal
constant to show what the character is.
Updates the dumping routines to match each other better,
improves some error messages and fixes a bug in the LXT2
dumper when dumping greater than 32 bit delays.
If the builder wants to build the package with an install suffix,
the %{suff} variable makes that easy. Just define that value as
needed, and there you go.
The dependency file may be written by ivlpp as it loads its own
dependencies. Make sure this doesn't mess up the dependencies that
are already written by the main program. This requires that ivl,
ivlpp and iverilog (driver) cooperate on the opening of the
dependency file.
This is mostly a minor definition change in the parsing of literal
numbers by the vvp lexor. Allow for 64bit numbers in the .delay
records, and have the code generator also able to cope with the
situation.
Icarus Verilog internally is not white-space clean. We need to make
sure the configured paths that cause the most trouble are clean and
usable. It is still possible to mess things up downstream, but at least
this should help.
Previously Icarus normalized the results so array [7:0] would
be the same as array [0:7]. This works just fine for
simulation, but the VPI calls can select the left or right
value and this was incorrect for the [7:0] case since it was
being normalized to [0:7]. This patch swaps the two values in
the a.out file and from this creates the previous first/last
values and a new flag that can be used to get the correct
left and right values for the VPI interface.
Allows iverilog to parse attribute like syntax that a common
simuator puts into automatically generated verilog code. This
syntax cannot be found in any of the IEEE standards.
Wires are not allowed as l-values of procedural assignments, even if
the wire is an array. Fix the checker to detect this case event when
the l-value is an array.
It is possible for an identifier to have multiple index expressions.
(For example, a part select of a memory word.) Make sure all the
index expressions are probed for width and type.
And also, note that the unary ! returns BOOL or LOGIC, not just
the type of its operand. It is slightly different from the other
unary operators in that way.
The test_width for repeat-concatenations is tricky because it
requires the evaluated value for the repeat expression. It should
be OK to call elab_and_eval on that expression even during the
test_width for the containing expression. We'll see.
This patch adds support for 64 bit non-blocking delays in procedural
code. We fixed the procedural delay operator (blocking delays) earlier.
This patch mostly mimics what was done there. The continuous assignment
delay operator still needs to be fixed.
This patch adds logical support for real values (!, && and ||). It
also prints an appropriate error message when a real value is
incorrectly given to an operator that does not allow real arguments
(bit-wise, reduction, shift and repeat/concatenation).
Two bugs:
(1) propagating values through the branch accidentally also
did a part select.
(2) Not all nodes of the branch nexus didn't receive a calculated
values, even though they were all marked as done.
In the process, I cleaned up the code a bit, and documented it for
better understanding.
This patch adds support for the other edges 01, 10, etc. These still
need to be verified in the context of IOPATHs, but they are ignored
in the timing checks and that's what was needed.
This patch updates the compiletf for $sdf_annotate() to better
check the arguments and to display the file and line location
when an error/warning does occur. It does the same for the
calltf messages. It also fixes a couple of subtle bugs.
First we need to look for a NULL string not a NULL value. The
result buffer should always be defined so will never be NULL.
Next if a scope has no modules we should return like the module
was not found (return 0) vs asserting.
In the past we automatically added the local directory to
the beginning of the include search path. This was found to
conflict with what other tools do so this functionality is
now only available when the -grelative-include option is
given to iverilog.
The code was using vpi_free_object() to free a vpiCallback
object and that was creating a memory leak since this is a
do nothing routine. You need to explicitly use delete.
The newer mkinstalldirs can handle paths that have spaces in them.
While I'm at it, I also updated the Makefiles so that installation
can also work to DESTDIR directories that have spaces.
When cleaning up the &A<> and &PV<> we need to check if the handle
argument is a nested call to another &A<> or &PV<> if it is then
we need to also delete that construct.
We also need to cleanup the vcd_info information list.
This patch adds code to generate process-local variables
for scopes of type IVL_SCT_BLOCK. This also handles using
the correct assignment operator (:=) for the local VHDL
variables.
This patch adds code to free most of the memory when vvp
finishes. It also adds valgrind hooks to manage the various
memory pools. The functionality is enabled by passing
--with-valgrind to configure. It requires that the
valgrind/memcheck.h header from a recent version of
valgrind be available. It check for the existence of this
file, but not that it is new enough (version 3.1.3 is known
to not work and version 3.4.0 is known to work).
You can still use valgrind when this option is not given,
but you will have memory that is not released and the
memory pools show as a single block.
With this vvp is 100% clean for many of the tests in the
test suite. There are still a few things that need to be
cleaned up, but it should be much easier to find any real
leaks now.
Enabling this causes a negligible increase in run time and
memory. The memory could be a problem for very large
simulations. The increase in run time is only noticeable on
very short simulations where it should not matter.
elaborate.cc:2456: warning: suggest parentheses around comparison in operand of &
vpi/vcd_priv.c:210: warning: operation on 'idx' may be undefined
Probable behavior change. Passes testsuite.
This patch cleans up the V-2005 and V-analog math functions to
free their allocated memory at the end of simulation. It also
modifies the veriusertfs code to do the same thing.
It also closes the VCD file at EOS.
This avoids generating invalid VHDL signal names in the
following cases:
- The name begins or ends with an underscore
- The name contains two consecutive underscores
- The name is the same as a component declaration
- The name differs from another only in case
This fixes a bug where temporary variables could be declared
more than once.
It also takes out a debugging print statement I accidentally
left in the last patch.
I forgot to modify the LPM generating code with the
last patch. This *should* now always ensure a signal
is readable before code is generated to read from it.
This patch corrects several bugs with the generation of
VHDL `buffer' ports. The code generator should now
generate a buffer only if the port needs to be read inside
the architecture, otherwise it will stay `out'.
This also correct a bug where an output port is connected
directly to the output of an instantiated component. Generating
`buffer's would work here, but a more idiomatic VHDL approach is
to declare an intermediate signal which both outputs are connected
to. This is implemented in the patch (fixes the regression of
readout.v in the testsuite).
If an &A() operator contains a label for an array that has not
yet been declared, vvp fails with an assertion error. This
patch delays the calls to array_find() in the functions that
compile &A() operators, using the usual resolve list mechanism.
Noticed this as part of the test case for pr2516774b. Under some
circumstances the input arguments would be cast to the wrong type.
This patch ensures that all the arguments have the correct type.
This patch changes the output of VHDL unsigned bit strings
which are 4, 8, 16, 32, or 64 bits to use VHDL hex string
constants.
So the following:
"00000001"
Becomes
X"01"
Which is much easier to read
This is a fix for pr2527366 where draw_nexus would sometimes
generate code to drive an input from in an input (where they
should have been left unconnected)
The patch for pr2516774 exposed a bug which caused
always3.1.8A to fail. This patch corrects that.
The test to decide when to use a sensitivity list
rather than an explicit wait statement wasn't tight enough.
This patch is a fix for pr2516774.
The idea is to generate a local variable inside
a function whenever an argument is assigned to. The
variable has an initial value of the argument value
and is used in its place for the remainder of the
function. This patch also handles the case where the
argument is assigned to inside a while loop.
Previously the VHDL code generator managed memory for
the AST objects by requiring that each AST element be
responsible for deleting its children. The disadvantages
of this are that it's quite easy to accidentally leak
memory by forgetting to delete a child, and no AST pointers
may be shared by multiple parents (or we'd end up with
double-deletes) -- this results in unnecessary copies of
objects being made.
There's no real need for fine-grained memory management of
AST objects since once they're allocated they tend to
persist until the code generator is about to terminate, when
they should all be freed.
This patch provides a custom new/delete operator for
vhdl_element which logs the vhdl_element objects allocated
in a std::vector (after calling the default operator new).
Once the code generator is finished a single free_all_objects
call deletes all the AST objects in one go. The custom delete
operator is required so that we can still explicitly deallocate
vhdl_element objects before the code generator completes.
There are also some allocation statistics printed at the end
when -pdebug=1 is specified.
This patch fixes some issues in the previous patch. Specifically
I need to use vpi_mcd_printf and some trickery was needed to
prevent the compiler from complaining about the format string.
Most named objects should have a vpiModule handle to get a handle
to the enclosing module. This patch adds code to get this for all
the elements that I could find that needed it.
It also adds a three more names to vpi_get_str(vpiType, ...) and
fixes a problem in the vpiLeftRange for PV signals.
For most cases just using the value of a parameter is fine, but
a vpi call can access more than the value so we want to use a
parameter reference instead of the value for vpi calls.
Strings were working correctly, integer values need some minor
code generator changes and real values needed to be pushed from
elaboration to the code generators. I also changed the default
real value comment from %g to %#g so that it is more obvious
that the value is a real value.
This completes the transition to the new string based formatting.
All the tasks now use the string formatting routines. Better
compile time checking and better messages were also added.
Also a couple of types were added to vpi_get_str(vpiType, ...)
and the calculation for vpiConstantSelect was fixed for both
the &A<> and &PV<> constructs. If the value is a plain variable
or if it is calculated in thread space we assume it is not a
constant. This may not be true because of limitations/bugs in
the compiler (constant user functions are one known problem).
Certain paths through vpi_put_value cause a vpip_put_value_event to
be created with no path for deleting in. Add the capability in the
schedule_generic method, so that it can be delete as soon as it is
executed.
This patch modifies $strobe and $fstrobe to use the string
formatting routines. It also combines the $display/$write
and $fdisplay/$fwrite routines into one and removes the
old routines that are no longer needed.
This patch fixes vvp to use the standard static result buffer
when returning the vector value of a constant string. The
previous calloc method was creating a memory leak.
With this small patch, building succeeds with Debian's current gcc-snapshot,
gcc (Debian 20090107-1) 4.4.0 20090107 (experimental) [trunk revision 143170]
That build shows no regressions in the test suite. The patch does not
break building, or show test suite regressions, with gcc-4.3.
That new gcc version still emits a pile of new and arguably bogus warnings
"dereferencing pointer '<anonymous>' does break strict-aliasing rules" for
elaborate.cc:3422
StringHeap.h:31
vvp/vvp_net.h:687 (really vvp/vvp_net.h:825)
This patch fixes some more memory leaks in vvp. Mostly related
to UDP compilation and one in find_scope() that was found when
testing the VPI code. The leak in ivlpp was that the define
temporary buffer not being freed when the lexor was finished.
This patch fixes a bunch of memory leaks in vvp and converts the
T_STRING lexical token to be new based. There are still two
known leaks that I need to find a way to fix and likely some
unknown leaks that still need to be found and fixed.
When doing right shift of unsized expressions, pad the left operand
so that the right shift does not lose. This better accounts for the
lossless expectations of unsized arguments.
Seemingly does nothing, just refactors to create two new methods:
bool NetPins::is_linked(void)
void NetNet::initialize_value_and_dir(verinum::V init_value, Link::DIR dir)
and rearranges netlist.h.
This patch causes no regression in the testsuite.
It smooths the way for any attempt to address pr2023076.
This patch makes the $fdisplay() and $fwrite() family of task
use the string formatting code. It also adds a compiletf routine
for the tasks and a run time check that the FD or MCD is correct.
If not it fails instead of just dropping the output.
It also cleans up a couple of memory leaks and adds no argument
compiletf routines for the $monitoron/$monitoroff tasks.
Verireal had hooks for this, but had an assert(0). This patch
replaces the assert(0) with assert(gn_icarus_misc_flag) and
then used fmod() to calculate the modulus. It is the callers
responsibility to verify and report a message to the user
if the current state should not support real modulus.
The STRING lexical token was malloc based, but then was passed
to routines that are expecting a new based result. This patch
standardizes on a new/delete based approach.
This patch fixes some technically benign problems found by valgrind,
but we may as well give the values a default to make sure things
work correctly. I believe that the default I choose is the
appropriate value for the context.
The other problem is that real valued (local)parameters should be
printed as a real value like a real variable, etc. Trying to
do this as a decimal with the string formatting was causing a
memory problem. I could have fixed the routine to handle this,
but the better solution was to just display things the right way.
By not creating Nexus objects until necessary, we avoid creating a
lot of spurious objects. In fact, it is true that almost every
link that is created and connected to another link will create a
spurious Nexus object without this patch.
This patch generates VHDL sensitivity lists for sequential
as well as combinatorial processes which do not contain
a wait statement. Otherwise it falls back on the original
wait-on/until behaviour.
This should make the generated VHDL more acceptable to
synthesisers.
This patch generates a sensitivity list for combinatorial
VHDL processes if they don't contain a wait statement, and
a wait-on statement if they do contain another wait statement.
This should help synthesisers correctly identifier
level-sensitive latches.
In particular this improves the code generated for flip-flops
so the output can be synthesised with certain tools (e.g. Synopsis).
See the comments above draw_synthesisable_wait for more details.
This patch does a number of things.
It adds file and line number information to the strobe_cb_info
structure. This allows the $swrite and $sformat calls to reference
their location in warning/error messages.
Their compiletf and calltf routines also display file and line
number information in messages.
The $display routine was converted to use the string formatting
routine. This can be reverted by defining USE_OLD_DISPLAY. The
old code will be removed once there has been more testing.
A number of bugs were fixed that were discovered with the
$display code.
The output of some conversions, variables and system functions
were changed to match the original display code or to better
match expectation.
Leading zero support was added to the %b/%b, %o/%O, %h/%H, %x/%X,
%c/%C and %d/%D. The floating point conversions already supported
adding a leading zero.
This is the start of converting all the various display tasks to use
the string formatting code and a cleanup/update of the sys_display.c
file in general.
Rather then spread VERSION= defines throughout all the makefiles, put
the base version in version_base.in. Use that to generate a version.h
that includes the base version as well as the detailed version.
Part selects need to be fully defined. If not, then the resulting
expression is 'bx no matter what. The same for bit selects, when
the bit select expression is constant.
This reverts commit 31d67fcd3e.
The concensus has been that this causes too many build problems in
the general case and what is needed instead is a way to turn on the
extra warnings for developers only.
CFLAGS has the appropriate -W flags defined while CXXFLAGS is
just the default. The script iverilog-vpi uses CXXFLAGS because
it is defined in the Makefile to have the -W flags. This
directory is C based so does not define CXXFLAGS.
Add code to check for a plain delay statement (just a delay).
When one is found generate a null statement and do not add it
(the null statement) to result.
Functions that appear in continuous assignment expressions and that
have hidden dependencies or side effects need to be re-evaluated
whenever any input to the expression changes. This patch adds support
in the compiler and vvp runtime to enable this. This is currently
activated for any system function call that has no arguments. The
user may also force it to be used for any user function by passing
the option -gstrict-ca-eval to the compiler driver.
This patch also removes the -dautomatic option which was used for
gaining confidence in the code that supports automatic tasks and
functions. It is believed that the testsuite provides reasonable
fault coverage, and further tests can be added if bugs are found.
The code base is almost shadow-free now, so this won't add much noise to the compiles.
Problems I know about:
lxt{,2}_write.c: patch sent upstream
cflexor.c: exposes gray area of name space boundary
Finish cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. No regressions in the test suite.
This is the end of the simple, coordination-free patches.
The remaining shadows are special cases that will need extra attention.
When the parameter up index was being reworked someone mistakenly
used the pointer value instead of the actual value in the MSB/LSB
comparison. This obviously could give incorrect results.
This fixes up the elaboration of binary expressions found in
parameter expressions. Parameter expressions are special because
they elaborate early, before all the other parameters are necessarily
completed.
Having our users manually edit their .git/info/exclude is
tedious and this information belongs in the code repository.
So this patch creates a file .gitignore that contains the
appropriate information to exclude all the normal files
that should never be tracked in git..
The Makefile.in was incorrectly changed and this broke compilation
on MinGW. This patch basically reverts the previous changes and
uses a few more $(srcdir) paths.
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. No regressions in test suite.
This patch set covers C code, with the notable exception of
vpi/lxt_write{,2}.c.
Previously only the X/Z state of the label expression was
considered to be a don't care. This patch adds that
functionality to the conditional expression as well.
This patch cleans up the Makefile.in files.
We only need to delete config.log in the lower directories.
We reference the *.in files at $(srcdir)/
We need to make distclean for the tgt-(fpga,pal,verilog) directories.
This is to cleanup the Makefile.
Add some missing "rm -r f dep"
I know we are not currently using this, but configure is building
the Makefile so it would be best if it didn't complain. This patch
adds a datarootdir target and fixes the Makefile and distclean
targets.
cadpli will not compile correctly unless it knows which DL
interface to use. This patch makes it include config.h to get
this definition. It also cleans up the Makefile.in.
This patch adds support for concatenation/repetition, signals and
part and bit select of signals for casez/x expression labels.
These along with the original constants can be mixed in almost any
order. Only constant selects are currently supported.
Specifying -pdepth=N only outputs entities that correspond
to Verilog modules found at depth < N in the hierarchy.
Setting -pdepth=0 (the default) outputs all entities.
This is for feature request 2391457
Collapse all the configure checks to a single configure script in
the root of the source tree. This makes the configure process run
a lot faster, expecially on Windows systems that are slower in general.
It is recommended that AC_CYGWIN not be used and under MinGW
the previous test was complaining about multiple calls to
AC_CANONICAL_HOST. The new test performs the same function
and also displays the MinGW status if we are compiling on
windows.
Also removed a AX_CCP_IDENT call in the vpi directory and
tgt-null is built by the top configure so there is no need
to try to run configure in that directory.
A native MinGW compile was not setting these to the correct
value. This patch makes them match what Cygwin uses. Adding
the -Wl,--enable-auto-image-base should make vvp load
slightly faster since it loads multiple DLL files.
This patch fixes the crash in MinGW make distclean. The problem
was that vpi/ and driver-vpi/ were being called twice and the
MinGW make was failing on the second call since the Makefile
was already removed.
Add a dependency on config.h and _pli_types.h in the make all
target. It is likely that only _pli_types.h was needed, but
this makes it clear that they need to be rebuilt if the .in
files change.
The lower directories that depend on the top level config.status
now have a target to rebuild the local Makefile file it the
corresponding Makefile.in changes.
We were not checking the return of the two system calls used
to get the version information from ivlpp and ivl. This patch
adds checks and prints an appropriate message if they fail.
This patch optimises away straight line sequences like:
wait for 0 ns;
wait for X ns;
to:
wait for X ns;
This tidies up the output a bit.
It also has the effect of removing all code from initial
processes where the assignments have been extracted as
VHDL signal intialisers. (c.f. pr2391337)
This prints out an error message rather than crashing out with
an assertion failure when a function assigns to a non-local
variable, which cannot be done in VHDL.
This changes the assignment statement generator so that
each VHDL declaration "knows" which type of assignment
statement can/should be used on (i.e. signals must be
assigned with <=). This will help us catch cases when
we try to use, for example, := with signals. This occurs
in pr2362211 where we try to assign to a signal within
a function (where only := can be used).
If a module's input was connected to a nexus that contained
a constant driver. That constant would be incorrectly generated
as an assignment to the input *inside* the child module (instead
of an assignment inside the instantiating module).
Remove the #ident and $Log$ strings from all the header files and
almost all of the C/C++ source files. I think it is better to get
this done all at once, then to wait for each of the files to be
touched and edited in unrelated patches.
With this small patch, building succeeds with Debian's current gcc-snapshot,
gcc (Debian 20081130-1) 4.4.0 20081130 (experimental) [trunk revision 142292]
That gcc also warns about the remaining #idents in
vvp/concat.cc
vvp/dff.h
The resulting build shows some regressions in the test suite, that
I am still investigating. The patch does not break building, or show
test suite regressions, with gcc-4.3.
This patch fixes fully out of range constant indexed part selects
to just return 'bx. It also adds support for constant undefined
base values which also just return 'bx.
A bug in the bit width calculation when building an unsized, signed
negative integer value was also fixed (-3 needs 3 bits not 2, etc.)
This patch adds the function definitions for ivl_expr_branch and
ivl_expr_nature to the ivl.def file. This is needed to get Cygwin
and MinGW to compile correctly.
Probe the widths of the case statement expressions. The expressions
are self-determined in that context, but the probe is needed to
setup the expression types.
Tran islands are a kinds of island, so seperate the tran handling
from the core island concept. This will allow for creating new
kinds of islands. (Think analog.)
The expressions of a contribution statement are real valued by
definition, but we need to do the width probing anyhow in order
to resolve types and the widths of subexpressions.
The power (**) and shift operators are different from other binary
operators because their expression width calculations rely only on
their left operand, with their right operand self-determined. Get
the handling of these operators out of the PEBinary base class to
prevent confusion.
The power operator is different in that it uses the signed version
if either of it's arguments are signed. This patch fixes the code
generator to do this correctly.
This patch adds the procedural power function %pow/s for signed
values. This has bit based inputs and outputs, but uses the double
pow() function to calculate the value.
This test was way to picky about the widths of the arguments. In real
tests, the arguments may have different widths. This especially matter
when comparing unsized values.
Verilog generate schemes support a special case where conditional
generate schemes that contain only a nested conditional generate
scheme do not create a new scope. Instead, it relies on the nested
generate scheme to generate the scope.
unary expressions that have problems should not assert in the
test_width method. Instead, let the error propagate back and be
handled during expression elaboration. This found a few places
where expression widths/types weren't probed before elaboration.
Signals of width 1 are declared in VHDL as std_logic, as this
is the usual way to represent them. Unfortunately, we cannot
distinguish between
reg [0:0] a;
and
reg a;
This patch avoids trying to slice a std_logic so a[0] is equivalent to a.
This patch removes the CVS ident information from the Makefile.in
files it also puts in the current version 0.9.devel for the default
VERSION definition. This is normally passed down, but a local make
will use the value from the local Makefile. This will eventually be
replaced with a file based version to give us just one place to
reliably modify the version.
Move the header files from includedir/verilog to .../iverilog
because the verilog name is a little too generic. The iverilog-vpi
command should handle the changes.
This patch makes the code generator put the compiler version
information in the vvp output file. It also adds checks in vvp
to verify that this version is compatible with the run time.
I am assuming that a base release 0.9.0, etc. will have a
blank VERSION_TAG. Any change relative to the release will have
a VERSION_TAG.
The disciplines are, from the perspective of the ivl target, collected
into the design. Add functions for the target to scan the disciplines
in the design.
In the process, also clean up the handlng of design constants.
It is ot uncommon for the arguments to logical or to leave stuff
in bit registers 4-7. Allow the lor itself to take advantage of
that to save some %mov instructions.
When padding expressions, pre-allocate the target space and calculate
the sub-expression directly into the target. Then pad from there. This
saves a move into the result space.
This patch adds a -V flag to the runtime to print version information.
It also updates the manual page to document this and makes some minor
changes to the iverilog an iverilog-vpi manual pages.
Users expect that vpi_put_value() will keep a copy of the string
that is passed to it. This patch implements this buy copying the
string and then freeing it after the actual put_value call.
In some cases, it was possible for the NetEConcat expression to
lose track of the repeat expression, causing the output result to
have a broken concatenation expression.
This also adds some internal checks that the concatenation widths
add up properly.
This patch updates the GNU address in the -V output, adds the
VERSION_TAG info to the tgt-vvp back end and adds the whole -V
hook to the tgt-vhdl back end.
When padding a signal or when creating a local signal the file and
line information should be related to where the new object was
created not the signal value it is being created from.
This patch modifies the NetE* pad_to_width() routines to take a
LineInfo object to set the location to the correct value.
It fixes some set_line() calls to use the correct location.
It fixes ports to not set the file/line information if it is
already defined. Doing this was causing the definition of
signals to become the instantiation instead of the real
module declaration.
Named blocks create scopes, and generated named blocks' scopes can
have signals declared in them. So the elaborate_sig for the generate
scheme needs to call the elaborate_sig for the processes as well as
the obvious gates and tasks/functions.
Fix for pr2224949
The compiler generates a concatenation LPM to zero-pad ports when the
signal widths don't match up. However, when the VHDL generator generated
the input signals to this LPM it incorrectly sized them to be the width
of the result.
The VHDL converter erroneously treated a casez and casex exactly
the same. In reality a casez compares a 'x' value (it is not a
don't care). It also adds support for a full don't care case by
just returning True for the condition.
When the parser detects a signal type conflict, print a more useful
error message. In the process, be more careful with what line number
is actually attributed to the declaration.
In a procedural single bit non-negated reduction (&, | or ^)
we need to translate a 1'bz to a 1'bx. The easiest way to do
that is with two %inv opcodes. This patch modifies the code
generator to do this for this very special case.
This configure option causes the installed commands to have
a suffix string that makes them distinct from other versions
that also have a suffix string. This allows for multiple
installed versions of Icarus Verilog.
Also, move installed C/C++ header files into a subdirectory of
their own under the target include directory, to make clearer
the purpose and source of those files.
Eliminate three "warning: suggest parentheses around assignment used as truth value"
Obviously not needed, but it's easier to add the superfluous parentheses
than remember that these warnings are benign.
If one of the arguments of a comparison expression has a real value, then
the expression with is 1 no matter the width of the other argument. This
means that the arguments may have different widths in this special case.
Patch is from pr2251119, suggested by Martin Whitaker.
This patch moves the checks for automatic variables being passed to
the $monitor or $strobe system tasks from the calltf routine to a
new compiletf routine. It also adds the file name and line number
of an offending call to the error message.
VHDL can't select bits from arbitrary expression so sometimes
translating IVL_EX_SELECT would fail. This is easily fixed by
replacing the select with a shift in this instance (and the
resizing)
The VVP %join function was incorrectly treating the return from a
non-automatic function as a return from an automatic function in
the case that the non-automatic function result was being used as
a parameter to an automatic function. This patch fixes this error.
A simple typo in the rhs of an expression would crash the compiler.
Example:
module crash3;
reg clk;
integer cnt1=0;
always @(posedge clk) begin
cnt1 <= (cnt==81) ? 0 : (cnt1+1);
end
endmodule
This patch addresses a number of issues:
Rewrote the $test$plusargs and $value$plusargs routines to have
better error/warning messages, to support runtime strings, to
correctly load bit based values (truncating, padding, negative
value), added support for the real formats using strtod() and
added "x/X" as an alias for "h/H" to match the other part of
Icarus.
Rewrite the vpip_{bin,oct,hex}_str_to_vec4 routines to ignore
embedded "_" characters. Add support for a negative value and
set the entire value to 'bx if an invalid digit is found. A
warning is printed for this case.
Rewrite vpip_dec_str_to_vec4 to ignore embedded "_" characters,
to support a single "x" or "z" constant and to return 'bx if an
invalid digit is found. A warning is printed for this case.
It simplifies the system task/functions error/warning messages.
It removes the signed flag for the bin and dec string conversions.
This was not being used (was always false) and the new negative
value support makes this obsolete.
Add support for a real variable to handle Bin, Oct, Dec and Hex
strings. They are converted into a vvp_vector4_t which is then
converted to a real value.
Add support for setting a bit based value using a real value.
Removed an unneeded rfp signal in vpip_make_reg()
make_safe_name now makes sure a VHDL signal is never given a
name that conflicts with any reserved words. If it does, we
just prepend VL_.
(This code was already present, but the full list of reserved
words wasn't.)
In the vvp code generator, when zero/sign extending a sub-expression,
the sub-expression is first evaluated and stored in one location in
the thread vector store, then is copied and extended into a second
location. The storage used for the initial sub-expression evaluation
is never deallocated.
The NetEBAdd::eval_tree method is able to use the associative property
of addition to reduce some constants, but it is picky about widths.
Make it a little bit more resilient to expression widths.
Even though we cannot immediately give a width for a concatenation
that has a repeat expression (the expression must be evaluated first)
we still must scan the test_width of the arguments so that they can
resolve their types.
This patch adds a number of compile and run-time checks for illegal
uses of variables declared in automatic tasks and functions. It
also adds a check for event expressions in automatic tasks that use
features not yet supported in VVP.
In the ivl_target API, the IVL_EX_BACCESS expression type gets some meat,
specifically references to the branch it accesses and the the nature to
be accessed on that branch.
This includes enough API to get the branch nexus bits and signals
and show them in the dump. This also includes creating the reference
ground for branch access functions that use the implicit ground.
This patch fixes a number of problems related to the divide and
modulus operators.
The net version (CA) of modulus did not support a signed version.
Division or modulus of a value wider than the machine word did
not correctly check for division by zero and return 'bx.
Fixed a problem in procedural modulus. The sign of the result is
only dependent on the L-value.
Division or modulus of a signed value that was the same width as
the machine word was creating an incorrect sign mask.
Division of a signed value that would fit into a single machine
word was not checking for division by zero.
Division or modulus of a wide value was always being done as
unsigned.
Added a negative operator for vvp_vector2_t. This made
implementing the signed wide division and modulus easier.
This patch fixes a minor memory leak in ivlpp and releases all
dynamically allocated memory before the program exits. Other than
the dynamically allocated push state buffer in flex, ivlpp has no
valgrind memory errors or warnings.
There was a memory leak in the preprocess_only code (cmd was not
being freed when the command completed successfully. Valgrind
was also marking the temporary file names as still reachable, so
they are not memory leaks, but freeing them makes valgrind happier.
The natures of disciplines were already available, this just brings
the information forward to the ivl_target.h API and exposes them via
access functions.
The goal is to completely remove the svector class because the standard
vector class works perfectly well. This removes the uses in the Module.h
header file.
Signals may have VMA disciplines attached. Make the attached discipline
visible through the ivl_target.h API. Also, re-arrange the internal
handling of the discipline structure so that we can expose disciplines
through the ivl_target C API without creating new structures. The
t-dll-api implementations of the discipline access functions can look
at the elaborated discipline structure directly. This is possible since
the discipline parse and elaboration are very simple.
Support arrays of realtime variable arrays and net arrays. This
involved a simple fix to the ivl core parser, proper support in
the code generator, and rework the runtime support in vvp.
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. This patch set covers the tgt-vhdl
directory, and was tested by Nick.
This patch fixes some problems found when trying to dump words
from a real wire array. There are still a few more things that
look suspicious and need testing.
This patch splits any VVP net functor that needs to access both
statically and automatically allocated state into two sub-classes,
one for handling operations on statically allocated state, the
other for handling operations on automatically allocated state.
This undoes the increase in run-time memory use introduced when
automatic task/function support was first introduced.
This patch also fixes various issues with event handling in automatic
scopes. Event expressions in automatic scopes may now reference either
statically or automatically allocated variables or arrays, or part
selects or word selects thereof. More complex expressions (e.g.
containing arithmetic or logical operators, function calls, etc.) are
not currently supported.
This patch introduces some error checking for language constructs
that may not reference automatically allocated variables. Further
error checking will follow in a subsequent patch.
The arguments of logical and/or are self determined, and the width is
fixed as 1 bit. Account for this special behavior by creating the
PEBLogic class.
The comparison operator operands are self determined, but are forced
to be the width of the wider operand. This means that the operands must
be evaluated with their widths truncated. In spite of all this, note
that comparisons expression results are 1 bit wide.
The operands of divide need to be at least the width of the expression
when calculating a constant divide. The only matters for the special
case where the result is x, because the verinum implementation of
divide will get the result width from the left expression width.
Now that NetNet objects in NetScopes are kept in a map, remove the
linked list for scanning them. This improves the lookup process from
an O(e**N) process to more like O(log(N)). This matters for very
large designs.
Get at least basic elaboration of analog processes and contribution
statements. Bring the statements and analog statements together and
net future elaboration work sort out which statements are valid in
a given context. This makes sense because there really is a lot of
syntactic overlap, and analog behavioral code is processed somewhat
sequentially.
Put together the infrastructure for elaborating analog statements,
including create the NetAnalogTop objects that hold analog statements
and are in turn held by the design.
While doing this, clean up the various unique initial/always enumerations
to use the ivl_process_type_t type.
The optimization that allowed a mux that had one input always
connected to high-Z produces code that is actually slower than
the original mux, so for now we are removing that optimization.
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. No regressions in test suite.
The bufif devices do not correctly propagate the Z value as
required by the standard. The MOS devices do propagate a Z
value, but they do not correctly handle the case where both
inputs are Z and the select is undefined/Z. The standard
specifies that this should be X, but we produce Z. The full
MUX and %blend operator also function this way, so Icarus
may not match the standard, but it is consistent. I would
also argue that the standard is incorrect. If both inputs
are Z then the output should be Z no matter what select is.
The condition expression needs its width tested, even if the width
is not used. Also clean up some handling of widths/types for other
expression types.
This fixes the sign calculation for port padding. It also reports if
the padding will be signed or not in the warning message. The inout
calculation may not be correct. It requires both the signal and the
port to be signed, but inout is not currently padded anyway.
If a part select (either a constant or constant indexed part select)
of a L-value is fully outside the signal the part select will be
omitted after printing a warning. If a part select straddles the
upper portion of a signal a warning will be printed. The run time
will use only the appropriate part of the select. Straddling the
lower part of the signal is not currently supported and a message
is printed for this case.
The right-operand of shift expressions is self-determined, but we still
need to run a test_width to get the PExpr decorated with types and
expression widths.
A casex statement cannot be directly translated to a VHDL case
statement as VHDL does not treat the don't-care bit as special.
The solution here is to generate an if statement from the casex
which compares only the non-don't-care bit positions.
The l-value doesn't really constrain the size of unsized expressions
because there are possible sub-expressions that may pull high bits
down to the low bits. (Divide, for example.)
It is possible, via the use of the $signed() function, for concatenation
expressions to be signed. Make sure the evaluated constant had the
proper sign by checking explicitly.
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. No regressions in test suite.
This patch modifies the code that finds and combines similar events
such that if similar events are found in both static and automatic
scopes, the retained event will be in a static scope. This is a
performance enhancement, as VVP has more run-time overhead when
handling events declared in an automatic scope.
This code was likely never checked properly since it makes no
sense to copy the expression from the new temporary system
function. You must copy the value from the current function.
Even on 64 bit machines immediate values should be limited to
32 bits so that the a.out file will run correctly on a 32 bit
machine. This patch fixes a number of places where the code
generator was not checking for/observing this.
The signedness of comparison expressions is typically unsigned, even if
the comparison to be performed is signed. The comparison (and particularly
the expr_synth of the comparison) needs to account for this explicitly.
If either of the operands of a ternary expression are unsigned, then
both are treated as unsigned. It works just like a binary expression
in that regard.
It is up to the elaborator to sign-extend the inputs if the multiply
is signed in the Verilog source. The run time always processes the
multiply as unsigned.
The results of comparisons are unsigned, but the arguments may be signed
and the calculation performed may be signed. Handle the padding properly
for comparisons so that the math is properly signed.
When doing lossless addition to an unsized constant, we make the size
be width of an integer, only to be consistent with other tools. In fact,
don't go overboard if we don't have to.
Later passes need the intermediate results for width and size so that
some special cases, were self-determined arguments occur, can be
processed properly during elaboration. This can be especially tricky
and interesting for ternary expressions.
Start cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. YMMV.
This patch fixes the expression width calculation for a multiply
operation with an unsized operation. The expression width needs
to be at least the minimum of the maximum multiply result width
and the width of an integer.
Currently, a bitwise boolean operator will cause the expression
width to be reduced to the size of the result. This can give
rise to incorrect results. This patch changes the behaviour to
take into account the required precision for calculating the
two operands.
This patch removes all the checks for constant expressions performed
during the parsing phase, as these checks are (mostly) repeated during
elaboration. It adds the missing check in the elaboration phase (the
RHS of a register initialisation), and improves the error reporting
and error recovery in other checks.
This patch fixes pr2132552, which was caused by a fault in the parser
constant expression checking.
Emitting a VHDL expression like Resize("01", 32) is ambiguous
between interpreting "01" as a Signed or an Unsigned. There's
no point actually outputting this as we can sign-extend the
constant value in the code generator, which is what this
patch does.
In assignments, the expression width may be defined by the width of
operands, and not that of the l-value. Choose whichever is creater and
set (or pad) the expression to that width.
Multiply of any expression with constant 0 will always return zero.
We can handle this early, during elaboration, and save a lot of code
downstream the trouble.
Also, while we are at it, fix up test_width to re-test the left
expression width if the right expression width is unsized. This allows
for the left expression code to adapt to the unsized-ness of the
expression context.
This patch pads inputs and output ports correctly when the port
and the port expression have different widths. It does not fix
inout ports.
It also sets the file and line number information in the unsigned
pad_to_width() routine.
This patch pushes the evaluation of constant system functions into
normal elaboration vs doing them in the preliminary parameter
elaboration.
It also fixes the compiler version of clog2 to return integer_width
vs a fixed 32 bits.
There are cases where the r-value doesn't pad itself to the width
that is requested by the call to elaborate_expr. This impacts the
elaboration of PGAssign. Pad/sign extend as appropreate.
The arguments to bitwise operators are padded if *either* of the operands
is unsigned. This is according to the sign/unsigned expression rules
of Verilog, and also matches the behavior of the "Big-3."
The addition of UINT_MAX in netlist.cc requires #include <climits> when compiling with gcc-4.3.2.
I also noticed that commit 8704e3e used c style includes in c++ sources contrary to the style used in the rest of the c++ code and fixed those.
In the transition to the new expression code we forgot how to
handle the logical not (!) of a real value. This patch adds a
more appropriate error message until we get this reimplemented.
MinGW uses the GetProcAddress() function to find the address of
the vlog_startup_routines() procedure in a .vpi file. This routine
requires that the leading underscore be omitted from the name even
though the underlying routine really has one.
alloc_instance for real values was just passing a new double
to be added to the context items. The new constructor does
not set the default value so we need to do that manually.
Simple error setting the expression width of the FALSE clause of a
ternary expression when the expression is short cuirted to false.
Fix a simple error where the type of a system function is not returned
through the test_width function.
The arguments to user defined functions are self-determined. And if
the result is real valued, we can call them lossless self-determined.
Treat these arguments like r-value elaboration for assignments.
Also clean up the binary divide elaboration a little bit.
Also, floating point literals are unsized with width==1.
When a multiply expression is IVL_VT_REAL, then the default width is
the width of the operands, and not the sum of the operands. In fact, it
should turn out to be 1.
Also, the width of the multiply expression when we get to the ivl_target
API, need not be the sum of the widths of its arguments. In fact, if the
arguments are signed, that would be completely wrong. So adjust the
stub target to properly test this constraint.
Widths of real values are always 1. When paired with vectorable types
in expressions, the vectorable type is processed as losslessly self-
determined. ("unsized" in the test_width methods.)
Don't force the expression with to be different from the l-value if the
l-value is the immediate destination. This saves the effort of handling
overly wide constant values in simple cases.
Also, in determined contexts, signed unary minus does not need to pad the
width of the expression.
the PGAssign elaborate method used the test_width to get the width
of the r-value expression. This should be completely sufficient to
get the width of the expression, so always use a defined width to
elaborate the expression.
When ternary expressions are self-determined, use the test_width
method to get a proper reading of the expression width. Also improve
the test_width method to handle unsized operands.
This patch adds non-blocking event control for array words.
It also fixes a problem where the word used to put the
calculated delay for a non-blocking array assignment was
not being released. It also fixes the non-blocking array
assignments to correctly handle off the end/beginning part
selects.
Currently, parameters and localparams declared in tasks, functions,
generate blocks, and named blocks are placed in the parent module
scope. Event declarations in these scopes are not permitted (a
syntax error is reported). This patch corrects this behaviour, so
that all the above declarations are accepted and are placed in the
scope in which they are declared.
Note that the IEEE standard does not permit parameter declarations
in generate blocks. This patch causes the parser to reject such
declarations.
Since some event control assignments can be skipped we need an
event control clear so that future %evctl statements do not fail
their assert. This patch adds %evctl/c and uses it in the compiler
as appropriate to keep the event control information in sync.
This patch adds full event control for vectors and parts of a
vector. It also fixes the other non-blocking part select code
to correctly handle a negative offset ([1:-2] of a [4:0] will
have an offset of -2).
When evaluating an expression into an index register bit 4 is used
to determine if the expression had any X/Z bits. In the case of a
constant immediate value this can not happen so make sure the bit
is cleared.
We need consistent pointer output (%p) and under MinGW we need to
us _snprintf instead of snprintf to get this. The recent event
control addition missed this. This has been reported to the MinGW
developers and they are working on a solution.
The previous patch (commit 8b0ca902a6)
dealing with the possibilities of (unsigned long) and (vvp_time64_t)
being either the same or different managed to redefine UL_AND_TIME64_DIFF
in the 64-bit case. This does, of course, trigger a compiler warning.
That warning is repeated on every .cc file with a #include "config.h",
which is to say, just about every file.
This patch inverts the sense of the preprocessor conditional, calling
it UL_AND_TIME64_SAME. No more warnings!
It takes a carefully crafted source file to cause elabortion to make
an arrayed multiple-output gate that is not vectorized into a single
wide gate. But that special case does need to be handled.
While the standard is not completely clear about this, we are making
it an error for a `timescale directive to be inside a (macro)module
definition. This means that all modules and any statements contained
within have a single well defined time unit and precision.
Logic gates usually have one output and several inputs, but a few
have multiple outputs and one input. Since the NetNode objects have
only a single output, handle the case by creating multiple NetNode
objects, one for each output.
A variable that is used to set the delay of a .delay statement
must be scaled to match the local units and for real values
rounded using the precision. This value is then converted to
the simulation precision.
Signals of a nexus must have types that exactly match, but the drivers
of a signal nexus have slightly more subtle rules for the case where
the signal is IVL_VT_LOGIC. Express those rules in the function
check_signal_drive_type, and use it to check the type of constants
driving a signal.
Remove redundant pointer to the containing NetPins object by keeping
the pointer only in the first Link (pin 0) of an array of links. In
this link, replace the pin number with the NetPins pointer, and set
a pins_zero_ flag to indicate that this has happened. This way, only
the first pin in a Link array will have the pointer to the NetPins
that contains the array, and the pointer takes up practically no space
at all.
This class was old, and its original design pulled literally from
the LPM reference. But of nine pins declared, only 4 were used.
Remove all the excess junk and clean up the designed dump handling
of the device.
The r-value expression takes on at least the width of the l-value. If
there is a sized width greater then the l-value width, take that on
instead. But if the r-value is unsized, there are unsized sub-expressions
that cause the expression as a whole to be unlimited width, so elaborate
and evalulate the r-value as lossless.
The true and false expression clauses must have compatible types,
which are not necesarily identical. In particular, VT_BOOL and
VT_LOGIC are compatible for the purposes of ternary arguments. The
test in NetETernary::synthesize was incorrect.
In the process, fix the type handling of NetConst objects to allow
for IVL_VT_BOOL constants. This is information that the downstream
may find useful, so should be handled correctly.
It's processed once by AC_OUTPUT in configure.in and then again
by AC_OUTPUT in tgt-vhdl/configure.in. This is a bug from when I
first started on the VHDL target, and was basing it on the tgt-vvp
code. The call to configure in the tgt-vhdl directory is not
actually necessary either, since it doesn't do any checks not
performed elsewhere, so that should proably be removed later.
This patch pushes the non-blocking event control information to
the code generator. It adds the %evctl statements that are used
to put the event control information into the special thread
event control registers. The signed version (%evctl/s) required
the implementation of %ix/getv/s to load a signed value into
an index register. It then adds %assign/wr/e event control based
non-blocking assignment for real values. It also fixes the other
non-blocking real assignments to use Transport instead of inertial
delays.
The exponentiation operator in VHDL is not defined for numeric_std
types. We can get around this by converting the operands to integers,
performing the operation, then converting the result back to the
original type. This will work OK in simulation but certainly will not
synthesise unless the operands are constant.
However, even this does not work quite correctly. The Integer type in
VHDL is signed and usually only 32 bits, therefore any result larger
than this will overflow and raise an exception. I can't see a way
around this at the moment.
When the -V flag is passed to the iverilog command, we can easily
print the version information for the driver itself, but it is also
valuable to probe all the components that would have been used for
a real compile. So the driver executes the preprocessor and the ivl
core to have them print version information.
The ivl core program also tries to load the target code generator
and get version information to print. For this to work, create a new
optional entry point "target_query" that takes a query key string as
an argument and returns a const string as the result. Use this with
the key "version" to get version information out of the target.
Target selection is done by the DLL target code generator, so there
is no value having a layer of target selection ahead of it. Remove
all that redundant code and simplify the target config files to reflect
this.
It is possible for signe-extend to have a delay attached to it. (Same
for repeat.) Handle it like other LPM devices, by stuffing a .delay
device into the output path of the device, if appropriate.
Generate scopes were previously ignored, and this would cause a segfault
later on. This patch gives an error whenever it encounters a generate
scope. This should be removed once generate statements are implemented.
Nothing to do with tab width! Eliminates useless
trailing spaces and tabs, and nearly all <space><tab>
pairings. No change to derived files (e.g., .vvp),
non-master files (e.g., lxt2_write.c) or the new tgt-vhdl
directory.
Low priority, simple entropy reduction. Please apply
unless it deletes some steganographic content you want
to keep.
Statements can have attributes attached to them. Handle a few cases in
the parser where attributes may be attached to statements, and get them
as far as the pform.
This patch adds blocking repeat event controls and also makes the
base repeat statement sign aware. If the argument to repeat is
negative (it must be a signed variable) then this is treated just
like an argument of 0 (there is no looping). Doing this allows us
to model the repeat event control as follows.
lhs = repeat(count) @(event) rhs;
is translated to:
begin
temp = rhs;
repeat (count) @(event);
lhs = temp;
end
This patch also pushes the non-blocking event control
information to the elaboration phase where it will report they
are not currently supported.
The generate block is a placeholder for the generate items, and it
is the items themselves that can specify the name of the generate
block that is created.
Add "include" to fix error with abort() in dup_expr.cc
Add "include" to AStatement.h so usage of struct PExpr works
Get rid of eval_tree.cc:577: warning: suggest parentheses around comparison in operand of ^
The right shift of vvp_vector2_t needs to
account for and mask off shifted bits. Otherwise
there will be unexpected results after
a vvp_vector2_t::trim method.
This patch adds the constant system functions for Verilog-2005
and Verilog-AMS. These are evaluated at compile time. $abs(),
$min() and $max() support their polymorphic behavior in the
compiler where it really matters. They are always evaluated
as reals in the run time and the result/argument(s) will be
converted as needed.
The Verilog-2005 functions are available if using the 2005
generation (default) and if either the icarus-misc (also on
by default) or verilog-ams flags are set.
The Verilog-AMS functions are available if either the
icarus-misc or verilog-ams flags are set.
If the argument to $clog2() is unsized constant, then trim it to the
smallest representation that doesn't lose the sign, then do the $clog2
on that.
Also, use integer_width instead of 32 for the minimum $clog2() result
for a negative value.
If the argument to $clog2() is unsized constant, then trim it to the
smallest representation that doesn't lose the sign, then do the $clog2
on that.
Also, use integer_width instead of 32 for the minimum $clog2() result
for a negative value.
This patch moves the always zero or possibly zero delay checks
to a point after the circuit is full elaborated. Before it
could try to check tasks that had not already been evaluated
resulting in a crash.
When looking for a delay_type() in a block stop when we have a
DEFINITE_DELAY. Doing this could reduce the number of statements
that need to be checked.
Previously only signedness was only corrected for the
result. This patch ensures the VHDL operands have the
same signedness as their Verilog counterparts.
This fixes a few of the signedX tests.
Assume that anything that is strength aware already handles a
recv_vec8_pv and make the default function convert the bits
to a vec4 and then call recv_vec4_pv with this new value.
It is legal for a task to have no definition. In that case, the
delay_type calculations (used to detect infinite loops) can assume
that an empty definition is a no-op and return NO_DELAY.
Be more sophisticated with the code generated for constant values.
When values are large, use an optimal mix of %movi and %mov
instructions to get the desired value, no matter what the content.
This splits up the monolithic and confusing vhdl_expr::cast function into
several smaller to_XXX functions which each generate code to cast an
expression to type XXX. This makes it much easier to understand and maintain.
In continuous assignment, the width of the expression needs to come
from the expression itself, and not just from the width of the l-value.
Use the PExpr::test_width method to get the width of the expression
to pass to the elaborate.
the sub_net_from function is used by the ::synthesize method of the
NetEUnary class to make the expression 0-N. By making that function
handle a real-valued net, the NetEUnary suddenly supports real-valued
nets, and this probably helps in other places as well.
When the condition expression of a ternary is constant 1 or 0, we can
short-circuit the elaboration by only processing the clause (true or
false) that we need. This saves compile time and execution time.
This patch adds an error message for the standard system
tasks and functions that are not currently implemented.
These are currently $fmonitor*, $ferror, $fread, the
queue and PLA tasks.
It is possible for the left operand of a left shift to be not known
early during elaborate expression. In that case, make a punt expression
and expect it to be resolved later.
GCC 4.3 has tightened up header dependencies so that
`strcmp' is no longer declared if <cstdlib> is included
(which it was in prior versions). This causes the changes
in 5e512e6570 to fail to
build with 4.3.
This patch includes <cstring> in the files that are failing.
The expr:::synthesize methods need not deal with saturating left or
right shifts if they are dealt with early, in elaborate_expr methods.
So the elaborate_expr for shift takes on much more responsibility.
Mostly this ensures that a recursive call to a function
is made with the correct types (this may involve generating
code to cast expressions to the correct type).
This patch pushes the automatic property for both tasks and
functions to the code generators. The vvp back end does not
currently support this so it will error out during code
generation. The VHDL back end should be able to use this
property and tgt-stub prints the property. Having this will
also make it easier when we do adding this to the runtime.
This patch adds the $clog2 system function. It also makes this
function work as a constant function. The runtime version still
needs to be updated to use an integer based version instead of
the current double based method. The double method suffers from
rounding errors.
This patch adds support for vpiScaledRealTime and vpiSuppressTime
to VPI callbacks. It also fixes a bug where the callback data
object was not being copied correctly and adds support for
vpiSuppressVal. This requires adding vpiSuppressVal to a few
other routines. It adds the ability for a callback to return
more than vpiScalarVal (all values supported by the
vpip_vec4_get_value() procedure). It also fixes a bug where
vpip_vec4_get_value() would incorrectly return vpiZ for a BIT4_X
scalar value. It also comments the potentially dangerous
vpiScalarVal calculation in the vvp_fun_signal::get_value()
procedure.
Since NetExpr::synthesize methods were rarely used, then had a lot
of bugs. Now that continuous assign uses these methods, these bugs
must be fixed.
Binary and Unary minus properly pad/extens its arguments,
Case compare generates correct code,
Divide properly takes on signed flag,
Signed right shift sign-extends its argument to prevent loss of sign bits
and uses the NetSignExtend instead of simple padding,
Use the correct target node for reduction NAND,
Properly handle constant arguments of NetESelect
Handle some exressions that were not handled before, include abs()
and POW.
In signed contextx, the right shift and unary minus expressions need
to be sign extended before they operate, otherwise there may be bad
results in the high bits in the greater context.
This patch causes a thread that is created to evaluate a function
to be executed immediately. The parent thread is resumed when the
function thread terminates.
Because Icarus tries to elaborate as much as it can even after
an error has occurred we need to check for these errors during
elaboration. This patch prevent an undefined identifier from
crashing the compiler.
When the continuous assignment is signed, then sign-extend the r-value
in the few cases where the expression is stubbornly smaller then the
desired width.
When multiply is done in native words, the conversion to words from the
vp_vector4_t vectors must be done signed. This only matters if the
input operands are different sizes (and themselves signed) but will
not hurt even if we want an unsigned result.
Logical (in)equality needs to look at all the bits of both operands,
and cannot short circuit the test unless defined bits differ. If there
are undefined bits, the equality is undefined at that point, but return
x only if there are not other bits that make the results clearly
unequal.
When nets are assigned directly to a net, we need to create a driver
to carry the strength. Normally, the implied drive of a continuous
assignment is carried by whatever gate the r-value expression ends
with, but with simble net-to-net assignment, there is no net so we
need to install a BUFZ to carry the assignment.
This is caused by using a hierarchical reference (which can't
be translated to VHDL). The result of get_decl is NULL since
the signal has been declared in a different VHDL architecture.
Adding the assert is cleaner than having it segfault, for the
moment, until a nicer error message can be added.
convert the continuous assign elaboration to use elaborate_expr
and synthesize methods instead of the elaborate_net methods of
PExpr. This exposes problems with the synthesize methods, but it
is a better way to do it.
Previously this was handled by creating an internal
signal that was connected to the output and could also
be read inside the entity. The correct solution is to
make the output `buffer' rather than `out'. However, this
does not work in the case when an output is connected to
an output of a child entity, and that values is read
in the parent. In this case *both* the outputs of the child
and the parent need to be made `buffer'.
Combinatorial UDPs will be implemented with a `with ... select'
statemetnt. However the input to this must be "locally static".
This patch joins the inputs into a vector which can be used as
the select expression.
In preparation for using the synthesize method to replace the
elaborate_net method of PExpr, rework the interface to the
synthesize() method. This changes no fnctionality, but does set
up the infrastructure for the next step.
When elaborating a parameter expression fails we need to set the
expression to 0 since it has already been partially allocated.
Doing this allows us to not evaluate the dummy expression later.
This patch adds the time and realtime properties for user
task and function arguments. It also make a common rule
for real and realtime since they are the same.
This patch fixes a bug in the VVP code generator that causes syntactically
incorrect code to be generated if an event expression contains a memory or
array port.
The list of defparams in the pform module definitions (in class Module)
should not be consumed when they are used. The module may be instantiated
moltiple times, so consuming the defparams during elaboration will cause
subsequent instantiations to not have the defparams. That's wrong.
...with the correct behavior. It would be possible to
just translate it as a regular VHDL case statement (as
it was before this patch). But the behavior is not
correct as VHDL only does the equivalent of case-equality
in case statements and this can be confusing when debugging
the output. An alternative might be to emit a warning rather
than an error.
When driving an input port to a module, watch out for the case where
the net is also driven within the instance. If this is the case, take
pains to make sure what goes on in the instance doesn't leak out
through the input port. Add a BUFZ (continuous assignment) to isolate
the context from internal driving.
The old code returns a vpiIntVal for $fscanf("%d") format strings. This
limits the maximum input range arbitrarily to 32 bit.
This patch implements %d parsing similiar to %b and %x.
'?' and 'X' chars are not accepted for %d format.
If the final statement in a process is a non-blocking
assignment then there is no point adding a `wait for 0ns'
after it since it will be immediately followed by another
wait. This case is suprisingly common, so this patch helps
generate much cleaner output without breaking the cases
where the 0ns wait is actually required (e.g. to implement
non-blocking assignment properly).
The NetBranch object is connected, but not like an object, so the
NetPins object base class is factored out from NetObj to handle the
connectivity, and the NetBranch class uses the NetPins to connect a
branch.
Also, account for the fact that nets with a discipline are by default
real-valued.
This patch adds a forward declaration for every user funciton.
This fixes VHDL compile problems if a function calls another
before it has been declared.
Multiple lvals are implemented by first assigning the complete
RHS to a temporary, and then assigning each lval in turn as
bit-selects of the temporary
Previously the code generator expanded ternary assignments to
and `if' statement. This patch replaces that with a single assignment
and a call to a Ternary_* support function. This will make it
much easier to support multiple lvals later.
The double to vvp_vector4_t constructor was not using the correct
declaration for the bit words. This worked as long as unsigned and
unsigned long were the same size (usually).
Detect function call expressions that turn out to be calls to the
access function of a nature. Elaborate the access function and stub
the emit code. This gets the access function just short of the code
generator.
The preprocessor was incorrectly setting the line when starting
an include file to the line it was called from instead of 1.
This would give incorrect line numbers for errors/warnings in
the included file.
The new real to int conversion was incorrectly setting the
bits for minus infinity to all ones. This is incorrect in a
two's complement encoding where the largest negative number
would be a leading 1 followed by an infinite number of zeros.
This patch updates the %cvt/vr command to use the new double to vector
constructor. This allows the resulting bit pattern to be larger than
a long. The old method was producing incorrect results without a
warning for large bit values.
This patch makes .part/pv strength aware, resolv vec8_pv
aware. vvp_net_fun_t adds vec8_pv as a virtual function
with an appropriate error default. vvp_fun_signal should
full support vec8_pv (not tested and may not be needed).
This patch fixes a bug where a local parameter with only a range
was incorrectly setting the default parameter type to IVL_VT_NO_TYPE.
This would create a compile time assert for any untyped
parameter/localparam immediately following it.
Contribution statements have an l-value and r-value. Parse those
expressions into pform so that elaboration has something to work with.
In this process, this patch also changes the PECallFunction class to
use the vector template instead of the svector template. The latter
doesn't add anything over the STL vector template, so this is a start
of working the svector out.
Whilst adding `wait until ...' at the end of every
process is a valid translation of the input, it is not
actually synthesisable in at least one commercial
synthesiser (XST). According to the XST manual the
correct template is to use `wait until ...' at the
start of sequential processes and `wait on ...'
(equivalent to `wait until ...' with 'Event on all
the signals) at the end of combinatorial processes.
This patch implements that.
Initial processes set a magic flag in the code generator
which allows it to push constant assignments into the
VHDL signal initialisation and omit the assignment.
However, it should only do this if the signal has not
already been read (otherwise the previous read would
not get the undefined value as expected)
If the Verilog source contained a continuous assignment
of a constant to an output, it would not be present in
the VHDL output. This patch generates a VHDL continous
assignment in these cases.
If output P of A is connected to output Q of B (and A is
instantiated inside B) then VHDL does not allow B to read
the value of Q (also P), but Verilog does. To get around
this the output Q is mapped to P_Sig which is then connected
to P, this allows B to read the value of P/Q via P_Sig.
Previously the code generator tried to infer the VHDL types. Now it
takes a much more dumb approach and forces the VHDL type to be
the same as the ivl type (derived from ivl_expr_signed and
ivl_expr_width) in the expression tree. This works much better :-)
The signed/unsigned-ness of an expression needs to be
preserved over any call to Resize. Also add a sanity
check to make sure non-vector types are not resized.
Verilog_Case_Ex is used as a temporary to store the result of
any non-static case expression. This fixes a bug where it would
be declared multiple times if there were multiple case statements
in a block.
When generate schems and instance arrays are nested, it takes
multiple iterations of elaborate scope, defparams and evaluate
parameters before everything is worked out. Rework the work item
processing so that the loop elaborates scopes and runs defparams
in phases. The phases are needed so that we can tell when the
remaining defparams are orphaned.
Modules mentioned within generate schemes are not candidates for
defaults guesses at root modules. They are, obviously, used within
the generate schem.
We must run generate schemes after running defparams because the
defparams may define the results of the generate schemes. So put
the generate schemes for a module scope into elaborator work items.
The l-value of a defparam assignment is a hierarchical name that may
include array selects to select scopes from module arrays. Therefore
it makes no sense to store parsed defparams in a map. Instead, they
should go into an ordered list. This also maked more sense because later
defparams *may* have the same name as a previous defparam, and will
override the previous defparam. So replace the map of parsed defparams
with a list of parsed defparams.
Also, as soon as the defparam expression is elaborated, the list entry
is no longer needed, so delete it. Save memory.
It is possible for defparams to not find their target the first time
around, because the elaboration of the target scope is not yet done.
So retry the defparams once for each scope by putting it on a work
item in the elaborator_work_items list.
The file and line number information needs to be copied when
doing a macro expansion. This prevents a macro that expands to
an `ifdef of other construct that needs to push the stack
from core dumping.
When we detect that a module instance is an array of instances, delay
the elaboration of the array until after the first defparam processing
is complete. This allows for defparam statements to control the
instantiation of module instance arrays.
Putting scope elaboration into work queue items allows for handling
more complex processing order. The elaboration_work_list queue drives
the processing of elaborate_scope and parameter evaluation.
This patch adds .cast/int and updates .cast/real to act as a local
(temporary) net and to support either a signed or unsigned input.
The vvp_vector4_t class not can convert an arbitrarily sized double
to a vector value. This removes the restriction of lround().
Also document the new statements.
Within generate schemes it is possible to have nested scopes, even
more liberally then outside generate blocks. So see to it that the
scopes properly stack with the generate blocks, and that wires and
behaviors are put in the right scopes.
Generating task/function definitions involves getting the functions
to put themselves into the generate scheme instead of the module,
and getting elaboration to elaborate those definitions in the
generate scheme.
Verilog-2001 only allows a single generate item within a generate-
endgenerate region, but allowed one to collect generate schemes with
begin/end blocks. Verilog-2005 cleaned up that mess, and it is the
2005 syntax that Icarus Verilog implements. This patch detects the
anachronistic use of begin/end within the generate region, ignores
the begin/end words, and prints a warning that the user is using an
obsolete syntax.
Named begin/end blocks burried within generate schemes need to be
elaborated. Handle this by remembering to elaborate_scope on the
statements within the generate scheme.
In the process, clean up/regularize some of the member names and
methods.
This handles the general case of a non-real operand to a real-valued
division. This can turn up if only 1 operand of a divide is real. In
this case the division as a whole is real and the other operand must
be cast to real.
This method creates an extra node, but it should be a very compact
node and this node does no evaluation tricks so in the run time should
be no more expensive then folding the cast into the .arith/div.r itself.
This patch adds checks that $fopen is only called with a valid
mode argument. It also checks that the file name for $fopen{a,r,w}?
is a valid looking file name (all characters satisfy isprint()).
The later should prevent creating weird file names because of
Verilog bugs.
This patch changes the base oct to string converter to correctly
pad the top digit. x or xx should display as a single lower case
x when they are located in the top bits. Before these were being
interpreted as 00x or 0xx and displayed X. Also modified the hex
conversion to use this same scheme instead of a loop.
First, handle the trivial (but possibly common) resolution cases in
inlined code, and only call the complete function for the complicated
cases. Then clean up the complex function for readability, and account
for the constraints that the front-end function established.
Arrays of vvp_vector4_t values redundantly store some fields in every
word. Create a special type that stores vvp_vector4_t values in a form
that does not duplicate the width of all the items. This can save a lot
of space when big memories are simulated.
The schedule_assign_plucked_vector is a better way to implement the
schedule_assign_vector, or at least no worse, so remove the now
redundent schedule_assign_vector.
It is legal (though worthy of a warning, I think) for the part select
of an l-value to me out of bounds, so replace the error message with
a warning, and generate the appropriate code. In the process, clean
up some of the code for signal l-values to divide out the various kinds
of processing that can be done. This cleans things up a bit.
This is a major rework on the sys_fileio routines. They now have
improved compiletf routines and the calltf routines are now
standardized. Along the way a few bug were fixed as well. Some
updates to other vpi files as well.
I changed the order of the $fputc() arguments to match C and the
rest of the system functions like it ($fungetc, etc.). I recently
fixed $fungetc() so I'm assuming the $fputc() needs the same fix.
It's an Icarus specific function.
The load-and-add for vectors %load/vp0/s can be combined with the
load-and-add for array words, and the %load/avp0/s added to round
out the combinations. This can make for fewer instructions when
words are padded in arithmetic expressions.
The load-and-add for vectors %load/vp0/s can be combined with the
load-and-add for array words, and the %load/avp0/s added to round
out the combinations. This can make for fewer instructions when
words are padded in arithmetic expressions.
The functor_ref_lookup() function fills its argument in with the
vvp_net_t* pointer that matches the var name, so there is no need
to create the vvp_net_t object before then.
The vpiIndex is really just a different view into the same object,
so implement the trickery needed to support a vpiIndex with the
absolute minimum memory cost.
The %load/vp0 instruction adds a signed value to the signal value being
loaded, but it doesn't allow for a signed source vector. Add the
%load/vp0/s instruction that pads the loaded vector, and add the code
generator details to properly use it.
The vvp_net_fun_t objects, and derived objects, are small, and are
created in large quantities. Tightly pack them into permanently
allocated space in order to save on system allocation overhead, and
thus save overall on memory.
Actually, the immediate value handling is a little chaotic and should
be cleaned up. This patch opens the door for allowing signed immediate
values, and uses them in a few places where they are explicitly handled.
We must go through the opcodes that can take immediate values and make
explicit whether they are signed/unsigned/etc, and what their size
limits are.
Part select of an entire signal returns just the NetESignal itself,
but since part selects are always unsigned, even if the selected
signal is signed, we need to cast the NetESignal to unsigned first.
The part select of a vector is converted by the compiler during
elaboration to a 0-based canonical address. But since it is legal
to address bits below the LSB, the canonical address can be negative.
So make the part select base for selecting from signals work with
signed arithmetic and make the code generator generate negative
indices when needed.
Scheduler cells are small objects that come and go in great quantities.
Even though they are allocated and deallocated a lot, they tend to a
steady state quantity, so put together a heap that is unique for each
cell type.
This heap actually saves memory overall because cells are allocated in
chunks, thus eliminating allocator overhead, and they are pulled/pushed
from/to a heap very quickly so that what overhead remains is slight and
bounded.
The vvp_net_t objects are never deleted, so overload the new operator
to do a more space efficient permanent allocation.
The %assign/v instruction copied the vvp_vector4_t object needlessly
on its way to the scheduler. Eliminate that duplication.(cherry picked from commit d0f303463d)
The vvp_vector8_t constructor and destructor involve memory allocation
so it is best to pass these objects by reference as much as possible.
Also have the islands take more care not to perform resolution if the
inputs aren't really different.
NOTE: This is a port of commit 2f4e5bf5b6
from the "performance" branch, without the resolver scheduling changes.
This was causing test suite variances with pr1820472.v. It looks like
there might be a race in that program anyhow, but for now leave out the
resolver scheduling changes so that the rest of this commit can go in.
The __vpiPV objects express themselves as vpiPartSelect objects.
Add support for value change callbacks by attaching the callback
to the signal that we part select from.
This patch adds the time and realtime types to parameters
and local parameters. It also makes the width (range) of
an integer parameter match the variable "integer_width"
(normally 32 bits). It also converts a real value to
an integer when a range is implicitly or explicitly
given. This all matches what the standard specifies.
Fixed an error in converting -1 to a unsized verinum.
The %load/v instruction was doing some spurious resizes of the vector
that comes from the signal. Eliminate those resizes that can be
removed, and optimize some that remain.
When parameters are replaced, the expression that is replaced is deleted
so make sure the pointer in the map is properly updated. Also, make sure
the defparam expression itself is not deleted because it is used to
print messages, such as design dumps.
This is not a solution to all the problems, but is a better catch-all
then what is currently there. Allow the index field to be a T<> that
accesses the thread to get the address index.
Note that the lexor.lex currently returns the T<> as a T_SYMBOL, and the
users of T_SYMBOL objects need to interpret the meaning. This is
probably not the best idea, in light of all the other *<> formats that
now exist.
Part select of parameter names is fixed up to be structurally similar
to part select of signals, and also to behave similarly. (Though not
identically, for reason.)
Part selects to signals are allowed to be off the ends of the signal
itself. The bits that are beyond the vector return X. This may mean
creating constant X bits on one or both ends of the result.
This patch cleans up some of the code to use common compiletf
routines where appropriate. It also adds code to print the
number of extra arguments and cleans up the messages a bit.
Parameter value ranges support the exclude of a point as well as
range, so add the syntax to support that case. Internally it is
handled as a degenerate range, but the parse and initial elaboration
need to know about it.
If a memory word was accessed before it was defined the
code was returning a zero width vector result. Now it
returns an appropriately sized vector of 'x'.
The memory opcodes %assign/mv, %load/mv and %set/mv
were removed by a previous patch. This one removes
the documentation from opcodes.txt. It also removes
the documentation for the .mem* statements for the
same reason.
Recursive branch resolution was scanning every branch end, even though
many branch ends share ports and need not be repeatedly scanned. Handle
marks and flags to cut off recursion where it is not needed so as to
save much run time.
Conflicts:
tgt-vvp/vvp_scope.c
Note that the draw_net_input.c takes in a lot of the codes that used
to be in vvp_scope.c, so some changes may have been lost.
This patch cleans up the dump routines and adds file and
line number information for errors. It also adds some of
the missing MemoryWord properties so they can now be
dumped and monitored correctly.
This patch adds $simparam and $simparam$str from Verilog-A.
The analog simulator parameters return 0.0 or N/A. The
vvp_cpu_wordsize system function has been moved into the
$simparam call and is now named CPUWordSize.
This patch also starts the factoring of common code in the
vpi directory. Some routines were renamed.
The priv.c file was renamed to sys_priv.c to match the
include file.
System functions can now have strings put to their output.
Rather then join islands while branches are initially created, save the
island creating for the end. This way, the process is actually recursive
and greedy, reliably collecting branches into islands without conflict.
Fold the bi-directional part select into the pass switch (tran) support
so that it can be really bi-directional. This involves adding a new
tranvp device that does part select in tran islands, and reworking the
tran island resolution to handle non-identical nodes. This will be needed
for resistive tran devices anyhow.
The draw_net_input function is modified to account for nexus that is
a port of an island. Draw the ports (and the islands if necessary)
to the island and use the port output for the nexus instead of the
port input. This allows the bi-directional behavior of the port to
interpose itself in the data flow.
In this process of these changes, the draw_net_input function was
reorganized, and all the considerable amount of code for it was
moved to a file of its own. (vvp_scope.c is pretty unruly.)
NetTran devices must be collected into islands because they are all
a bi-directional mass. This is how vvp will process them and the code
generator will need a head start organizing them.
The vvp_island classes are added, as well as support for tranif nodes
that use this concept. The result is a working implementation for
tranif0 and tranif1.
In the process, the symbol table functions were cleaned up and made
into templates for better type safety, and the vvp_net_ptr_t was
generalized so that it can be used by the branches in the island
implementation.
Also fix up the array handling to use the better symbol table support,
and to remember to clear its own table when linking is done.
The code generator was reading the wrong node of a bi-directional
part select. This happens exclusively with part selects passed to
bi-directional ports, so was rare. The result was that the non-part
selected part may get an incorrect value.
The multiply runs does not need to do all the combinations of digit
products, because the higher ones cannot add into the result. Fix the
iteration to limit the scan.
ivl_switch_scope, ivl_switch_attr_cnt and ivl_switch_attr_val
are non-existent routines and should not be in ivl.def. I also
removed them from ivl_target.h. Cygwin expects that if a routine
is listed in ivl.def that it will find a real implementation.
My previous patch always used an empty file if git was not
available. This patch extends this to use the existing
version.h file if it exists (snapshot, etc.)
The handling of immediate add used to do 16bits at a time. When it went
up to 32bits, the need to work in chunks vanished, but the chunk handling
was still there, this time shifting by 32, which causes problems on 32bit
machines. Simplify the %addi handling to avoid this.
Clarify that operands are typically 32bits, and have the code generator
make better use of this.
Also improve the %movi implementation to work well with marger vectors.
Add the %andi instruction to use immediate operands.
Use high radix long division to take advantage of the divide hardware
of the host computer. It looks brute force at first glance, but since
it is using the optimized arithmetic of the host processor, it is much
faster then implementing "fast" algorithms the hard way.
This instruction adds an integer value to the value being loaded. This
optimization uses subarrays instead of the += operator. This is faster
because the value is best loaded into the vector as a subarray anyhow.
The AND and OR operators for vvp_bit4_t are slightly tweaked to be
lighter and inlinable.
The vvp_vector4_t::set_bit is optimized to do less silly mask fiddling.
This involves defining the API for switches and cleaning up the
elaborated form to match the defined ivl_target API. Also add t-dll
code to support the ivl_switch_t functions, and add stub code that
checks the results.
When processing wide vectors of these operations, it pays to process
them as vectors. This improves run-time performance. Have the run time
select vectorized or not based on the vector width.
Improve vvp_vector4_t methods copy_bits and the part selecting constructor
to make better use of vector words. Eliminate bit-by-bit processing by
these methods to take advantage of host processor words.
Improve vthread_bits_to_vector to use these improved methods and Update
the %load/av and %set/v instructions to take advantage of these changes.
The MinGW system() implementation appears to return the straight
return value instead of the waitpid() like result that more
normal systems return. Because of this just return the system()
result without processing for MinGW compilations.
Older version of the MinGW runtime (pre 3.14) just used the
underlying vsnprintf(). Which has some problems. The 3.14 version
has some nice improvements, but it has a sever bug when processing
"%*.*f", -1, -1, <some_real_value>. Because of this we need to use
the underlying version without the enhancements for now.
snprintf prints %p differently than the other printf routines
so use _snprintf to get consistent results.
Only build the PDF files if both man and ps2pdf exist.
MinGW does not know about the z modifier for %d, %u, etc.
Add some missing Makefile check targets.
These instructions can take advantage of the much optimized
vector_to_array function to do their arithmetic work quickly and
punt on X very quickly if needed. This helps some benchmarks.
If the select of a MUXZ is constant 0 or 1, then we can elide the MUX
in place of a simple BUFZ. This should allow the dead code on the
unused side to be removed as well.
Functions like $monitor need to attach callbacks to array words if
those words are to be monitored. Have the array hold all the callbacks
for words in the array, under the assumption that the monitored words
are sparse.
Array words don't have a vpiHandle with a label, so the %vpi_call
needs a special syntac for arguments that reference array words.
This syntax creates an array word reference that persists and can
be used at a VPI object by system tasks.
Memory words may have part selects assigned, but the code messed up
the testing for the validity of the part select base. This fixes do
detect constant bases so that base validity tests are handled at
compile time.
The tran devices include tran, rtran, tranif0/1 and rtranif0/1. These
are all elaborated as options on a NetTran device. It is still not
clear the best way to present tran devices via the ivl_target.h API.
Add include statements (<cstdlib> for abort()) and a cast.
Necessary and sufficient for successful compilation with
gcc-4.3 (Debian 4.3.0-4) 4.3.1 20080501 (prerelease)
The draw_input_from_net function was being used to access words of
a var array, which doesn't work. Have the draw_input_from_net punt
on that case, and by the way the mux inputs don't need to use that
function, instead they should use the general draw_net_input function
to get the input labels.
It is possible for an array to have 1 word in it, so using the array
count to detect an array is incorrect. Use the ivl_signal_dimensions
function, which is there exactly for that purpose.
Before this, the types of parameters were always logic, only the
width and signed-ness could be controlled. A parameter may take
on implicit real values if the expression were real.
With this patch, the type for the parameter can be explicitly set
to logic or real. This also means that the parameter real valued
expressions need to be more crefully treated, possibly with casting
integral expressions to real values, or real expressions to integral
values.
It is possible for the code generator to create .array/port objects
before the .array object that the port refereces, so use the resolv_list
to arrange for binding during cleanup.
Save tons of space per memory word by not creating a vpi handle for
each and every word of a variable array. (Net arrays still get a
vpiHandle for every word.) The consequence of this is that all
accesses to a variable array need to go through the indexing.
This commit handles the most common places where this impacts, but
there are still problems.
vpi_handle_by_name() was assuming it was always given a valid scope
object. In the context of vpi_chk_error() this is not required and
some users use/abuse the interface by calling the function with invalid
objects expecting a 0 return value. This patch adds an explicit check
for the supported types vpiScope and as an extension vpiModule.
Anything else should be flagged as an error once we have vpi_chk_error()
implemented, but for now it just returns 0.
The arguments to $ungetc() were backwards! This patch fixes that
and adds a bit more checking to the compile_tf routine. It still
needs more work, but that can wait for the major system function
clean up I have planned when I can find the time.
It is a quirk of the $signed() system function that the argument
is converted to signed, but the operation that is performed is
not changed. So arithmetic operators on unsigned arguments inside
a $signed() expression still perform unsigned arithmetic.
The pform is now translated/elaborated into NetScope objects. All that
remains is to check the parameter values against the ranges. This is
to be done in the evaluate_parameters() method.
A recent change to sb_to_idx() made it return a signed value
where it previously returned an unsigned value. This patch adds
explicit casts to remove the two signed vs unsigned comparison
warning messages.
Handle parameter value ranges as far as the pform. The +-inf expressions
are not handled yet, nor is the single value exclude, but the other
cases are handled.
The VAMS-2.2 LRM syntax does not include a semicolon after the nature/
discipline name, but the 2.3 LRM does. Effectively, that means that
the simicolon is option from now on.
Fix
elab_expr.cc:1561: warning: comparison between signed and unsigned integer expressions
caused by revised prototype of NetNet::sb_to_idx() in
commit dfb7bf5211
Pform parse enough of the natures that they can be mapped and the
disciplines can bind to them. Since Verilog-AMS expects natures to
be declared before use, we can do the binding early.
The VAMS-2.3 specification says that discipline and nature declarations
have a semi-colon after the identifier, but the disciplines.vams in
the appendix does not. Initial guess what that the disciplines.vams
is correct, but I've been told that the syntax is correct and the
disciplines.vams file is not.
Parse discipline declarations, net discipline declarations, and
analog contribution statements. Don't yet do anything useful with
these, just give a sorry message where they are encountered.
This is part of the standard disciplines header file, with enough
syntax to part the natures and disciplines included. Don't do anything
with the parse results yet.
The Verilog LRM specifies that it is legal to give constant part
selects that are beyond the bounds of the identifier being selected.
But elaboration was flagging that as an error. This patch changes it
to a warning, and handles the cases by generating 'bx bits as needed.
The elaborator improperly allowed user function call nodes to take on
the expression width requested of them. The result was that generated
code had junk pad bits in certain cases.
When calculating 0^z with constant arguments, make sure the result is
x. This problem only happens when the arguments are constants and the
expression is calculated at compile time.
Verilog does not allow macro expansion in strings, and that's that.
But sometimes people want strings of a macro expansion, so add a
stringify syntax that does the trick.
Verilog-AMS supports scaled real numbers, where the "e<N>" (scientific
notation) is replaced with engineering scales from "a" (atto-) to
m (milli-) and "K" (kilo-) to "T" (tera-). This syntax can be handled
way down in the lexor.
IEEE1364 has specific names for the various generations of Verilog that
are supported. Icarus Verilog should stick to those names for selection
the language feature set.
In the process, the extensions that were tied to the 2x generations
are pulled out out and given their own enable flags. The makes all the
feature control more regular and understandable.
This patch adds a new system function $vvp_cpu_wordsize. It returns
the size of the underlying CPU word (long) in bits. This function
can be used to write fully portable tests for the test suite. Other
functions will be added as needed.
The abs() function needs to be able to turn -0.0 into 0.0. This proved
to be too clunky (and perhaps impossible) to do with tests and jumps,
so add an %abs/wr opcode to do it using fabs().
The min/max functions need to take special care with the handling
of NaN operands. These matter, so generate the extra code to handle
them.
Fix when sign extending an expression that the result is also signed.
This bug caused some arithmetic operations (with extended arguments)
to not notice that they are signed.
Also be more robust in noticing that comparisons are signed and should
generate the right code.
This patch adds file and line information for parameters and
local parameters. It also adds file/line stubs for signals in
the tgt-* files. It adds the pform code needed to eventually
do genvar checks and passing of genvar file/line information.
It verifies that a genvar does not have the same name as a
parameter/local parameter.
In continuous assign expressions, the abs() operator can't easily be
burried in generic unary handling, so add the IVL_LPM_ABS type and
generate it as needed.
The va_math module implements functions that are optional in base
Verilog but included in Verilog-AMS. So automatically include the
module if -gverilog-ams is given.
The va_math module implements functions that are optional in base
Verilog but included in Verilog-AMS. So automatically include the
module if -gverilog-ams is given.
Implement in behavioral the abs/min/max operators for real values.
The parser treats these builtin functions as operators, unary or
binary, and elaborates them appropriately.
Also add enough code generator support to handle real valued expressions
in thread context.
Verilog-2005 defines the base-10 log function to be $log10. This makes
sense because in C the log() function is the natural log. So add the
$log10 function.
Since there may be legacy code that uses the $log function, leave it
defined, but we should consider at least printing a warning when the
$log function is used.
Verilog-AMS recommends that users use the system-function style
math functions, but supports traditional style math functions for
portability. Add the keywords and parse the traditional Verilog-A
functions, and handle them as calls to the equivilent system
function.
Add the -gverilog-ams flag to the driver, and the begin_keywords support
for VAMS-2.3 keywords. With this, the infrastructure is in place to
start pulling in features from Verilog-AMS.
The begin_keywords directives manage a mask of keyword sets that are
active at a given moment. This patch makes the lexor actually test
the given keyword against the mask. If it matches, return the keyword
id, if it is disabled then it is an IDENTIFIER.
Package builders/managers find the DESTDIR variable convenient for
installing into a temporary target for building a package. This adds
the DESTDIR varilable to the root makefile.
Also, clean up the verilog.spec file to reduce redundancy so that
maintence for releases is easier.
1364-2001 does not allow a replication count of zero, but
1364-2005 allows them when the replication is enclosed in
a concatenation with other valid bits. This patch adds
code to perform these checks for procedural expressions.
Because of the NetNet object must have a width greater
than zero a replication used in a continuous assignment
can never have a count of zero.
This patch makes sure that objects either support vpiFile
and vpiLineNo or adds dummy code so that a runtime error
will not occur when accessing these properties. It also
returns 1 for the size of real variables and adds a
simplified vpiIndex that matches the Memory interface.
The begin_keywords directive allows the source code to select keyword
subsets so that a bit of code that uses identifiers that class with a
newer version of the standard can still be compiled.
This patch adds code to push the file and line information
for scope objects (modules, functions, tasks, etc.) to the
runtime. For modules, this includes the definition fields.
The va_math.vpi module implements systen-function versions of the
Verilog-A math functions. This library was contributed by Cary R.
Also add the constants.vams include file. This is pretty much
direct from the Verilog-AMS LRM.
This patch adds ifnone functionality. It does not produce an
error when both an ifnone and an unconditional simple module
path are given. For this case the ifnone delays are ignored.
This patch does a better job of recovering from an error in a
task or function definition. This prevents the compiler from
printing many irrelevant error messages.
This patch adds the functionality to tasks/functions to handle the
declaration of multiple ports using a single ANSI declaration. It
also deletes the old range vector before it adds the new one. The
tasks and functions are different than modules so we need to copy
the range for them.
Several places in Icarus Verilog try to get the bits of the integer
part of a double by casting to unsigned or unsigned long. But that
causes some compilers to generate smart code that converts all values
less then 0 to 0, even though we are after the bits, not the math
value. So be careful to do this cast only to non-negative values and
uminus the bits if necessary to get exactly what we want.
Signed-off-by: Stephen Williams <steve@icarus.com>
Fix handling of cases where multiple specified delays are activated
for a given output. Need to apply the standard selection criteria
that gets the minimum value.
The %sub instruction didn't have the efficent implementation that
the %add instructions used. Update subtraction to use the array
method, so that it gets the same performance benefits.
The vvp_vector4_t often receives the results of vector arithmetic.
Add an optimized method for setting that data into the vector. Take
into account that arithmetic results have no X/Z bits, etc.
Logical and/or take as inputs condition expressions, which are scalar
expressions. Be sure to reduce vectors using proper logic to get the
right condition value.
This patch adds check to determine if an always block has delay
in it or not. If there is no delay a runtime infinite loop will
occur. For the indeterminate case it will print a warning message
if the new -Winfloop flag is given. This flag is not part of the
-Wall check!
When generating a real expression you can have bits of the
expression that use vector only operands. When this happens
evaluate that part of the expression as a vector and then
convert it to a real value.
On some systems, 1UL<<X will make a mess if X is the size of
an unsigned long. This especially seems to be a problem on i386
systems. Protect those shifts in the vvp_net.cc.
When left-shifting unsized constants in self-determined contexts, the
constant value is normally pared down to its minimum required width.
But this practically guarantees loss of bits. Instead, detect this
special case and give the unsized constant a width of an integer.
Still allow for the super-special case that the shifted value and the
shift amount are constants. In that case, the result width (and value)
can be calculated precisely and there is no need to resort to default
widths.
This patch uses the true delay expression count not the truncated
one to check that the number of delay expressions is correct.
It also prints the actual number of expressions it found when
printing the error message.
By slightly altering the vvp_bit4_t encoding, a few simple
optimizations become possible. By making Z==2 and X==3, the
conversion from X/Z to X is a simple shift-or, and this can
be used to reduce the size of some of the bit4 operators.
In previous incarnations of the vvp runtime, bit vectors were passed
around as arrays of unsigned char that charried bit4 vectors. That
is no longer used. Remove the last vestiges of that dead code.
Remove dependencies on vvp_bit4_encoding outside of the vvp_net
core types. The table_functor_s class was the worst offfender and
was barely used, so it is now removed completely. There are a few
opcodes in vhtread.cc that also make vvvp_bit4_t encoding
assumptions (and used casts) and those have been fixed. There
were also various VPI interface functions that are fixed.
The vvp_vector4_t holds 4-value logic. This patch changes the encoding
of 4-value bits in the vector to use separate A- and B bit vectors,
with the B- vector signaling the A- bits that are not 0/1. This
allows rapid conversion to 2-value logic, and rapid tests for X
and Z values.
Update the rules for parsing user function definitions to allow
Verilog-2001 ANSI style port declarations. In the process, also
unify with the user task port declaration so that the types don't
diverge. The rules are the same for both, with the extra constraint
that function ports must all be input. This latter rule is checked
later, during elaboration, so that the task/function pform code
can be shared, and better error messages can be generated.
This patch fixes deassign to allow it to unlink from a driver.
It also zeros the cassign_link and force_link pointers after
they have been unlinked. Not doing this will cause an assert
if deassign/release are called multiple times (variable only).
commonly, the make install is run in a compiled directory by a
different user (i.e. an administrator) that doesn't necessarily
have write access to the build directory. This patch fixes it so
that the test that the version.h is up to date doesn't need to
write a temporary file in the build directory.
It also makes sure that if there is a real need to update the
verion.h, and it is not writable, then properly fail the build.
Passing preprocessor definitions forward into library cells was broken
by this bug in processing the precompiled macro values that were written
by the main preprocessor.
Detect thread bit allocation failures and fail gracefully. Print an
error message that points at the expression in question, and return
with an error code so that the compiler exits with an error.
When constant values are added to get another constant value, and the
expression is not otherwise a fixed size, then trim the result to
prevent unbounded expansion of unsized expression with.
In the process, find and fix a bug in the vtrim function that caused
an assert if trimming were not possible for an unsigned value.
This patch fixes the elaboration of parameters in a continuous
assignment to only pad the constants to their defined width.
Previously they were padded to the l-value width which resulted
in a vvp runtime error. This appears to be because the width
for padding is the defined width, but the constant is printed
using its internal width which previously could be larger than
its defined width.
These constants are local nets so I added that flag as well.
This patch adds the ability to assign/deassign a bit or part select.
It also cleans up the code and fixes some problem in the forcing of
strength aware nets.
When printing the strength information for a multi bit net this patch
adds an underscore between the individual bit strength values. This
makes it easier to see the individual bit values.
A patch to insert the version string from git broke compilation when
the source was not a git repository or when building in a read-only
source tree. This patch avoids breaking compilation by using a
graceful failure mechanism for generating the version string and does
not write to the source tree.
Rework the MUXZ and MUXR code to use an enum instead of plain
integers for the select input state. This makes it more obvious
what is actually going on.
This patch adds a flag to the MUXZ object to make sure that it will
run at time zero if needed. If this is not done the default Z result
may not be overridden by an X result.
This patch adds a %assign/av/d opcode. This is a version of %assign/av
that allows a delay expression. Ultimately this allows a dynamically
indexed array to have a delay expression (non-constant delay value).
This patch removes the overly optimistic lookaside save for a signal
that has been set (%set/v). This is incorrect because if a force or
assign are active the value will not be set as expected.
Parameters with vector descriptions that are not zero based and
are used in net contexts should generate the properly ranged
temporary signals. This causes subsequent part selects to work
out properly.
During elaborate_sig, the code to detect implicit wires did not
properly account for the possibility that the name is that of an
explicitly declared parameter.
This patch add (I believe back in) the < and > characters to the
general T_SYMBOL regular expression. The match was also moved after
the special T_SYMBOL cases so that flex would match them correctly.
Flex matching rules are longest or if a tie the first.
This patch adds code to prevent the broken synthesis code in
the development branch from core dumping. Broken code here
refers to the Icarus code not a Verilog file.
This patch fixes a delete[] vs free problem in the NexusSet
class. The items_ array was being allocated with malloc/realloc
and freed with delete[]. The quick fix was to replace delete[]
with a call to free(). A better fix would probably be to rework
the class to use a vector.
The default nettype was not always being set. This patch
modifies the NetScope constructor to get the default
nettype from a parent if it exists. It is set to NONE if
a parent does not exist.
This patch fixes some allocation problems (mostly in the parser
and lexor relating to identifiers). It also fixes a couple places
where uninitialized variables were used. All found with valgrind.
There are still 100 tests that have problems. Many of these appear
to be related.
Macro argument substitution used to just use strstr() to
find an argument that needed to be substituted. This is too
aggressive. It would do argument substitution in the middle
of keywords and other identifiers. A new routine is used
that verifies the character preceding the match is not
a normal identifier character [a-zA-Z0-9_$].
Binary bit based operators were not padding arguments if they had
different widths. The reduction operators and ! were not correctly
evaluating their arguments in a self-determined context.
vvp did not have the ability to handle real parameters.
This patch fixes that omission. Parameters are only used
by vpi calls to get compile time information.
Problems with signed expressions that are set to parameters and
that include multipliciation exposed a few bugs in the calculation
of signed multiply. Fix this and add some improved diagnostics.
It is questionable, but probably legal, for expressions passed as
arguments to input ports of various kinds of gates to implicitly
declare nets. This patch allows the scan through different types
of expressions for implicit nets.
The elaborate_sig handling here does not test for the legality of
having a non-trivial expression as argument to a port. For example,
it is definitely NOT legal to have r-value expressions passed to
output or inout ports. But that will be checked for later when the
instance is elaborated for real.
Threads used to be deleted when they finished processing code.
The problem with this is that some of the code could be
rescheduled to run at rosync ($strobe, etc.). This allowed the
thread data the code depended on to be reaped too soon. This
patch uses a new queue to schedule thread deletion. The queue
is processed after rosync has finished.
This patch makes the muxz and muxr functors schedule events
instead of directly calling vvp_send_*(). This prevents the
code from going into an infinite loop when the output feeds
back to the select.
This patch only applies to the ternary operator when used in a
continuous assignment. It adds short circuiting when the expression
is a constant true or false. It does not optimize the special case of
a constant 'bx expression with constant T/F expressions.
This patch enhances dump() for function definitions, by indicating a
signed result with a prepended "+" and also printing the MSB and LSB.
This matches other dump() routines. It also prints the arguments with
the same information. The arguments also include their type "input",
"output" or "inout".
If implicit nets are declared during elaboration, then the success
of binding during elaboration will depend on the order of the code
in the source file.
The dup_expr() function for NetESignal was not copying the word_
expression. This would cause an individual array access to turn
into an entire array access. The file and line information was
also not being set correctly.
An assert() in tgt-vvp/eval_expr.c was also replaced with an
exit() since the appropriate information was already being
printed.
This patch adds functionality to do a bit or part select release
when a constant value is forced to the net/register. It also adds an
error message when the user tries to force a signal to a bit/part
select. This is not currently handled by the run time, so is now
caught in the compiler (tgt-vvp). Where when this functionality is
needed, it will be easy to know what to do instead of trying to track
down some odd runtime functionality.
What this all means is that you can force a signal to an entire
signal or you can force a constant to any part of a signal (bit,
part or entire) and release any of the above. Technically the
release of a constant value does not have to match the force.
The runtime verifies that if you are releasing a signal driver
it is being done as a full release. I don't see an easy way to
check this in the compiler.
To fix the signal deficiencies we need to rework the force_link
code to allow multiple drivers and partial unlinking. Much of
this is in the runtime, but the %force/link operator may also
need to be changed like I did to the %release opcode.
The IVL_EX_NONE type was not displaying any message and default did not
use the new ivl_expr_{file,lineno} functions to get the source location.
This patch remedies these problems.
vpi_put_value can mimic force and release with vpiForceFlag and
vpiReleaseFlag flags to the vpi_put_value call. With this patch,
the infrastructure is added to allow the flags argument to be passed
to the dispatched put_value function, and for signals handle those
flags as force/release of a net.
This patch reworks much of the ternary code to short circuit when
possible and supports real values better. It adds a blend operator
for real values that returns 0.0 when the values differ and the value
when they match. This deviates slightly from the standard which
specifies that the value for reals is always 0.0 when the conditional
is 'bx. There are also a couple bug fixes.
These fixes have not been ported to continuous assignments yet.
Ternary operators used at compile time and in procedural assignments
should be complete (short circuit and support real values).
When a bit port of a module instance is connected to a vector
argument, the MSB module instance should be connected to the MSB
of the vector argument. This matters only in the rare case that
the %m is used. It also makes wave dumps come out right.
The updates to the do_include code destroyed the
handling of absolute paths; all of the code that
handles buffer-switching was erroneously placed
in just the relative-path branch. Thanks go to
Cary R. for pointing out the problem.
Now the common code has been extracted yet again,
and the notorious goto statement has been used
in favor redundancy.
The test vvp_reg.pl produces the same output as
before, so hopefully nothing new is broken.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
Normally processes are found in the lexical scope of a module, but
there are special cases where processes (other then task/function
definitions) are in other lexical scopes. The most likely case is
initilizations that are in the lexical scope where the assigned
variable is declared.
In the process, the behaviors list is kept in the base PScope class
instead of the Module or any other derived lexical scope class.
Case-generate alternatives create sub-scopes that need to be scanned
by the scope scanner in order to get function definitions etc. that
are defined lexically within generated scopes.
This patch converts a constant real index to an integer value when
defining an array. This can happen when using 2**8 which returns a
real value since the operands are signed.
draw_number_bool64() in tgt-vvp/eval_bool.c was using %ix/load to
load immediate values into registers greater than three. The problem
was that of_IX_LOAD() in vvp/vthread.cc was masking off the upper
bits. This was putting the results in the wrong register. This patch
removes the bit masking from of_IX_LOAD() and updates the %ix/load
documentation.
The file lexor.lex was beginning to suffer a catastrophic
increase in entropy due mainly to the mingling of spaces
and tabs--an age-old problem that often finds itself as
the subject of many a religious war.
The key rule: Make it consistent in as many editors as
possible; this was achieved by converting all hard tabs
into soft tabs (composed of spaces) of width 4.
I couldn't help but make modifications to the code as I
tabifified, but most of the changes are strictly style.
While maintainers generally treat large scale whitespace and
formatting changes with much caution, I believe that the code
is now much more maintainable; moreover, the test suite
produces the same results as before.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
Macro names cannot be compiler directive names.
Such trespasses are now recognized and reported:
(1) Offending `define lines are skipped.
(2) Offending macros meant to be expanded
are replaced with nothing.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
Move the storage of wires (signals) out of the Module class into
the PScope base class, and instead of putting the PWires all into
the Module object, distribute them into the various lexical scopes
(derived from PScope) so that the wire names do not need to carry
scope information.
This required some rewiring of elaboration of signals, and rewriting
of lexical scope handling.
The ordering of the logic was a little strange before.
Also, there were unnecessary operations, like the assert
and the include_dir[0]=0 business.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
Discussions online and "standards" documents are never
conclusive, but the code that was present suggests that
iverilog adopts the sane practice of resolving relative
paths against the directory of the file that is currently
being processed.
Unfortunately, when a relative path is made absolute, the
code forgot to update the necessary include_stack_t object.
This has now been fixed.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
When the lexical analyzer encounters and EOF, the
analyzer invokes yywrap() to determine what to do
next. The function determines one of two paths of
execution:
(1) If yywrap() returns 0, then the analyzer
assumes that yywrap() has setup a new input
source, and so scanning continues.
(2) If yywrap() returns non-zero, then the analyzer
assumes that yywrap() has not setup a new input
source, and so the analyzer proceeds to run the
matching EOF action (the default of which invokes
yyterminate()).
NOTE: The analyzer does not touch the start condition.
The old implementation was using yywrap() to destroy the current
input source and setup the next one. However, this causes problems
when the analyzer is in the middle of parsing some directive:
(1) Because yywrap() is called before any EOF action,
the include_stack_t structure is destroyed before
being used in the EOF action; the result is a segfault.
(2) Because yywrap() does not change the start condition,
any EOF action would occur completely out of context;
however, because of (1), this problem never cropped
up.
The new implementation simply:
(1) Employs "%option noyywrap", which effectively causes
the analyzer to act as though yywrap() produces a non-zero.
(2) Renames yywrap "load_next_input".
(3) Calls load_next_input() explicitly in exhaustive EOF actions,
so that control is more fine grained.
The added benefit is that the code that finishes parsing EOF terminated
directives now works properly; `include and `define directives previously
segfaulted in such situations.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
This variable was used in yywrap purportedly to obviate
hidden access to a file that should be closable.
After investigating the code flex produces, it would
seem that these fears are unfounded.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
The verilog preprocessing language is sufficiently simple
that the parser may be implemented by hand on top of the
lexical analyzer.
In fact, ivlpp was already implemented in this way; relevant
[bison] parser files specified no grammar, and the parser
entry-point (yyparse) was simply an indirect use of the lexical
analyzer (yylex).
Therefore, parse.y has been removed, invocations of yyparse()
have been replaced by yylex(), references to bison generated
files have been removed, and Makefile.in has been updated
accordingly.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
This patch fixes two problems. The first is that thr_check_addr()
was being used inconsistently. It should be passed a real address,
but the resize of the vector should be at least one more than this
address. The extra and unneeded CPU_WORD_BITS was also removed
from the routine.
The second problem involved an invalid memory access in
vvp_vector4_t::set_vec() when the vector being copied was an integer
multiple of the machine word width. Under this condition there would
be no remaining bits that needed to be copied but the routine was always
trying to copying some remaining bits. This code is now only executed
when there is a remainder.
Neither of these appear to be causing runtime problems. The second one
was found with valgrind. The first were found while tracking down the
second problem.
All the pform objects that represent lexical scope now are derived
from the PScope class, and are kept in a lexical_scope table so that
the scope can be managed.
This patch adds support for delaying constants at time zero. It also
cleans up the code in elab_net.cc to use this capability instead of
building it with an extra BUFZ to carry the delay information.
Modules, functions and tasks are named scopes so derive them all
from the PScope base class. These items all take scoped items, so
the eventual plan is to move these items into PScope.
This patch adds a real error message instead of an assert when
someone attempts to release a part or bit select. I plan to work
on the real functionality soon.
This patch adds the power operator for signed bit based values
in a continuous assignment. It also fixes a few other power
expression width problems. The expression width is still not
calculated correctly, since the correct method can produce huge
possible bit widths. The result is currently limited to the width
of the native long. This is because lround() is used to convert
from a double to an integer. A check in the code generator protects
the runtime from this limitation.
Generate case is a complex generate scheme where the items are
sub-schemes of the case generate itself. The parser handles them
something like nested generate statements, but storing the case
guards as the test expression. Then the elaborator notes the
case scheme and reaches into the case item schemes inside to make
up tests, select the generate item, and elaborate.
This patch adds the power operator for unsigned bit based values
in a continuous assignment. It also refactors the power code for
normal expressions and continuous assignments.
User functions called in a continuous assignment were not getting
their scope mangled. This is needed to handle arrayed instances and
possibly other things.
This patch fixes some bugs in the implementation of signed integer
division with wide operands in constant expressions and adds support
for signed integer modulus with wide operands in constant expressions.
It also removes a few redundant lines of code.
Incorrect trimming of unsigned verinum values was causing the
compilers unsigned constant verinum pow function to give
incorrect results. This patch restores the pow compile time
optimization and fixes the trimming to always leave a single
zero in the MSB.
This patch adds bit based power support to normal expressions.
It also pushes the constant unsigned bit based calculation to
the runtime until the bit based method can be copied to the
compiler. Continuous assignments also need to use this type
of calculation.
Currently, if a localparam declaration does not include a type or
range, the RHS expression is cast to an unsigned value. This patch
changes this to make the localparam inherit the type of the RHS
expression, as is done for parameter declarations and is specified
by the Verilog-2001 standard.
This patch adds a check and prints a warning message when the power
operator is used with unsigned bit based values. It also fixes a couple
of typos and adds an asserts if the above power operator happens to
get to the tgt-vvp back end.
Fallout from me trying to understand the origin of pr1780480
and pr1830834. Too bad I don't understand c++ and vvp as
well as I understand English!
(Spelling and grammer fixes in comments. -ed.)
vvp/main.cc was including asm/page.h on GNU/Linux
systems, though that file does not often exist and
is not necessary.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
Padding and continuous assignment caused problems if the continuous
assignment includes a delay. The problem is that the padding was
not necessarily included in the delay. Rework the elaboration to
make sure the padding is indeed included in the delay.
This patch adds some checks to verify that shifts, the reduction
operators and the bit wise operators are not used with real values.
It also includes a few other cleanups.
This patch makes sure the delay is calculated correctly when only some
of the bits change and you are comparing against the initial (t0) value.
Basically you have to check the initial value against all the bits in
the new signal not just the first bit since the order that bits change
is not deterministic.
This patch add delays in continuous assignments for the shift operators,
concatenations and replications. It also reports an error if the user
attempts to take the modulus of a real value.
This patch uncovers a couple other problems in the system. I am trying
to fix one of them. I will report the other problem shortly.
This patch fixes some of the delays in bit based continuous
assignments (unary -, unary +constants, string constants,
reduction operators and user functions).
Use draw_lpm_output_delay() in all functions that need it.
Addresses pr1879226 on a couple of levels. Analysis:
NetNet* PEBinary::elaborate_net_shift_() didn't flag dist==lwidth
as a case where all bits of the input are shifted away, which made
it create a real concatenator for this case. It attempted to create
NetNet*tmp with zero width, which doesn't work; (lsb,msb) ends up
as (0,-1), which is later interpreted as a 2-bit wide net.
Added an assert to the NetNet constructor to catch any other lurking
attempts to create zero-width nets.
Added short-circuit code to handle the case where all bits of the input
are shifted away. This case used to be "handled" by an assert failure.
When used in continuous assignments, user defined functions may have
delayed output. Handle that by generating the proper .delay node when
needed to delay the output of a .ufunc node.
Allow user defined functions to take real value arguments and return
real value results in net contexts. Use the data type of the nets
attached to the ports to define the data types of the arguments and
return value.
There was much redundant code in the compile-tile handling of the
less-then and greater-then of constant expressions, and much of it
was buggy. Unify much of the code and squeeze out the bugs so that
compile-time evaluations come out correctly.
The compiler attempts to precalculate the results of <= comparisons.
Fix a few corner cases where the arguments are signed. Also fix the
important test of constant against non-constant where we try to test
if the non-constant value can possibly make the test fail.
When conditional delays are in use, it is sometimes possible for there
to be no delays available for a given input event. In that case, skip
the delay processing for that case instead of crashing.
Previously only the logical operators (~, &, |, ^, etc.) supported a
delayed value in a continuous assignment. This patch should extend this
to all operators. An extensive check of real values was done. The same
will be done shortly for bit based nets.
Checks for constructs currently unsupported in continuous assignments
provide a more explicit message (** operator, real user functions,
{!, && and ||} operators with a real argument).
Rework the encoding of a real value in the Cr<> label to be similar to
the format used by the %loadi/wr instruction. This mantissa-expoment
format better carries all the bits of the desired real value with
plenty of fidelity and range.
The continuous assignment multiply expands vectors to the sum
of the two widths. This is correct for bit based vectors, but
for real variables it should always be one bit wide.
The sys_funcs table should be left to those functions that are handled
internally by the compiler. Really, the internal sys_funcs table is a
legacy from the days before the compiler supported system function
tables in the .sft format.
System functions used in a continuous assignment must be defined
in the system function table since the name of the system functions
is kept in this definition. The default name is NULL which causes
problems. This patch add $rtoi to the system table and adds a check
for a NULL name.
The comment that shows the intended value for real constants was
being printed with a %f. This is wrong for large or small values.
This patch changes the %f to a %g to get more consistent results.
A right shift may generate extra bits to preserve the proper shift
characteristic. This patch replaces the assert that was forcing the
input vector to not be greater than the input port width with code
to only select the required lower bits from the vector if it is
larger than the input port.
This patch adds support for the following statement:
<vector>[<i>] <= #<delay> <value>.
It is a copy with slight modification of code from the next
else/if clause.
The nodangle functor tries to delete NetNet objects that are not used.
But NetNet objects that are addressed by a NetArrayDq should never be
dangling. So make sure the NetArrayDq marks the target NetNet correctly.
This patch adds a new opcode %load/avp0 that is used to load a
word from an array and add a value to it. %load/vp0 was
changed/fixed to do the summation at the result width not the
vector width. This allows small vectors to index large arrays with
an offset. A few errors in the opcodes.txt file were also fixed.
In nets, if system functions return a real value the function lookup
was getting the correct width, but was also setting the width to 0,
which confused down-stream net handling. Real-value system fuctions
have a width of 1. (1 real-valued scalar.)
This patch modifies the conversion functions $rtoi, $itor,
$realtobits and $bitstoreal calltf routines to be more efficient.
This is done by caching the vpiHandle to the argument in the userdata
pointer. This eliminated the need to get the argument iterator, scan
and free the iterator.
It also updates the error messages to use the new file and line
number information that is available for system functions. It also
adds a check that verifies the functions are only called with one
argument and makes the errors fatal.
This patch schedules the input value change to .sfuns calls to avoid
potential recursion problems. It also cleans up two put_value calls
that did unneeded loops when putting VectorVals and the width was
greaten than 32 bits.
This patch adds a new flag to vvp "-n" that can be used to make
$stop and hence <Control-C> act like $finish. This may be desired
when using vvp in a non-interactive environment.
tgt-vvp/eval_expr.c uninitialized variables
vpi/sys_display.c uninitialized variables
vvp/vpi_priv.cc deprecated string constant usage
vvp/vpi_vthr_vector.cc deprecated string constant usage
the last entry invokes vpip_name_string() and uses const char *
in the same way as the other 9 callers in vvp/*.cc, the only
difference is that the argument is static instead of computed.
cvs -z3 -d:pserver:anonymous@gtkwave.cvs.sourceforge.net:/cvsroot/gtkwave co -P gtkwave3
delete CVS logs embedded in files
had to add #define wave_alloca alloca to lxt2_write.h
differences remain relative to upstream .h files:
whitespace
value chosen for LXT*_WR_SYMPRIME
Regarding the latter, Tony writes "Don't worry about the .h file.
The only difference is a considerably larger initial hash size.
If this isn't a problem with Icarus now, it certainly doesn't
need to be bumped up."
Fix data type handling of module ports. When ports are declared
as ports and given data types in different statements, the parser
incorrectly (and silently) dropped the intended data type for the
default LOGIC type.
Rework the ivl_file_table_* interface to be more generic and easier
to use. Also all the vvp examples except for memory.vvp have been
fixed to run correctly with the current vvp. Someone with a bit more
experience will need to fix memory.vvp.
Add the vpiFile and vpiLineNo properties to system functions.
Most other objects have stubs that return "N/A"/0. Interactive
functions (called from the debugger) use <interactive> for the
file name.
Use the precompiled defines file support of the ivlpp preprocessor
to pass defines made in the main program to processed library modules.
In other words, a `define in the Verilog source will be visible to
library modules.
Core preprocessor support for writing out and reading precompiled
defines. The preprocessor can read initial precompiled defines from
any number of specified source files, and can write all the defines
into a specified output file.
With this change, local symbols are not emitted in the vvp target,
but are marked as local. When thus marked, the vvp run time does not
offfer any VPI access and the signals (net or var) are effectively
invisible.
Zero-based part selects are a special case that is handled with
optimized code. Properly handle the part select width to get the
desired padding.
Signed-off-by: Stephen Williams <steve@icarus.com>
The code to handle real functions using the PLI 1 interface was
missing some functionality. This patch fixes that and fixes a
bug in the veriuser.h include file.
The recent changes to vpi_get_str had a minor problem that was
causing a core dump when trying to get the vpiFullName of an
arrayed signal. Basically vpi_get_str is not reentrant so the
name must be duplicated. It must also be duplicated to work with
the free in the code (do not free a result_buf).
Add support for a default, standard, implicit include directory
in the base directory for the ivl installation, where standardized
Verilog header files may be placed.
Rework the handling of file names to use a perm_string heap to hold
the file names, instead of the custom file name heap in the lexor.
Also rename the get_line to get_fileline to reflect its real duties.
This latter chage touched a lot of files.
Gets rid of a few warning: deprecated conversion from string
constant to 'char*', follows IEEE 1364-2001C 27.10 in more cases,
and fixes at least one real bug (look at the previous use of
strdup/strcat in real_var_get_str() and signal_get_str()).
When evaluating bitwise binary expressions at compile time, get the
signed/unsigned padding correct. Pay special attention to the case
of $signed/$unsigned changing the signedness of the operand.
Prevent an overflow of command line flags if the -Wall argument
is used multiple times, and fix processing of individual flags
that may be in the beginning of the warnings flag buffer.
When user defined function calls are withing a $signed, the result
needs to be properly padded. To make this work, handle padding of
a function result exactly type the padding of a signal vector. this
is natural in that the function return value *is* in a signal vector.
This fixes pr1841300.
This patch fixes the calculation of the scope type in draw_scope.
This code is really only used in the VCD dumper so I commented it
out in the other two. The problem was that the lower scope was
used to calculate the scope type. It is also now an error to try
to draw an invalid scope type.
This patch fixes a number of problems associated with the various dumpers.
1. It catches the problem uncovered in pr1809904 and prevents the core
dumps from happening. It prints a warning message if you try to change
the file after the program has started dumping data to the file.
2. It makes all the dumpers work in the same manner. Before the VCD
$dumpfile was processed at compile time, but the LXT/LXT2 versions
did this at run time. The correct place for this is the run time so
that you can pass the task a calculated name.
3. All the dumpers use common compiletf routines located in vcd_priv.c
4. Make the LXT/LXT2 $dumpfile commands only get the file name and
let $dumpvars actually open the file. This matches the VCD code.
5. Fix the $dumpfile code to allow calculated file names.
6. Make dumpvars without a scope/variable match all toplevel modules
not just the toplevel module the $dumpvars was located in. This
now matches the standard (2001).
7. Simplify the no dumper code (vcdoff.c) and add missing functions.
8. Cleanup the code and messages.
9. vvp can take -none for no dumper.
This patch fixes another minor problem introduced by the process
end of simulation events. Specifically if the compilation has
indicated we should not run do not even start the main event loop.
Parse SDF file annotations of edge sensitive delay paths.
Add vpi support for getting the specified edge sensitivity of
an edge sensitive path, and annotate paths with proper attention
to the edge that is specified for the path.
When loading a part select from the least significant bits, it is
OK to use the %load/v instruction to strip the high bits off. This
allows the zero-based part select to work in one step, without
loading excess bits.
Some patch caused a variable that held the constant base of a part
select to become unassigned. This led to unexplained failures to part
select a signal. Fix by properly detecting the case of a constant base
of 0 for the part select.
The %ix/getv instruction loads an integer register directly from
a signal vector. This is an optimization that an index register
is loaded from an expression is only a signal. It avoids the thread
vector space.
Using the parser supplied error token to get file and line number
information appears to give incorrect results at best and core dump
at worst. This patch uses the closest real token that makes sense
to alleviate this problem.
Use the new array VPI functionality (vpiIndex, vpiParent, vpiArray)
to dynamically generate array word names. The old patch to implement
was mostly reverted.
Add the array related VPI calls. These will be used to generate
the array word name only as needed to conserve space. This patch
also makes scanmem3 from the vpi test work correctly after a
slight gold file update.
Where and expression is an immediate value added to a signal value,
it is possible to optimize them to a single instruction that combines
the load with an add at the same time.
The patch for adding support for macros with arguments contained
a leftover debugging aid. This patch corrects the code. It also
should eliminate some compilation warnings.
The functor counters were left over from the v0.8 release. Rework
the counters to be relevent to the current state of vvp.
Signed-off-by: Stephen Williams <steve@icarus.com>
This patch modifies the preprocessor to handle text macros with
arguments. It also fixes a bug that prevented a `line directive
being issued after a multi-line text macro had been instantiated.
The second argument of $sdf_annotate is the scope that is to be
annotated. The argument is optional, and the default is to annotate
the current scope, where the $sdf_annotate is invoked.
Signed-off-by: Stephen Williams <steve@icarus.com>
This patch adds a -D option to iverilog-vpi and updates the manual
page to document this option and some others that were missing.
From c7347239335558b26c873ea5e64d278d1feff38a Mon Sep 17 00:00:00 2001
From: Cary R <cygcary@yahoo.com>
Date: Thu, 29 Nov 2007 10:31:25 -0800
Subject: [PATCH] LD should be based on $CC and not hardcoded to gcc
Fix the default loader so it will be whatever the default C
compiler is ($CC).
---
iverilog-vpi.sh | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/iverilog-vpi.sh b/iverilog-vpi.sh
index fbccedb..d2512cc 100644
--- a/iverilog-vpi.sh
+++ b/iverilog-vpi.sh
@@ -25,7 +25,7 @@ CXX=@IVCXX@
CFLAGS="@PIC@ @IVCFLAGS@ -I@INCLUDEDIR@"
# These are used for linking...
-LD=gcc
+LD=$CC
LDFLAGS32="@SHARED@ -L@LIBDIR@"
LDFLAGS64="@SHARED@ -L@LIBDIR64@"
LDFLAGS="$LDFLAGS64"
--
1.5.3.4
Handle the special case that the SDF CELL instance is empty. In this
case, the SDF file is requesting the current scope instead of an
instance within the scope.
Signed-off-by: Stephen Williams <steve@icarus.com>
the lexor didn't allow numbers in the IDENTIFIER name,
and the parser wasn't very nice with IDENTIFIER errors.
Signed-off-by: Stephen Williams <steve@icarus.com>
This patch adds the ability to dump array words. The words are only
dumped if they appear in a $dumpvars() statement (they are not dumped
by default). The name used for the word is <array_name>[<index>], so
you can get unexpected name conflicts.
There is also a slight increase in the memory requirements since each
array word now keeps its own name information. In the future we would
like to change this, but that is a much larger rewrite of the array
code in vvp.
This patch also needs the "Prefix escaped identifier ..." patch to
work correctly (the array word name is an escaped identifier).
Comparison operands are signed only of both operands are signed.
If one is unsigned, then they both are unsigned. This does not
affect the signedness of the comparison itself, which is unsigned.
Signed-off-by: Stephen Williams <steve@icarus.com>
Implement extended vvp command line options to control the amount
of detail that the sdf annotator emits while parsing the source
file.
Signed-off-by: Stephen Williams <steve@icarus.com>
Pass parsed SDF delays into the vvp run time as vpiScaledRealTime
variables, and handling the mapping of 2-values to 12-delays.
Signed-off-by: Stephen Williams <steve@icarus.com>
The LXT and LXT2 formats ignore/work with duplicate variables in
$dumpvars() commands, but VCD output includes extra definitions that
may cause some confusion. This patch checks for duplicates and prints
a warning when they are being suppressed.
It also corrects some error messages in the LXT and LXT2 files to not
reference VCD and some other message cleanup.
The min/typ/max default warning was not being produced in all
locations a min/typ/max expression could be used. This patch
adds the default warning code to all locations. It also
modifies the manual page to explicitly state that only the
first ten warnings are printed.
GTKWave needs to have escaped identifiers properly escaped (preceded
with a back slash) in its VCD input. Without this the name may not
display correctly. Even though it is not required, to keep things
consistent LXT and LXT2 formats also prefix escaped identifiers with
a back slash.
This patch causes unnamed generate blocks to be automatically named
using the naming scheme defined in the Verilog-2005 standard. This
is a fix for the problem discussed in pr1821610.
This patch cleans up some of the crashes in the synthesis
code by incrementing the error count as appropriate. This
also removes the three false positives in the test suite
(Sorry-Ran-PASSED). A few other messages will change in
the test suite as well (blocksynth? and basiclatch).
This was causing a core dump for a number of the vpi test cases.
The problem was that they did not need the simulation time, so it
was being set to NULL. The problem was the EndOfSimulation callback
was always setting cb_data.time to the current time. A big problem
when the pointer was NULL. The solution is to only set the time
when the pointer is not NULL
During elaboration certain constants were getting extended with
the MSB. This patch makes that happen only if the constant does
not have a length. At this point most should have a length so
effectively every unsigned value is extended with 0.
For text macro substitutions the lexor did not allow leading underscores.
This patch fixes that omission. All other places that text macros may be
used appear to be correct.
Most types in Icarus support a single array dimension (reals do
not support arrays at all). If you try to use an invalid number
of dimensions the parser will now display an error message.
String values are known to be 2-value bits, so they are natural
candidates for using the movi instruction to load the value in
far fewer instructions. With this patch, up to 16bits (two bytes)
at a time can be loaded per instruction.
Signed-off-by: Stephen Williams <steve@icarus.com>
tgt-vvp was taking strings and processing them as is, but the strings
could contain octal constants. These constants needed to be converted
to binary form before they could be turned into a bit pattern.
CMOS gates like NMOS and PMOS have a strength aware output.
They were missed when the NMOS and PMOS were fixed. "cmos.v"
will now pass in the test suite.
A previous patch I submitted to try and keep the $finish time
events missed the case of an infinite loop that did not advance
the micro time step which then prevents the debugger from
generating a finish (you can interrupt an infinite loop, but you
could not finish out of it). This patch adds a check for a
finish after each debugger call to fix this problem.
When nets are forced by non-constant expressions, the value is linked
to the destination net through a force_link. This patch adds the code
needed to unlink a force/link so that release and new force/links can
work. This fixes pr1735836.
Signed-off-by: Stephen Williams <steve@icarus.com>
This patch adds marks at simulation end if needed and enabled (on
and not over the limit) for vcd/lxt/lxt2 files. End of simulation
callbacks also now have the correct simulation time. The default
file names for lxt and lxt2 now match the vcd file except for the
extension. lx2 is also an alias for lxt2 and the default lxt2 file
extension is lx2. This matches what GTKWave expects. Any lxt2
diagnostic output print LXT2 instead of LXT to make it clear which
dumper you are using.
Handle arithmetic right shift during compile time. This comes
up with both the operands are constant expressions. the compiler
is able to evaluate this down to a constant to replace the
expression.
Signed-off-by: Stephen Williams <steve@icarus.com>
Here are some more array fixes. They are mostly better error messages
instead of just asserting and some code cleanup. The one new thing
that probably should have been a separate submission is that down
indexed part select [base -: width] can now be a lvalue.
This patch fixes/enhances the array part select code. It also
verifies that any lval array index in a continuous assignment
is a constant value. Also, %set/av now uses index register 1 as
described in the documentation (as a bit offset).
@* was only expanding to input nets. nex_input() for blocks was removing
any output net that was also an input. There was also a bug in how output
nets were removed. Only outputs currently defined were removed from the
input list.
always @(*) begin
y = a;
z = y;
end
would report "a" as an input. While
always @(*) begin
z = y;
y = a;
end
would report both "a" and "y" as inputs.
To fix this all nex_inputs now take a flag that when true (the default)
correctly removes any output from the input list. Both the above cases
will now return "a". If the flag is false outputs which are also inputs
will be included in the input list. This is what the @* elaboration code
uses to get the correct sensitivity list.
Add/rework VPI access to modpaths. This allows VPI code access to
paths described in specify blocks. In the process, the VPI structure
has been reworked to conform to the IEEE1364 standard.
Signed-off-by: Stephen Williams <steve@icarus.com>
Cleanup klunky implementation of vpi_get/put_delays for modpath
objects. Remove some useless members.
Signed-off-by: Stephen Williams <steve@icarus.com>
Wide division/modulus (more bits than unsigned long) gave incorrect
results when both the divisor and dividend where the same. They also
did not produce an error message when dividing by zero.
This patch enhances the current fflush implementation to flush a mcd or an
individual fd. Before it always flushed everything. A compiletf routine was
also added.
The modpath source node defines the modpath object, and carries the
nodes for the source expression. The modpath outputs are references
by pointers to the vpiModPath that is not in itself a vpi object
any more. This makes the VPI view of a module path look like the
source-destinaiton pair that is the IEEE1364 description of the
modpath.
Add vvp support for modpath path term outputs. This also introduces
the concept of path terms and moves towards the path term in general
for getting at the endpoits of a modpath.
Modpaths need to be in the proper scope in order to be available to
vpi functions. The code generator manages that by writing the modpath
records with scope switch functions. Batch the modpath records at the
end of the structural stuff so that the scope switching doesn't cause
trouble.
Also seperate the modpath code into its own source file.
Signed-off-by: Stephen Williams <steve@icarus.com>
Delay paths need a scope. This helps the code generators bind the
modpaths to the correct scope. This patch doesn't actually make use
of the information, it just makes it available to code generators.
Signed-off-by: Stephen Williams <steve@icarus.com>
Clean up rather poorly written modpath vpi support, fixing the
parse of the modpath syntax element to not use pointless globals.
Collect the modpath code into the delay.cc file instead of the
inapropriate vpi_signal.cc source file.
Signed-off-by: Stephen Williams <steve@icarus.com>
The << operator may not be defined when the RHS is greater than or
equal to the LHS width. To work around the problem the mask is
incrementally generated.
There have been reports in the field of number-to-real conversions
doing bad things with the calculated mantissa. This patch eliminates
a opssible portability problem by reworking the negating of negative
mantissa values.
Signed-off-by: Stephen Williams <steve@icarus.com>
Print out a warning if extra digits are given for sized binary, octal
or hex constants. Decimal constants are very hard since we never
calculate the true number of bits the digits represent, so for now
decimal constants are not checked.
The attached patch add an implementation for $dumplimit(). It does
not do a hard limit to the file size, but for VCD files it completes
the current time step and puts a comment in the file. For lxt and
lxt2 files the functionality is in place, but because of buffering
the file can be slightly larger than expected.
Factor common code for processing signed constants to be padded.
In the process, fix some minor bugs in the padding decisions.
Signed-off-by: Stephen Williams <steve@icarus.com>
Fixed some signed/unsigned warnings, including one that caused an
actual runtime error if not dealt with safely.
Signed-off-by: Stephen Williams <steve@icarus.com>
The argument to $unsigned is self-determined no matter what the
context the $unsigned itself is in. This is important only where
the result can be negative but the result width is context-determined.
Do ocntext fitting manually to prevent the context fitting it and
affecting the expression argument.
Signed-off-by: Stephen Williams <steve@icarus.com>
This patch implements the System Verilog $urandom() and $urandom_range()
functions. There are no check to verify that $urandom_range is only given
unsigned arguments. If you give it a negative value the bit pattern will
be interpreted as a unsigned number.
Fix the handling of expressions that have unsized integers and are
in self determined context. Unsized integers are generally assumed
to have at least 32bits.
Signed-off-by: Stephen Williams <steve@icarus.com>
Constant propagation incorrectly elided an entire constant net node
if only the LSB of the driven vector was HiZ. This caused the entire
vector to look like HiZ. Also, the code generator for writing the
constant values missed bits.
Signed-off-by: Stephen Williams <steve@icarus.com>
signed compare in proceedural code was comparing the absolute
value if both operands were negative. Wrong!
Signed-off-by: Stephen Williams <steve@icarus.com>
Implement compare-immediate instructions and generate code to use
these new instructions to improve runtime performance.
Signed-off-by: Stephen Williams <steve@icarus.com>
This patch adds the ability to call command files from other command
files. There is currently a limit of 16 total levels deep (15 stored
plus the current file). -f is now an alias for -c for both the command
line and command files. The parser also reports errors when they occur
along with the file name and line number to aid in debugging problems.
In expressions, user defined functions have a clearly defined
width and the test_width expression needs to express that. Note
that the $signed/$unsigned functions are special and magical.
Signed-off-by: Stephen Williams <steve@icarus.com>
Variable word addresses are not to be adjusted by the bit select
of the vector direction. That is a holdover from when arrays were
stored as bit vectors.
Signed-off-by: Stephen Williams <steve@icarus.com>
This patch adds ivl_scope_time_precision() to the compiler which can
be used to extract the local scope precision. tgt-stub and tgt-vvp
have been modified to use this new function and output a value that
is appropriate. The vvp runtime has been altered to use this new
data which is accessed with the vpip_time_precision_from_handle()
function. vpiTimePrecision uses this function to return the correct
precision.
The outputs to bufif and nmos/pmos devices are always strength-aware,
so should have their outputs connected to a net8 device.
Signed-off-by: Stephen Williams <steve@icarus.com>
This patch adds min_typ_max to expressions. Remember when using a
min_typ_max triplet in an expression they must be enclosed with
parenthesis (1364-2001 section 4.3 page 58).
Add support for accessing the modpath nodes via PLI,
and add support for the vpi_set_delays and vpi_put_delays
functions to set the delays on those paths.
- GSoC 2007
It is legal in Verilog to bind expressions to ports that do not
match the port width. Icarus Verilog needs to create the necessary
part selects to get the connections right.
Signed-off-by: Stephen Williams <steve@icarus.com>
Add code to handle all the primitives currently defined and
fixed a power of ten error in the time units display (it is
either 10^{units} or 1e{units}, but not 10e{units}).
This patch adds functionality to verify that primitives are given
an appropriate number of ports. For multiple output gates (but,
not, pulldown, pullup) it also reports that Icarus currently does
not support multiple outputs when more than one is given.
When a repeat concatenation expression is translated to a netlist,
get the repeat expression right. This comes up when an elab_and_eval
elaboration contains a repeat concationation, and the expression is
ultimately turned into a netlist by expr_synth.
Signed-off-by: Stephen Williams <steve@icarus.com>
Signed divide of 32bit values can overflow if done in a 32bit long
due to the truncation of sign bits. So use the large value algorithm
if the values are >= 31 bits (63 bits on 64bit machines).
Signed-off-by: Stephen Williams <steve@icarus.com>
This patch adds checks to verify that functions do not invoke
statements that are invalid for them (#, @, wait, enable/call
tasks and non blocking assignment). For reference see section
10.3.4 of 1364-2001.
C style comments were not recognized as comments in false or
suppressed sections of ifdef/etc. blocks. This prohibited an
unneeded endif/else/etc. from being commented out with this
style of comment.
I decided not to delete these since we may at some point in time want
this functionality back. For now they are commented out with an
explanation so we know what is going on.
This patch splits the end of compile and the start of simulation call
backs code into two different procedures. The end of compile events are
still executed at the same time they alway were. The start of simulation
events are now run after initialization.
The event loop used to check for $finish at every iteration. This patch
alters this behavior to only check just before you advance to the next
time step. This allows events for the current time step to complete.
Modified the code that deals with real variables to accept an integer
value when using vpi_put_value(). Also added some type of diagnostic
message for all switch defaults that have an assert(0) to indicate an
error condition, removed CVS comments and removed a small section of
unreachable code.
Modified the code that deals with real variables to accept an integer
value when using vpi_put_value(). Also added some type of diagnostic
message for all switch defaults that have an assert(0) to indicate an
error condition, removed CVS comments and removed a small section of
unreachable code.
Previously list of port declarations were considered a complete
definition of the port. This caused problems for some, so this patch
allows implicitly defined ports (no wire/reg/etc.) to have net
declarations in the body.
This would have never been a problem with the actual circuit generated.
The problem was that the assert was checking values that had never been
set. The constructor now explicitly sets these values to zero and while
I was at it I added a couple more asserts.
This patch is rather large and fixes a couple of problems. The major
change is that instead of keeping all the range specifications in
a list that is later processed the information is now kept as
individual entries for the port and net definitions. This allows
easier checking for multiple definitions (pr1660028), more
detailed error messages and the ability to pass the now deprecated
style of a scalar I/O definition used with a vectored net definition.
These changes did require extra code to prevent a single definition
from setting the range values in more than on place.
When using the new ANSI-C style of port declarations (1364-2001 12.3.4
list_of_port_declarations) the compiler ensures that you do not
redeclare the port in the body (it is already completely defined).
This caught a few errors in the test suite (pr859 and sqrt32*).
The flag to disable the normal port checking and allow the deprecated
port syntax is -gno-io-range-error. This will print a warning for the
case of a scalar port with a vectored definition in the body. All
other cases are still considered an error.
This patch adds better checking for a missing endmodule or an attempt
to nest modules. A more descriptive message is printed and the location
of the original module definition is printed.
It is possible for the compiler to generate logic gates that have
inputs from part select nodes. This implements the part select
input methods.
Signed-off-by: Stephen Williams <steve@icarus.com>
This patch fixes an incorrect optimization that was skipping a
call to set the port width when there was no width (a scalar).
The problem with this is that since a (0,0) pair was not added
to the list, later when the width was define to (1,0) the checking
code did not have the (0,0) to tell that there was a mismatch in
the port size. Section 12.3.3 States that the two sizes shall be
identical, so yes this is an error even though it is very minor.
This patch makes vpiFullName for real variables return the correct
value. A Scope reference was added to the base structure along with
the relevant code to support generating the full name. A couple of
memory leaks were plugged and some formatting fixed as well.
It appears that other simulators allow the second argument to
vpi_handle_by_name to be either a scope or a module. Allowing
a module in addition to a scope significantly increases the
usability of this function.
vpi_get_str() can now return a reasonable value for most of the
types used in vvp. I'm not certain I got all of them, but they
are easy to add if any are missing. I also fixed a couple of
typos that I found while looking for all the different types.
Real value constants have width 1 in Icarus Verilog. This is not
the same as the output from $bitstoreal, which is *not* a real
valued expression but a logic vector that losslessly carries the
real value.
Also remove unused CVS markings.
Signed-off-by: Stephen Williams <steve@icarus.com>
This patch adds the missing vpiFullName property to binary and
string parameters (FYI real parameters are not currently supported
by the VPI interface).
This patch implements the swrite* and sformat system tasks. It also
makes $simtime distinguishable from the other integer time tasks.
This was needed to get the correct time units when $simtime was given
as an argument to $swrite*. The string constant code was also modified
to allow a string to be returned as a vector (0/1 bit pattern).
Here are some more specifics about the swrite* changes.
1. They do not share formatting code with the other display functions,
so they may/will produce different results.
2. All %{alpha} codes allow a width and justification. Others have been
enhanced (%t allows the default width and precision to be overridden,
time functions print with time formatting, better error checking and
messages, etc.).
3. %u and %z formatting codes have been added. It is important to note
that these two formats can produce embedded NULLs, since these
functions are returning a string anything after the first NULL will
not be reachable! memcpy is used instead of regular string processing
where needed so that the original string will contain the total
result. The size returned when the string is created is the true
length. A warning will be printed if a string with embedded NULLs is
produced (strlen() does not match the true length).
4. Real numbers are printed with %g instead of %f.
Once this new formatting code has been evaluated we should incorporate
the changes/fixes into the formatting code for the other functions or
the other functions could be modified to use this new code. The true
string length is available so we should be able to work around the
embedded NULL problem.
The calculated return value for the calculated strength value of
a net was left dangling. This patch fixes that. See pr1770199 in
the regression test suite.
Signed-off-by: Stephen Williams <steve@icarus.com>
distinguish between self-determined and value-preserving when
evaluating constants that are arguments to concatenations.
Signed-off-by: Stephen Williams <steve@icarus.com>
Support initialization assignments of real value variables. In the
process, clean up the processing of real variable declarations in
the parser.
Signed-off-by: Stephen Williams <steve@icarus.com>
The standard states that the seed for the random functions should be
an integer/time variable or a register. This patch fixes the compiletf
routines to check for this. There is also a small patch to
vvp/vpi_signal.cc that removes an assert that was failing and replaces
it with appropriate code. The assert was verifying that the source was
not bigger than an integer. The problem with this is that a time
variable or register may be bigger than an integer. I altered the code
to remove the assert and copy only the lower (8 * sizeof integer) bits.
The potential overflow/loss of precision is not checked. This passes
the regression tests.
Delat the compiletf calls until after all the label references
are resolved and link bindings are complete. Otherwise, there may
be dangling references.
Signed-off-by: Stephen Williams <steve@icarus.com>
This patch adds a compiletf routine to the $deposit system task and
simplifies the calltf routine. It also patches the constant string code
to return an appropriate integer value when needed. A number of compiletf
routines that check for this can now be simplified since this (string
constants) no longer causes an assert in an integer environment.
Better handle cases where the scope part of a heirarchical name does
not match any existing scope, or where scope index expressions are
not correct.
Signed-off-by: Stephen Williams <steve@icarus.com>
In rare cases, the reduction logic nodes may get vector part inputs.
This patch adds support for vector parts entering a reduction node.
Signed-off-by: Stephen Williams <steve@icarus.com>
This fixes r-value type references to memory words for memories
that have a non-zero base address. Elaborate the expression
needed to get the canonical word index.
The port input count assertion was triggering incorrectly. It was
comparing the count with the bytes instead of bits in a word.
Signed-off-by: Stephen Williams <steve@icarus.com>
The argument passed to $finish and $stop is not currently used, but it
is now passed down to the functions that may someday do something
useful with it (schedule_finish() and schedule_stop() in vvp/schedule.cc).
Add the missing probabilistic functions and add compiletf routines
for all the functions. The original calltf routines have been
modified as appropriate. The base functions are straight copies
from the standard. I have visually verified the curves with 5,000
points and they look correct.
Even though vpiFinish does not currently do anything with it's
argument I thought it would be best to have them all be in the
correct range [0, 1, 2], so they have been updated as appropriate.
Handle real valued expressions in vector declarations. Also clean
up the handling of vector declaration expressions.
Signed-off-by: Stephen Williams <steve@icarus.com>
Nil parameter overrides can turn up in positional paramter override
lists, where items are intentionally skipped.
Signed-off-by: Stephen Williams <steve@icarus.com>
Be careful to include bitwise differences in double values, because
it is the bit pattern we are passing aroung, not the arithmetic value.
Signed-off-by: Stephen Williams <steve@icarus.com>
The runtime is a vvp runtime engine debug aid that allows for
detailed dump into a debug log. The trace is enabled by setting
the VVP_DEBUG variable and activating specific debug messages
in the vvp source.
Signed-off-by: Stephen Williams <steve@icarus.com>
Make varable drivers (reg vectors and real) propagate their initial
values using a special init scheduler queue. This causes the net to
be loaded with reasonable initial values.
Signed-off-by: Stephen Williams <steve@icarus.com>
Non-constant indexed part select in continuous assignment generates
a select node with the correct width. In the process factor out and
share some of the part select calculations with expr part select
handling methods.
Signed-off-by: Stephen Williams <steve@icarus.com>
Words of net arrays were incorrectly added to the scope. They should
only be attached to the array, and accessed as a word of the array.
Signed-off-by: Stephen Williams <steve@icarus.com>
Real value are vector width of 1, fix real literal to reflect this.
fix leaking real registers in code generation for function arguments.
Load of signal should handle conversion from real to vector. Function
arguments, type vector passed a real value, are an example where this
comes up.
Signed-off-by: Stephen Williams <steve@icarus.com>
Backslash-escapes are processed early, during elaboration, so that
escaped characters show up in all places with the calculated value.
This means the $display formatting will get processed strings and
should not process back-slashes again.
Signed-off-by: Stephen Williams <steve@icarus.com>
Parameter expressions that do not otherwise have a size should
evaluate expressions losslessly, expanding as necessary to prevent
overflow of data.
Signed-off-by: Stephen Williams <steve@icarus.com>
Arrays of nets that have all their words collapsed together can become
a collapsed array as a whole. Add support for this case in the vvp code
generator and runtime.
more general concept of arrays. The NetMemory and NetEMemory
classes are removed from the ivl core program, and the IVL_LPM_RAM
lpm type is removed from the ivl_target API.
including assing, cassign and force.
Generate NetConcat devices for gate outputs that feed into a
vector results. Use this to hande gate arrays. Also let gate
arrays handle vectors of gates when the outputs allow for it.
Add a vvp_event_anyedge class to handle the special
case of .event statements of edge type. This also
frees the posedge/negedge types to handle all 4 inputs.
Implement table functor recv_vec4 method to receive
and process vectors.
* The only known breaking change is that wires must now be declared before use; which is required in the standard (see `gh1287 <https://github.com/steveicarus/iverilog/issues/1287>`__).
----
🙏 Acknowledgments
------------------
We thank all contributors who reported issues, submitted patches, expanded regression coverage, and
improved documentation. Release 13 reflects continued community effort toward improving correctness,
The sizer target does not generate any code. Instead it will print statistics about the Verilog code.
It is important to synthesize the Verilog code before invoking the sizer. This can be done with the `-S` flag passed to iverilog. Note, that behavioral code can not be synthesized and will generate a warning when passed to the sizer.
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
"hello_world.v";
The first line contains the shebang. If this file is executed, the shebang tells the shell to use vvp for the execution of this file.
To run the simulation, execute::
% ./top.vvp
Or you can call vvp directly::
% vvp top.vvp
Next are some directives. The first one, `:ivl_version` specifies which version of iverilog this file was created with. Next is the delay selection with "min:typical:max" values and the time precision, which we did not set specifically, so the default value is used. The next lines tell vvp which VPI modules to load and in which order. The next lines tell vvp which VPI modules to load and in what order. Next, a new scope is created with the `.scope` directive and the timescale is set with `.timescale`. A thread `T_0` is created that contains two instructions: `%vpi_call` executes the VPI function `$display` with the specified arguments, and `%end` terminates the simulation.
Opcodes
-------
The various available opcodes can be seen in :doc:`Opcodes <../developer/guide/vvp/opcodes>`
Cary R
mjoekhan
Lars-Peter Clausen
Ethan Sifferman
Flavien Solt
Cookie
Ralf Habacker
Haowei Hsu
Jose Tejada
Martin Whitaker
Huang Rui
Stephan I. Böttcher
Stephan I. Böttcher
أحمد المحمودي (Ahmed El-Mahmoudy)
Wilson Snyder
Oscar Gustafsson
Michael Kupfer
Andreas Lööw
Gianluca Martino
henry
Dag Lem
ga
Paul Rigge
Jevin Sweval
Flavien Solt
Stephen Williams
gatk555
Johan Euphrosine
Sylvain Munaut
Marlon James
DeflateAwning
Ernesto Sola-Thomas
mole99
Wilfried Chauveau
Mason Loyet
Srinivasan Venkataramanan
a1ca7raz
Sean Cross
Bill Lye
Bill Lye
Stephen Williams
Jonathan Kimmitt
Sean Anderson
Lloyd Parkes
Nish Tahir
Henner Zeller
Emilio Miralles
Miodrag Milanovic
Zachary Snow
Michael Singer
Martin Whitaker
Tomasz Hemperek
umarcor
Marlon James
Tim
Purdea Andrei
Denis Redozubov
Purdea Andrei
Tim Pambor
Noah Moroze
Greg Steuck
minux
Prakhar Yadav
Nick Brereton
nbrereton
Nicholas Sielicki
StefanBruens
Stefan Biereigel
Maciej Kurc
Tomasz Hemperek
martinwhitaker
Konst Mayer
Alex Forencich
Aaron Parks
Scott Mansell
Andrew Andrianov
Daniel Andrade
8tab
Mikael Tuomisalo
Vamsi Vytla
Jesús Arroyo Torrens
Johann Klammer
Udi Finkelstein
Staf Verhaegen
Henry Wong
Maciej Suminski
Thomas Fors
Yury Gribov
Wojciech M. Zabolotny
Michele Castellana
anon
Larry Doolittle
Peter Jakobsen
Christian Taedcke
Frederick C. Kurz
Martin Whitaker
Tomasz Hemperek
Todd Strader (todd.strader@gmail.com)
Colin
Clifford Wolf
Jared Casper
Arun Persaud
Andrew Stevens
Gordon McGregor
Ole Henrik Jahren
Alexander Klimov
Nick Gasson
Prasad Joshi
Pawel Szostek
Prasad Joshi
Greg Steuck
Pawel Szostek
Joe Auricchio
Patrick Doyle
Picture Elements Inc
Sreeraj R
nog
Purdea Andrei
Michael Strelnikov
Martin Whitaker
Martin Whitaker
Martin Whitaker
Holger Wächtler
Stephen Williams
GuntherDannoritzer
thiede
J Varshney
Michael
Michael Witten
Gyorgy Jeney
Martic Whitaker
yang yun ju
steve
