Spelling fixes to vhdlpp tree

Mostly comments as usual, but one error message is changed.

vhdlpp/README.txt

@@ -49,4 +49,4 @@ in your VHDL code, access packages like this:
 The *.pkg files are just VHDL code containing only the package with
 the same name. When Icarus Verilog encounters the "use <lib>.<name>.*;"
 statement, it looks for the <name>.pkg file in the <lib> library and
-parses that file to get the package header declared therin.
+parses that file to get the package header declared therein.

vhdlpp/architec_elaborate.cc

@@ -120,11 +120,11 @@ int ForGenerate::elaborate(Entity*ent, Architecture*arc)
 /*
  * This method attempts to rewrite the process content as an
  * always-@(n-edge <expr>) version of the same statement. This makes
- * for a more natural translation to verilog, if it comes to that.
+ * for a more natural translation to Verilog, if it comes to that.
  */
 int ProcessStatement::rewrite_as_always_edge_(Entity*, Architecture*)
 {
-	// If thare are multiple sensitivity expressions, I give up.
+	// If there are multiple sensitivity expressions, I give up.
       if (sensitivity_list_.size() != 1)
 	    return -1;
 

vhdlpp/entity.h

@@ -104,7 +104,7 @@ class Entity : public ComponentBase {
 
 	// After the architecture is bound, elaboration calls this
 	// method to elaborate this entity. This method arranges for
-	// elaboration to hapen all the way through the architecture
+	// elaboration to happen all the way through the architecture
 	// that is bound to this entity.
       int elaborate();
 

vhdlpp/expression.h

@@ -189,7 +189,7 @@ class ExpAggregate : public Expression {
 
 	      // true if this represents an "others" choice
 	    bool others() const;
-	      // Return expression if this reprents simple_expression.
+	      // Return expression if this represents a simple_expression.
 	    Expression*simple_expression(bool detach_flag =true);
 
 	    void dump(ostream&out, int indent) const;

vhdlpp/expression_elaborate.cc

@@ -120,7 +120,7 @@ int ExpName::elaborate_rval(Entity*ent, Architecture*arc, const InterfacePort*lv
         /* IEEE 1076-2008, p.80:
         * For a formal port IN, associated port should be IN, OUT, INOUT or BUFFER
         * For a formal port OUT, associated port should be OUT, INOUT or BUFFER
-        * For a formal port INOUT, associated prot should be OUT, INOUT or BUFFER
+        * For a formal port INOUT, associated port should be OUT, INOUT or BUFFER
         * For a formal port BUFFER, associated port should be OUT, INOUT or BUFFER
         */
         switch(lval->mode) {
@@ -193,7 +193,7 @@ int ExpBinary::elaborate_exprs(Entity*ent, Architecture*arc, const VType*ltype)
 int ExpAggregate::elaborate_expr(Entity*ent, Architecture*arc, const VType*ltype)
 {
       if (ltype == 0) {
-	    cerr << get_fileline() << ": error: Elaboration of aggregate types needs wel known type context?" << endl;
+	    cerr << get_fileline() << ": error: Elaboration of aggregate types needs well known type context?" << endl;
 	    return 1;
       }
 

vhdlpp/lexor.lex

@@ -44,10 +44,10 @@
 extern int lexor_keyword_code (const char*str, unsigned len);
 
 /*
- * Lexical location information is passed in the yylloc variable to th
+ * Lexical location information is passed in the yylloc variable to the
  * parser. The file names, strings, are kept in a list so that I can
  * re-use them. The set_file_name function will return a pointer to
- * the name as it exists in the list (and delete the passed string.)
+ * the name as it exists in the list (and delete the passed string).
  * If the name is new, it will be added to the list.
  */
 #define yylloc (*yyllocp)
@@ -89,7 +89,7 @@ based_integer		[0-9a-fA-F](_?[0-9a-fA-F])*
 [ \t\b\f\r] { ; }
 \n { yylloc.first_line += 1; }
 
-  /* Single-line comments start with - - and run to the end of the
+  /* Single-line comments start with -- and run to the end of the
      current line. These are very easy to handle. */
 
 "--".* { comment_enter = YY_START; BEGIN(LCOMMENT); }
@@ -635,7 +635,7 @@ static double make_double_from_based(char* text)
     *first_hash_ptr = '\0';
     *second_hash_ptr = '\0';
 
-    //now lets deduce the base
+    //now let's deduce the base
     unsigned base = (unsigned)strtol(text, 0, 10) ;
 
     double mantissa = 0.0;

vhdlpp/parse_api.h

@@ -25,7 +25,7 @@
 typedef void*yyscan_t;
 
 /*
- * The vlltype supports the passing of detailed source file location
+ * The yyltype supports the passing of detailed source file location
  * information between the lexical analyzer and the parser. Defining
  * YYLTYPE compels the lexor to use this type and not something other.
  */

vhdlpp/vtype.h

@@ -83,7 +83,7 @@ inline std::ostream&operator << (std::ostream&out, const VType&item)
 extern void preload_global_types(void);
 
 /*
- * This class represents the primative types that are available to the
+ * This class represents the primitive types that are available to the
  * type subsystem.
  */
 class VTypePrimitive : public VType {