Add regression tests for non-ANSI task port range mismatch

Check that when port direction and data type are declared separately that
an error is reported if the port direction has an explicit range
specification, but the data type has not. This should even be the case if
the data type has an implicit range, e.g `int` or a struct type.

For vector types also check that it is an error if the ranges are not
identical.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2022-04-12 17:10:26 +02:00
parent 521a7bea61
commit b0d328d594
12 changed files with 181 additions and 0 deletions

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@ -0,0 +1,16 @@
// Check that it is an error to declare a non-ANSI task port with implicit
// packed dimensions if it is later redeclared as an atom2 typed variable. Even
// if the size of the packed dimensions matches that of the size of the atom2
// type.
module test;
task t;
input [15:0] x;
shortint x;
$display("FAILED");
endtask
initial t(10);
endmodule

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@ -0,0 +1,19 @@
// Check that it is an error to declare a non-ANSI task port with implicit
// packed dimensions if it is later redeclared as a enum typed variable. Even if
// the size of the packed dimensions matches that of the size of the enum type.
typedef enum integer {
A, B
} T;
module test;
task t;
input [31:0] x;
T x;
$display("FAILED");
endtask
initial t(10);
endmodule

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@ -0,0 +1,16 @@
// Check that it is an error to declare a non-ANSI task port with implicit
// packed dimensions if it is later redeclared as an integer typed variable.
// Even if the size of the packed dimensions matches that of the size of the
// integer type.
module test;
task t;
input [31:0] x;
integer x;
$display("FAILED");
endtask
initial t(10);
endmodule

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@ -0,0 +1,19 @@
// Check that it is an error to declare a non-ANSI task port with implicit
// packed dimensions if it is later redeclared as a packed array typed variable.
// Even if the size of the packed dimensions matches that of the size of the
// packed array.
typedef reg [7:0] T1;
typedef T1 [3:0] T2;
module test;
task t;
input [31:0] x;
T2 x;
$display("FAILED");
endtask
initial t(10);
endmodule

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@ -0,0 +1,14 @@
// Check that it is an error to declare a non-ANSI task port with implicit
// packed dimensions if it is later redeclared as a real typed variable.
module test;
task t;
input [3:0] x;
real x;
$display("FAILED");
endtask
initial t(10);
endmodule

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@ -0,0 +1,21 @@
// Check that it is an error to declare a non-ANSI task port with implicit
// packed dimensions if it is later redeclared as a packed struct typed
// variable. Even if the size of the packed dimensions matches that of the size
// of the struct.
typedef struct packed {
reg [31:0] x;
reg [7:0] y;
} T;
module test;
task t;
input [47:0] x;
T x;
$display("FAILED");
endtask
initial t(10);
endmodule

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@ -0,0 +1,15 @@
// Check that it is an error to declare a non-ANSI task port with implicit
// packed dimensions if it is later redeclared as a time typed variable. Even if
// the size of the packed dimensions matches that of the size of the time type.
module test;
task t;
input [63:0] x;
time x;
$display("FAILED");
endtask
initial t(10);
endmodule

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@ -0,0 +1,17 @@
// Check that it is an error to declare a non-ANSI task port with implicit
// packed dimensions if it is later redeclared as a vector typed variable and
// the size of the packed dimensions do not match.
module test;
task t;
input [7:0] x;
reg [3:0] x;
$display("FAILED");
endtask
initial begin
t(10);
end
endmodule

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@ -0,0 +1,17 @@
// Check that it is an error to declare a non-ANSI task port without implicit
// packed dimensions if it is later redeclared as a vector typed variable and
// the vector type is not a scalar.
module test;
task t;
input [7:0] x;
reg x;
$display("FAILED");
endtask
initial begin
t(10);
end
endmodule

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@ -0,0 +1,17 @@
// Check that it is an error to declare a non-ANSI task port with implicit
// packed dimensions if it is later redeclared as a vector typed variable and
// the vector type is a scalar.
module test;
task t;
input x;
reg [3:0] x;
$display("FAILED");
endtask
initial begin
t(10);
end
endmodule

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@ -729,14 +729,18 @@ task_init_assign normal,-g2009 ivltests
task_init_var1 normal,-g2009 ivltests
task_init_var2 normal,-g2009 ivltests
task_init_var3 normal,-g2009 ivltests
task_nonansi_atom2_fail CE,-g2005-sv ivltests
task_nonansi_enum1 normal,-g2005-sv ivltests
task_nonansi_enum2 normal,-g2005-sv ivltests
task_nonansi_enum_fail CE,-g2005-sv ivltests
task_nonansi_int1 normal,-g2005-sv ivltests
task_nonansi_int2 normal,-g2005-sv ivltests
task_nonansi_parray1 normal,-g2005-sv ivltests
task_nonansi_parray2 normal,-g2005-sv ivltests
task_nonansi_parray_fail CE,-g2005-sv ivltests
task_nonansi_struct1 normal,-g2005-sv ivltests
task_nonansi_struct2 normal,-g2005-sv ivltests
task_nonansi_struct_fail CE,-g2005-sv ivltests
task_port_types1 normal,-g2009 ivltests
task_port_types2 normal,-g2009 ivltests
task_scope2 normal,-g2009 ivltests

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@ -1641,12 +1641,18 @@ task_iotypes2 normal ivltests # task ports with types.
task_mem normal ivltests
task_nonansi_integer1 normal ivltests
task_nonansi_integer2 normal ivltests
task_nonansi_integer_fail CE ivltests
task_nonansi_real1 normal ivltests
task_nonansi_real2 normal ivltests
task_nonansi_real_fail CE ivltests
task_nonansi_time1 normal ivltests
task_nonansi_time2 normal ivltests
task_nonansi_time_fail CE ivltests
task_nonansi_vec1 normal ivltests
task_nonansi_vec2 normal ivltests
task_nonansi_vec_fail1 CE ivltests
task_nonansi_vec_fail2 CE ivltests
task_nonansi_vec_fail3 CE ivltests
task_noop normal ivltests # Task with no contents.
task_noop2 CO ivltests # Task *really* with no contents.
task_omemw2 normal ivltests