Add regression tests for module port list default values

Check that default values are support for module port lists.
 * For output ports it is supported in both Verilog and SystemVerilog.
 * For input ports it is only supported in SystemVerilog.
 * For inout ports it is never supported

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/module_inout_port_list_def.v

@@ -0,0 +1,22 @@
+// Check that it is an error to specify a default value for inout port
+// declarations.
+
+module M (
+  inout [31:0] x, y = 1 // inout ports do not support default values
+);
+  initial begin
+    $display("FAILED");
+  end
+
+endmodule
+
+module test;
+
+  wire [31:0] x, y;
+
+  M i_m (
+    .x(x),
+    .y(y)
+  );
+
+endmodule

ivtest/ivltests/module_input_port_list_def.v

@@ -0,0 +1,31 @@
+// Check that it is possible to specify a default port value for each port in a
+// input port declaration list.
+
+module M (
+  input [31:0] x = 1, y = 2
+);
+
+  `define check(val, exp) \
+    if (val !== exp) begin \
+      $display("FAILED(%0d): %s, expected %0h got %0h", `__LINE__, `"val`", exp, val); \
+      failed = 1'b1; \
+    end
+
+  reg failed = 1'b0;
+
+  initial begin
+    `check(x, 1)
+    `check(y, 2)
+
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+
+endmodule
+
+module test;
+
+  M i_m ();
+
+endmodule

ivtest/ivltests/module_output_port_list_def.v

@@ -0,0 +1,31 @@
+// Check that it is possible to specify a default port value for each port in a
+// output port declaration list.
+
+module M (
+  output [31:0] x = 1, y = 2
+);
+
+  `define check(val, exp) \
+    if (val !== exp) begin \
+      $display("FAILED(%0d): %s, expected %0h got %0h", `__LINE__, `"val`", exp, val); \
+      failed = 1'b1; \
+    end
+
+  reg failed = 1'b0;
+
+  initial begin
+    `check(x, 1)
+    `check(y, 2)
+
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+
+endmodule
+
+module test;
+
+  M i_m ();
+
+endmodule

ivtest/regress-fsv.list

@@ -78,6 +78,7 @@ br_gh567		normal			ivltests
 check_constant_3	normal			ivltests
 function4		normal			ivltests
 module_inout_port_type	normal			ivltests
+module_input_port_list_def normal,-g2005-sv	ivltests
 module_input_port_type	normal			ivltests
 parameter_in_generate1	normal			ivltests
 parameter_no_default	normal			ivltests

ivtest/regress-vlg.list

@@ -651,7 +651,9 @@ mixed_width_case	normal			ivltests
 modparam		normal			ivltests top # Override parameter via passed down value
 module3.12A		normal			ivltests main
 module3.12B		normal			ivltests
+module_inout_port_list_def CE			ivltests # inout ports do not support default values
 module_inout_port_type	CE			ivltests
+module_input_port_list_def CE			ivltests # input ports only support default values in SV
 module_input_port_type	CE			ivltests
 module_nonansi_integer1	normal			ivltests
 module_nonansi_integer2	normal			ivltests
@@ -659,6 +661,7 @@ module_nonansi_time1	normal			ivltests
 module_nonansi_time2	normal			ivltests
 module_nonansi_vec1	normal			ivltests
 module_nonansi_vec2	normal			ivltests
+module_output_port_list_def normal		ivltests
 module_output_port_var1	normal			ivltests
 module_output_port_var2	normal			ivltests
 module_port_range_mismatch CE			ivltests