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Allow macro arguments to be omitted when default values are available. 

SystemVerilog allows fewer actual arguments than formal arguments when
all remaining formal arguments have default values.
This commit is contained in:
Martin Whitaker 2015-06-27 19:02:02 +01:00
parent 637fc40dd9
commit 586e415d96
1 changed files with 13 additions and 2 deletions
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15
ivlpp/lexor.lex
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@ -1379,11 +1379,22 @@ static void expand_using_args(void)
int arg;
int length;
if (def_argc != cur_macro->argc) {
if (def_argc > cur_macro->argc) {
emit_pathline(istack);
fprintf(stderr, "error: wrong number of arguments for `%s\n", cur_macro->name);
fprintf(stderr, "error: too many arguments for `%s\n", cur_macro->name);
return;
}
while (def_argc < cur_macro->argc) {
if (cur_macro->defaults[def_argc]) {
def_argl[def_argc] = 0;
def_argc += 1;
continue;
}
emit_pathline(istack);
fprintf(stderr, "error: too few arguments for `%s\n", cur_macro->name);
return;
}
assert(def_argc == cur_macro->argc);
head = cur_macro->value;
tail = head;