Spelling fixes from Larry
This commit is contained in:
steve
parent
96443f1338
commit
611d2c81b3
7
BUGS.txt
7
BUGS.txt
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@ -104,7 +104,7 @@ module may not be needed as long as the ``-s <name>'' switch is
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given.
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So when you send a test case, ask yourself "Can poor overworked Steve
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invoke the error without any Verilog other then what is included?" And
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invoke the error without any Verilog other than what is included?" And
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while we are at it, please place a copyright notice in your test
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program and include a GPL license statement if you can. Your test
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program may find its way into the test suite, and the notices will
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@ -160,8 +160,11 @@ I must insist that any copyright material submitted for inclusion
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include the GPL license notice as shown in the rest of the source.
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$Id: BUGS.txt,v 1.4 2003/02/19 04:36:31 steve Exp $
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$Id: BUGS.txt,v 1.5 2007/03/22 16:08:14 steve Exp $
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$Log: BUGS.txt,v $
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Revision 1.5 2007/03/22 16:08:14 steve
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Spelling fixes from Larry
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Revision 1.4 2003/02/19 04:36:31 steve
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Notes on hte bug database.
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: cflexor.lex,v 1.10 2007/03/07 04:24:59 steve Exp $"
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#ident "$Id: cflexor.lex,v 1.11 2007/03/22 16:08:18 steve Exp $"
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#endif
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# include "cfparse.h"
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@ -121,7 +121,7 @@ static int comment_enter;
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"/"[^\*\/] { /* A file name that starts with "/". */
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yymore();
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BEGIN(FILE_NAME); }
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[^/\n \t\b\r+-][^/\n\r]* { /* A file name that starts with other then "/" */
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[^/\n \t\b\r+-][^/\n\r]* { /* A file name that starts with other than "/" */
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yymore();
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BEGIN(FILE_NAME); }
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@ -1,4 +1,4 @@
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.TH iverilog 1 "$Date: 2007/03/08 03:06:47 $" Version "$Date: 2007/03/08 03:06:47 $"
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.TH iverilog 1 "$Date: 2007/03/22 16:08:18 $" Version "$Date: 2007/03/22 16:08:18 $"
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.SH NAME
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iverilog - Icarus Verilog compiler
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@ -68,7 +68,7 @@ full-timing simulations.
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.B -gxtypes\fI|\fP-gno-xtypes
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Enable (default) or disable support for extended types. Enabling
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extended types allows for new types that are supported by Icarus
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Verilog as extensions beyond the baseline verilog. It may be necessary
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Verilog as extensions beyond the baseline Verilog. It may be necessary
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to disable extended types if compiling code that clashes with the few
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new keywords used to implement the type system.
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.TP 8
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@ -199,7 +199,7 @@ implies the synthesis \fB-S\fP flag.
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.SH "WARNING TYPES"
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These are the types of warnings that can be selected by the \fB-W\fP
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switch. All the warning types (other then \fBall\fP) can also be
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switch. All the warning types (other than \fBall\fP) can also be
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prefixed with \fBno-\fP to turn off that warning. This is most useful
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after a \fB-Wall\fP argument to suppress isolated warning types.
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@ -264,7 +264,7 @@ well as # comments, if the # starts the line.
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.I "file name"
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A simple file name or file path is taken to be the name of a Verilog
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source file. The path starts with the first non-white-space
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character. Variables are substitued in file names.
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character. Variables are substituted in file names.
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.TP 8
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.B -y\ \fIlibdir\fP
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@ -322,7 +322,7 @@ This is similar to the \fB+toupper-filename\fP hack described above.
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.TP 8
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.B +integer-width+\fIvalue\fP
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This allows the programmer to select the width for integer variables
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in the verilog source. The default is 32, the value can be any desired
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in the Verilog source. The default is 32, the value can be any desired
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integer value.
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.SH "VARIABLES IN COMMAND FILES"
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@ -331,7 +331,7 @@ In certain cases, iverilog supports variables in command files. These
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are strings of the form "$(\fIvarname\fP)", where \fIvarname\fP is the
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name of the environment variable to read. The entire string is
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replaced with the contents of that variable. Variables are only
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substitued in contexts that explicitly support them, including file
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substituted in contexts that explicitly support them, including file
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and directory strings.
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Variable values come from the operating system environment, and not
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: elab_anet.cc,v 1.12 2006/05/01 20:47:58 steve Exp $"
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#ident "$Id: elab_anet.cc,v 1.13 2007/03/22 16:08:14 steve Exp $"
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#endif
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# include "config.h"
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@ -84,7 +84,7 @@ NetNet* PEConcat::elaborate_anet(Design*des, NetScope*scope) const
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concat operator from least significant to most significant,
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which is opposite from how they are given in the list.
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Allow for a repeat count other then 1 by repeating the
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Allow for a repeat count other than 1 by repeating the
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connect loop as many times as necessary. */
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NetNet*osig = new NetNet(scope, scope->local_symbol(),
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@ -169,6 +169,9 @@ NetNet* PEIdent::elaborate_anet(Design*des, NetScope*scope) const
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/*
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* $Log: elab_anet.cc,v $
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* Revision 1.13 2007/03/22 16:08:14 steve
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* Spelling fixes from Larry
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*
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* Revision 1.12 2006/05/01 20:47:58 steve
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* More explicit datatype setup.
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*
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11
elab_net.cc
11
elab_net.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: elab_net.cc,v 1.200 2007/02/27 06:10:16 steve Exp $"
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#ident "$Id: elab_net.cc,v 1.201 2007/03/22 16:08:14 steve Exp $"
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#endif
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# include "config.h"
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@ -761,7 +761,7 @@ NetNet* PEBinary::elaborate_net_div_(Design*des, NetScope*scope,
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// Make an output signal that is the width of the l-value.
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// Due to above calculation of rwidth, we know that the result
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// will be no more then the l-value, so it is safe to connect
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// will be no more than the l-value, so it is safe to connect
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// all the result pins to the osig.
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NetNet*osig = new NetNet(scope, scope->local_symbol(),
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@ -1507,7 +1507,7 @@ NetNet* PEConcat::elaborate_net(Design*des, NetScope*scope,
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concat operator from least significant to most significant,
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which is opposite from how they are given in the list.
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Allow for a repeat count other then 1 by repeating the
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Allow for a repeat count other than 1 by repeating the
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connect loop as many times as necessary. */
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NetNet*osig = new NetNet(scope, scope->local_symbol(),
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@ -1617,7 +1617,7 @@ NetNet* PEIdent::elaborate_net(Design*des, NetScope*scope,
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assert(pc);
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verinum pvalue = pc->value();
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/* If the desired lwidth is more then the width of the
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/* If the desired lwidth is more than the width of the
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constant value, extend the value to fit the desired
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output. */
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if (lwidth > pvalue.len()) {
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@ -2909,6 +2909,9 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
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/*
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* $Log: elab_net.cc,v $
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* Revision 1.201 2007/03/22 16:08:14 steve
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* Spelling fixes from Larry
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*
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* Revision 1.200 2007/02/27 06:10:16 steve
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* Better error message around repeat concatenation syntax.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: elab_scope.cc,v 1.43 2007/03/08 06:11:35 steve Exp $"
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#ident "$Id: elab_scope.cc,v 1.44 2007/03/22 16:08:15 steve Exp $"
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#endif
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# include "config.h"
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@ -288,7 +288,7 @@ bool Module::elaborate_scope(Design*des, NetScope*scope,
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}
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// Scan through all the named events in this scope. We do not
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// need anything more then the current scope to do this
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// need anything more than the current scope to do this
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// elaboration, so do it now. This allows for normal
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// elaboration to reference these events.
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@ -761,6 +761,9 @@ void PWhile::elaborate_scope(Design*des, NetScope*scope) const
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/*
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* $Log: elab_scope.cc,v $
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* Revision 1.44 2007/03/22 16:08:15 steve
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* Spelling fixes from Larry
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*
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* Revision 1.43 2007/03/08 06:11:35 steve
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* Elaborate scopes of modules instantated in generate loops.
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*
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11
elaborate.cc
11
elaborate.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: elaborate.cc,v 1.364 2007/03/08 05:30:02 steve Exp $"
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#ident "$Id: elaborate.cc,v 1.365 2007/03/22 16:08:15 steve Exp $"
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#endif
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# include "config.h"
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@ -318,7 +318,7 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
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name = scope->local_symbol();
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/* If the Verilog source has a range specification for the
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gates, then I am expected to make more then one
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gates, then I am expected to make more than one
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gate. Figure out how many are desired. */
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if (msb_) {
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NetExpr*msb_exp = elab_and_eval(des, scope, msb_, -1);
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@ -1778,7 +1778,7 @@ NetProc* PCondit::elaborate(Design*des, NetScope*scope) const
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return new NetBlock(NetBlock::SEQU, 0);
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}
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// If the condition expression is more then 1 bits, then
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// If the condition expression is more than 1 bits, then
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// generate a comparison operator to get the result down to
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// one bit. Turn <e> into <e> != 0;
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@ -2406,7 +2406,7 @@ NetProc* PEventStatement::elaborate_wait(Design*des, NetScope*scope,
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return 0;
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}
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// If the condition expression is more then 1 bits, then
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// If the condition expression is more than 1 bits, then
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// generate a reduction operator to get the result down to
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// one bit. In other words, Turn <e> into |<e>;
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@ -3401,6 +3401,9 @@ Design* elaborate(list<perm_string>roots)
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/*
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* $Log: elaborate.cc,v $
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* Revision 1.365 2007/03/22 16:08:15 steve
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* Spelling fixes from Larry
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*
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* Revision 1.364 2007/03/08 05:30:02 steve
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* Limit the calculated widths of constants.
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*
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@ -16,13 +16,13 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*
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* $Id: sqrt-virtex.v,v 1.4 2003/11/25 18:35:31 steve Exp $"
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* $Id: sqrt-virtex.v,v 1.5 2007/03/22 16:08:18 steve Exp $"
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*/
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/*
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* This module is a synthesizeable square-root function. It is also a
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* detailed example of how to target Xilinx Virtex parts using
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* Icarus Verilog. In fact, for no particular reason other then to
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* Icarus Verilog. In fact, for no particular reason other than to
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* be excessively specific, I will step through the process of
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* generating a design for a Spartan-II XC2S15-VQ100, and also how to
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* generate a generic library part for larger Virtex designs.
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@ -129,7 +129,7 @@
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* This command creates from the chip.ngd the file "chip_root.v" that
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* contains Verilog code that simulates the mapped design. This output
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* Verilog has the single root module "chip_root", which came from the
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* name of the root module when we were making hte EDIF file in the
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* name of the root module when we were making the EDIF file in the
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* first place. The module has ports named just line the ports of the
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* chip_root module below.
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*
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@ -183,7 +183,7 @@
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* where sqrt(y) is the exact square root of y and floor(N) is the
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* largest integer <= N.
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*
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* For 32bit numbers, this will never run more then 16 iterations,
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* For 32 bit numbers, this will never run more than 16 iterations,
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* which amounts to 16 clocks.
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*/
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@ -16,7 +16,7 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*
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* $Id: sqrt.vl,v 1.4 2004/10/04 01:10:56 steve Exp $"
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* $Id: sqrt.vl,v 1.5 2007/03/22 16:08:18 steve Exp $"
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*/
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/*
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@ -50,7 +50,7 @@
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* where sqrt(y) is the exact square root of y and floor(N) is the
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* largest integer <= N.
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*
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* For 32bit numbers, this will never run more then 16 iterations,
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* For 32 bit numbers, this will never run more than 16 iterations,
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* which amounts to 16 clocks.
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*/
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@ -249,7 +249,7 @@ exactly the same so far as the compiler is concerned.
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Unfortunately, Cadence seems to feel otherwise. In particular, it has
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been reported that although {1'b0, 16} causes an error, {1'b0, 15+1}
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is accepted. Further testing shows that any expression other then a
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is accepted. Further testing shows that any expression other than a
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simple unsized constant is accepted there, even if all the operands of
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all the operators that make up the expression are unsized integers.
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@ -498,8 +498,11 @@ of 4-value behavior in the dead zone, and appears more user friendly
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when viewed by reasonable viewers.
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$Id: ieee1364-notes.txt,v 1.17 2003/07/15 03:49:22 steve Exp $
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$Id: ieee1364-notes.txt,v 1.18 2007/03/22 16:08:16 steve Exp $
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$Log: ieee1364-notes.txt,v $
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Revision 1.18 2007/03/22 16:08:16 steve
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Spelling fixes from Larry
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Revision 1.17 2003/07/15 03:49:22 steve
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Spelling fixes.
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19
ivl_target.h
19
ivl_target.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: ivl_target.h,v 1.180 2007/03/02 06:13:22 steve Exp $"
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#ident "$Id: ivl_target.h,v 1.181 2007/03/22 16:08:16 steve Exp $"
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#endif
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# include <inttypes.h>
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@ -767,7 +767,7 @@ extern unsigned ivl_expr_width(ivl_expr_t net);
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* These devices are grouped as logic devices with zero inputs because
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* the outputs have the same characteristics as other logic
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* devices. They are special only in that they have zero inputs, and
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* their drivers typically have strength other then strong.
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* their drivers typically have strength other than strong.
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*
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* - IVL_LO_UDP
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* User defined primitives (UDPs) are like any other logic devices, in
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@ -926,7 +926,7 @@ extern const char* ivl_udp_name(ivl_udp_t net);
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* inputs. In fact, the compiler doesn't assure that the widths of the
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* inputs add up to the width of the output, but the possibility
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* exists. It is *not* an error for the sum of the input widths to be
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* more then the width of the output, although the possibility of
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* more than the width of the output, although the possibility of
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* overflow exists at run time.
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*
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* Multiply may be signed. If so, the output should be sign extended
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@ -1175,7 +1175,7 @@ extern const char*ivl_lpm_string(ivl_lpm_t net);
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* - Array words
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* If the l-value is an array, then ivl_lval_idx function will return
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* an expression that calculates the address of the array word. If
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* the referenced signal has more then one word, this expression must
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* the referenced signal has more than one word, this expression must
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* be present. If the signal has exactly one word (it is not an array)
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* then the ivl_lval_idx exression must *not* be present.
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*
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@ -1344,7 +1344,7 @@ extern ivl_expr_t ivl_parameter_expr(ivl_parameter_t net);
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* ivl_scope_children
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* A scope may in turn contain other scopes. This method iterates
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* through all the child scopes of a given scope. If the function
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* returns any value other then 0, the iteration stops and the
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* returns any value other than 0, the iteration stops and the
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* method returns that value. Otherwise, iteration continues until
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* the children run out.
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*
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@ -1355,7 +1355,7 @@ extern ivl_expr_t ivl_parameter_expr(ivl_parameter_t net);
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* Task definition scopes carry a task definition, in the form of
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* a statement. This method accesses that definition. The
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* ivl_scope_def function must return a statement for scopes that
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* are type FUNCTION or TASK, and most return nil otherwise.
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* are type FUNCTION or TASK, and must return nil otherwise.
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*
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* ivl_scope_event
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* ivl_scope_events
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@ -1599,7 +1599,7 @@ extern ivl_statement_type_t ivl_statement_type(ivl_statement_t net);
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/*
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* The following functions retrieve specific single values from the
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* statement. These values are the bits of data and parameters that
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||||
* make up the statement. Many of these functions apply to more then
|
||||
* make up the statement. Many of these functions apply to more than
|
||||
* one type of statement, so the comment in front of them tells which
|
||||
* statement types can be passed to the function.
|
||||
*
|
||||
|
|
@ -1618,7 +1618,7 @@ extern ivl_statement_type_t ivl_statement_type(ivl_statement_t net);
|
|||
* ivl_stmt_lval
|
||||
* ivl_stmt_lvals
|
||||
* Return the number of l-values for an assignment statement, or
|
||||
* the specific l-value. If there is more then 1 l-value, then the
|
||||
* the specific l-value. If there is more than 1 l-value, then the
|
||||
* l-values are presumed to be vector values concatenated together
|
||||
* from msb (idx==0) to lsb.
|
||||
*
|
||||
|
|
@ -1779,6 +1779,9 @@ _END_DECL
|
|||
|
||||
/*
|
||||
* $Log: ivl_target.h,v $
|
||||
* Revision 1.181 2007/03/22 16:08:16 steve
|
||||
* Spelling fixes from Larry
|
||||
*
|
||||
* Revision 1.180 2007/03/02 06:13:22 steve
|
||||
* Add support for edge sensitive spec paths.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ The msys package is available from the mingw download site. This is
|
|||
not the compiler but a collection of *nix tools ported to Windows and
|
||||
wrapped in a convenient installer. The msys package is all the various
|
||||
basic tools (shells, file utils, etc) and the msysDTK is extra
|
||||
developer tools other then the compiler.
|
||||
developer tools other than the compiler.
|
||||
|
||||
Download the msys-1.x.x.exe and msysdtc-1.x.x.exe binaries. These are
|
||||
self-installing packages. Install msys first, and then msysDTC. Most
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: netlist.h,v 1.372 2007/03/08 05:30:03 steve Exp $"
|
||||
#ident "$Id: netlist.h,v 1.373 2007/03/22 16:08:16 steve Exp $"
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -1530,7 +1530,7 @@ class NetUReduce : public NetNode {
|
|||
* N -- (1x)
|
||||
*
|
||||
* It also takes one of the following glob letters to represent more
|
||||
* then one item.
|
||||
* than one item.
|
||||
*
|
||||
* p -- 01, 0x or x1 // check this with the lexer
|
||||
* n -- 10, 1x or x0 // check this with the lexer
|
||||
|
|
@ -1543,7 +1543,7 @@ class NetUReduce : public NetNode {
|
|||
* SEQUENTIAL
|
||||
* These objects have a single bit of memory. The logic table includes
|
||||
* an entry for the current value, and allows edges on the inputs. In
|
||||
* canonical form, inly then entries that generate 0, 1 or - (no change)
|
||||
* canonical form, only the entries that generate 0, 1 or - (no change)
|
||||
* are listed.
|
||||
*
|
||||
* COMBINATIONAL
|
||||
|
|
@ -3495,6 +3495,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
|
|||
|
||||
/*
|
||||
* $Log: netlist.h,v $
|
||||
* Revision 1.373 2007/03/22 16:08:16 steve
|
||||
* Spelling fixes from Larry
|
||||
*
|
||||
* Revision 1.372 2007/03/08 05:30:03 steve
|
||||
* Limit the calculated widths of constants.
|
||||
*
|
||||
|
|
|
|||
4
parse.y
4
parse.y
|
|
@ -19,7 +19,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: parse.y,v 1.231 2007/03/07 04:24:59 steve Exp $"
|
||||
#ident "$Id: parse.y,v 1.232 2007/03/22 16:08:17 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "config.h"
|
||||
|
|
@ -3158,7 +3158,7 @@ statement_opt
|
|||
| ';' { $$ = 0; }
|
||||
;
|
||||
|
||||
/* Task items are, other then the statement, task port items and
|
||||
/* Task items are, other than the statement, task port items and
|
||||
other block items. */
|
||||
task_item
|
||||
: block_item_decl { $$ = new svector<PWire*>(0); }
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: svector.h,v 1.10 2005/06/14 19:13:43 steve Exp $"
|
||||
#ident "$Id: svector.h,v 1.11 2007/03/22 16:08:17 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "config.h"
|
||||
|
|
@ -31,7 +31,7 @@
|
|||
/*
|
||||
* This is a way simplified vector class that cannot grow or shrink,
|
||||
* and is really only able to handle values. It is intended to be
|
||||
* lighter weight then the STL list class.
|
||||
* lighter weight than the STL list class.
|
||||
*/
|
||||
|
||||
template <class TYPE> class svector {
|
||||
|
|
@ -109,6 +109,9 @@ template <> inline svector<std::string>::svector(unsigned size)
|
|||
|
||||
/*
|
||||
* $Log: svector.h,v $
|
||||
* Revision 1.11 2007/03/22 16:08:17 steve
|
||||
* Spelling fixes from Larry
|
||||
*
|
||||
* Revision 1.10 2005/06/14 19:13:43 steve
|
||||
* gcc3/4 compile errors.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: synth2.cc,v 1.45 2005/08/27 04:32:08 steve Exp $"
|
||||
#ident "$Id: synth2.cc,v 1.46 2007/03/22 16:08:17 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "config.h"
|
||||
|
|
@ -766,7 +766,7 @@ bool NetEvWait::synth_sync(Design*des, NetScope*scope, NetFF*ff,
|
|||
|
||||
assert(events_in.count() == 0);
|
||||
|
||||
/* This can't be other then one unless there are named events,
|
||||
/* This can't be other than one unless there are named events,
|
||||
which I cannot synthesize. */
|
||||
assert(nevents_ == 1);
|
||||
NetEvent*ev = events_[0];
|
||||
|
|
@ -1000,6 +1000,9 @@ void synth2(Design*des)
|
|||
|
||||
/*
|
||||
* $Log: synth2.cc,v $
|
||||
* Revision 1.46 2007/03/22 16:08:17 steve
|
||||
* Spelling fixes from Larry
|
||||
*
|
||||
* Revision 1.45 2005/08/27 04:32:08 steve
|
||||
* Handle synthesis of fully packed case statements.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: t-dll-expr.cc,v 1.46 2007/02/20 05:58:36 steve Exp $"
|
||||
#ident "$Id: t-dll-expr.cc,v 1.47 2007/03/22 16:08:18 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "config.h"
|
||||
|
|
@ -414,7 +414,7 @@ void dll_target::expr_signal(const NetESignal*net)
|
|||
|
||||
/* Make account for the special case that this is a reference
|
||||
to an array as a whole. We detect this case by noting that
|
||||
this is an array (more then 1 word) and there is no word
|
||||
this is an array (more than 1 word) and there is no word
|
||||
select expression. In that case, this is an IVL_EX_ARRAY
|
||||
expression instead of a SIGNAL expression. */
|
||||
if (sig->array_words > 1 && word_expr == 0) {
|
||||
|
|
@ -474,6 +474,9 @@ void dll_target::expr_unary(const NetEUnary*net)
|
|||
|
||||
/*
|
||||
* $Log: t-dll-expr.cc,v $
|
||||
* Revision 1.47 2007/03/22 16:08:18 steve
|
||||
* Spelling fixes from Larry
|
||||
*
|
||||
* Revision 1.46 2007/02/20 05:58:36 steve
|
||||
* Handle unary minus of real valued expressions.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: eval_expr.c,v 1.135 2007/02/26 19:49:50 steve Exp $"
|
||||
#ident "$Id: eval_expr.c,v 1.136 2007/03/22 16:08:18 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "vvp_priv.h"
|
||||
|
|
@ -1685,9 +1685,9 @@ static struct vector_info draw_select_signal(ivl_expr_t sube,
|
|||
return res;
|
||||
}
|
||||
|
||||
/* Try the special case that hte part is at the beginning and
|
||||
/* Try the special case that the part is at the beginning and
|
||||
nearly the width of the signal. In this case, just load the
|
||||
entire signal in one go then simply drop the excess bits. */
|
||||
entire signal in one go, then simply drop the excess bits. */
|
||||
if (shiv.base == 0
|
||||
&& (ivl_expr_width(sube) > wid)
|
||||
&& (ivl_expr_width(sube) < (wid+wid/10))) {
|
||||
|
|
@ -2201,6 +2201,9 @@ struct vector_info draw_eval_expr(ivl_expr_t exp, int stuff_ok_flag)
|
|||
|
||||
/*
|
||||
* $Log: eval_expr.c,v $
|
||||
* Revision 1.136 2007/03/22 16:08:18 steve
|
||||
* Spelling fixes from Larry
|
||||
*
|
||||
* Revision 1.135 2007/02/26 19:49:50 steve
|
||||
* Spelling fixes (larry doolittle)
|
||||
*
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: vector.c,v 1.13 2007/03/20 04:26:56 steve Exp $"
|
||||
#ident "$Id: vector.c,v 1.14 2007/03/22 16:08:18 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "vvp_priv.h"
|
||||
|
|
@ -199,7 +199,7 @@ static void clear_signal_lookaside_bit(unsigned idx, ivl_signal_t sig, unsigned
|
|||
void save_signal_lookaside(unsigned addr, ivl_signal_t sig, unsigned sig_word, unsigned wid)
|
||||
{
|
||||
unsigned idx;
|
||||
/* Don't bind any of hte low bits to a signal. */
|
||||
/* Don't bind any of the low bits to a signal. */
|
||||
if (addr < 8 && wid > 0)
|
||||
return;
|
||||
|
||||
|
|
@ -372,6 +372,9 @@ unsigned allocate_vector_exp(ivl_expr_t exp, unsigned wid,
|
|||
|
||||
/*
|
||||
* $Log: vector.c,v $
|
||||
* Revision 1.14 2007/03/22 16:08:18 steve
|
||||
* Spelling fixes from Larry
|
||||
*
|
||||
* Revision 1.13 2007/03/20 04:26:56 steve
|
||||
* Clear lookaside even if source bit is a constant.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: vvp_scope.c,v 1.155 2007/03/02 06:13:22 steve Exp $"
|
||||
#ident "$Id: vvp_scope.c,v 1.156 2007/03/22 16:08:18 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "vvp_priv.h"
|
||||
|
|
@ -379,7 +379,7 @@ static int can_elide_bufz(ivl_net_logic_t net, ivl_nexus_ptr_t nptr)
|
|||
|
||||
/*
|
||||
* Given a nexus, look for a signal that has module delay
|
||||
* paths. Return that signal. (There should be no more then 1.) If we
|
||||
* paths. Return that signal. (There should be no more than 1.) If we
|
||||
* don't find any, then return nil.
|
||||
*/
|
||||
static ivl_signal_t find_modpath(ivl_nexus_t nex)
|
||||
|
|
@ -809,7 +809,7 @@ static char* draw_net_input_x(ivl_nexus_t nex,
|
|||
continue;
|
||||
|
||||
/* Mark the strength-aware flag if the driver can
|
||||
generate values other then the standard "6"
|
||||
generate values other than the standard "6"
|
||||
strength. */
|
||||
if (ivl_nexus_ptr_drive0(nptr) != IVL_DR_STRONG)
|
||||
nex_flags |= VVP_NEXUS_DATA_STR;
|
||||
|
|
@ -1764,7 +1764,7 @@ static void draw_lpm_concat(ivl_lpm_t net)
|
|||
lpm_concat_inputs(net, 0, icnt, src_table);
|
||||
|
||||
} else {
|
||||
/* If there are more then 4 inputs, things get more
|
||||
/* If there are more than 4 inputs, things get more
|
||||
complicated. We need to generate a balanced tree of
|
||||
.concat nodes to blend the inputs down to a single
|
||||
root node, that becomes the output from the
|
||||
|
|
@ -2369,6 +2369,9 @@ int draw_scope(ivl_scope_t net, ivl_scope_t parent)
|
|||
|
||||
/*
|
||||
* $Log: vvp_scope.c,v $
|
||||
* Revision 1.156 2007/03/22 16:08:18 steve
|
||||
* Spelling fixes from Larry
|
||||
*
|
||||
* Revision 1.155 2007/03/02 06:13:22 steve
|
||||
* Add support for edge sensitive spec paths.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: sys_scanf.c,v 1.6 2007/03/14 04:05:51 steve Exp $"
|
||||
#ident "$Id: sys_scanf.c,v 1.7 2007/03/22 16:08:19 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "vpi_user.h"
|
||||
|
|
@ -256,7 +256,7 @@ static int scan_format(vpiHandle sys, struct byte_source*src, vpiHandle argv)
|
|||
byte_ungetc(src, ch);
|
||||
|
||||
} else if (*fmtp != '%') {
|
||||
/* Characters other then % match themselves. */
|
||||
/* Characters other than % match themselves. */
|
||||
ch = byte_getc(src);
|
||||
if (ch != *fmtp) {
|
||||
byte_ungetc(src, ch);
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
|
||||
*
|
||||
* $Id: README.txt,v 1.81 2007/03/01 06:19:39 steve Exp $
|
||||
* $Id: README.txt,v 1.82 2007/03/22 16:08:19 steve Exp $
|
||||
*/
|
||||
|
||||
VVP SIMULATION ENGINE
|
||||
|
|
@ -83,7 +83,7 @@ references symbolically.)
|
|||
|
||||
If the functor is part of a vector, then the symbol is the
|
||||
vvp_ipoint_t for the first functor. The [] operator can then be used
|
||||
to reference a functor other then the first in the vector.
|
||||
to reference a functor other than the first in the vector.
|
||||
|
||||
There are some special symbols that in certain contexts have special
|
||||
meanings. As inputs to functors, the symbols "C<0>", "C<1>", "C<x>"
|
||||
|
|
@ -164,7 +164,7 @@ implementation. Most of the core gate types have built in tables.
|
|||
The initial values of all the inputs and the output is x. Any other
|
||||
value is passed around as run-time behavior. If the inputs have C<?>
|
||||
symbols, then the inputs are initialized to the specified bit value,
|
||||
and if this causes the output to be something other then x, a
|
||||
and if this causes the output to be something other than x, a
|
||||
propagation event is created to be executed at the start of run time.
|
||||
|
||||
The strengths of inputs are ignored by functors, and the output has
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: memory.h,v 1.12 2006/03/05 05:45:58 steve Exp $"
|
||||
#ident "$Id: memory.h,v 1.13 2007/03/22 16:08:19 steve Exp $"
|
||||
#endif
|
||||
|
||||
#include "vvp_net.h"
|
||||
|
|
@ -119,7 +119,7 @@ long memory_word_right_range(vvp_memory_t mem);
|
|||
*
|
||||
* NOTE: This functor is unique in that it needs to store the
|
||||
* vvp_net_t pointer associated with it. It needs this because it can
|
||||
* received input from other then its ports. Notably, the memory
|
||||
* received input from other than its ports. Notably, the memory
|
||||
* itself reports word changes.
|
||||
*/
|
||||
class vvp_fun_memport : public vvp_net_fun_t {
|
||||
|
|
@ -157,6 +157,9 @@ vvp_memory_t memory_create(char *label);
|
|||
|
||||
/*
|
||||
* $Log: memory.h,v $
|
||||
* Revision 1.13 2007/03/22 16:08:19 steve
|
||||
* Spelling fixes from Larry
|
||||
*
|
||||
* Revision 1.12 2006/03/05 05:45:58 steve
|
||||
* Add support for memory value change callbacks.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com)
|
||||
*
|
||||
* $Id: opcodes.txt,v 1.74 2007/02/14 05:58:14 steve Exp $
|
||||
* $Id: opcodes.txt,v 1.75 2007/03/22 16:08:19 steve Exp $
|
||||
*/
|
||||
|
||||
|
||||
|
|
@ -9,7 +9,7 @@
|
|||
EXECUTABLE INSTRUCTION OPCODES
|
||||
|
||||
Instruction opcodes all start with a % character and have 0 or more
|
||||
operands. In no case are there more then 3 operands. This chapter
|
||||
operands. In no case are there more than 3 operands. This chapter
|
||||
describes the specific behavior of each opcode, in enough detail
|
||||
(I hope) that its complete effect can be predicted.
|
||||
|
||||
|
|
@ -288,7 +288,7 @@ thread to start executing at the specified address. The new thread is
|
|||
created and pushed onto the child stack. It is also marked runnable,
|
||||
but is not necessarily started until the current thread yields.
|
||||
|
||||
The %fork instruction has no effect other then to push a child thread.
|
||||
The %fork instruction has no effect other than to push a child thread.
|
||||
|
||||
See also %join.
|
||||
|
||||
|
|
@ -363,7 +363,7 @@ will jump to T_label if bit 8 is x or z.
|
|||
|
||||
This is the partner to %fork. This instruction causes the thread to
|
||||
wait for the top thread in the child stack to terminate, then
|
||||
continues. It has no effect in the current thread other then to wait
|
||||
continues. It has no effect in the current thread other than to wait
|
||||
until the top child is cleared.
|
||||
|
||||
It is an error to execute %join if there are no children in the child
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
|
||||
*
|
||||
* $Id: vpi.txt,v 1.7 2003/02/09 23:33:26 steve Exp $
|
||||
* $Id: vpi.txt,v 1.8 2007/03/22 16:08:19 steve Exp $
|
||||
*/
|
||||
|
||||
|
||||
|
|
@ -108,7 +108,7 @@ A scope is created with a .scope directive, like so:
|
|||
The scope takes a string name as the first parameter. If there is an
|
||||
additional parameter, it is a label of the directive for the parent
|
||||
scope. Scopes that have no parent are root scopes. It is an error to
|
||||
declare a scope with the same name more then once in a parent scope.
|
||||
declare a scope with the same name more than once in a parent scope.
|
||||
|
||||
The name string given when creating the scope is the basename for the
|
||||
scope. The vvp automatically constructs full names from the scope
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ident "$Id: vvp_net.cc,v 1.61 2007/03/07 03:55:42 steve Exp $"
|
||||
#ident "$Id: vvp_net.cc,v 1.62 2007/03/22 16:08:19 steve Exp $"
|
||||
|
||||
# include "config.h"
|
||||
# include "vvp_net.h"
|
||||
|
|
@ -410,7 +410,7 @@ void vvp_vector4_t::set_vec(unsigned adr, const vvp_vector4_t&that)
|
|||
|
||||
} else if (that.size_ <= BITS_PER_WORD) {
|
||||
|
||||
/* This vector is more then a word, but that vector is
|
||||
/* This vector is more than a word, but that vector is
|
||||
still small. Write into the destination, possibly
|
||||
spanning two destination works, depending on whether
|
||||
the source vector spans a word transition. */
|
||||
|
|
@ -2290,6 +2290,9 @@ vvp_bit4_t compare_gtge_signed(const vvp_vector4_t&a,
|
|||
|
||||
/*
|
||||
* $Log: vvp_net.cc,v $
|
||||
* Revision 1.62 2007/03/22 16:08:19 steve
|
||||
* Spelling fixes from Larry
|
||||
*
|
||||
* Revision 1.61 2007/03/07 03:55:42 steve
|
||||
* Cast to remove ambiguities calling pow function.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ident "$Id: vvp_net.h,v 1.56 2007/03/02 06:13:22 steve Exp $"
|
||||
#ident "$Id: vvp_net.h,v 1.57 2007/03/22 16:08:19 steve Exp $"
|
||||
|
||||
# include "config.h"
|
||||
# include <stddef.h>
|
||||
|
|
@ -914,7 +914,7 @@ class vvp_fun_signal_real : public vvp_fun_signal_base {
|
|||
|
||||
/*
|
||||
* Wide Functors:
|
||||
* Wide functors represent special devices that may have more then 4
|
||||
* Wide functors represent special devices that may have more than 4
|
||||
* input ports. These devices need a set of N/4 actual functors to
|
||||
* catch the inputs, and use another to deliver the output.
|
||||
*
|
||||
|
|
@ -1040,6 +1040,9 @@ inline void vvp_send_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&val,
|
|||
|
||||
/*
|
||||
* $Log: vvp_net.h,v $
|
||||
* Revision 1.57 2007/03/22 16:08:19 steve
|
||||
* Spelling fixes from Larry
|
||||
*
|
||||
* Revision 1.56 2007/03/02 06:13:22 steve
|
||||
* Add support for edge sensitive spec paths.
|
||||
*
|
||||
|
|
|
|||
7
xnfio.cc
7
xnfio.cc
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: xnfio.cc,v 1.29 2004/02/20 18:53:36 steve Exp $"
|
||||
#ident "$Id: xnfio.cc,v 1.30 2007/03/22 16:08:18 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "config.h"
|
||||
|
|
@ -308,7 +308,7 @@ void xnfio_f::lpm_compare(Design*des, NetCompare*dev)
|
|||
|
||||
bool xnfio_f::compare_sideb_const(Design*des, NetCompare*dev)
|
||||
{
|
||||
/* Even if side B is all constant, if there are more then 4
|
||||
/* Even if side B is all constant, if there are more than 4
|
||||
signals on side A we will not be able to fit the operation
|
||||
into a function unit, so we might as well accept a
|
||||
comparator. Give up. */
|
||||
|
|
@ -365,6 +365,9 @@ void xnfio(Design*des)
|
|||
|
||||
/*
|
||||
* $Log: xnfio.cc,v $
|
||||
* Revision 1.30 2007/03/22 16:08:18 steve
|
||||
* Spelling fixes from Larry
|
||||
*
|
||||
* Revision 1.29 2004/02/20 18:53:36 steve
|
||||
* Addtrbute keys are perm_strings.
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue