Use `assert false' as initial translation of $finish

tgt-vhdl/stmt.cc

@@ -103,6 +103,19 @@ static int draw_stask_display(vhdl_process *proc, ivl_statement_t stmt)
    return 0;
 }
 
+/*
+ * VHDL has no real equivalent of Verilog's $finish task. The
+ * current solution is to use `assert false ...' to terminate
+ * the simulator. This isn't great, as the simulator will
+ * return a failure exit code when in fact it completed
+ * successfully.
+ */
+static int draw_stask_finish(vhdl_process *proc, ivl_statement_t stmt)
+{
+   proc->add_stmt(new vhdl_assert_stmt("SIMULATION FINISHED"));
+   return 0;
+}
+
 /*
  * Generate VHDL for system tasks (like $display). Not all of
  * these are supported.
@@ -113,6 +126,8 @@ static int draw_stask(vhdl_process *proc, ivl_statement_t stmt)
 
    if (strcmp(name, "$display") == 0)
       return draw_stask_display(proc, stmt);
+   else if (strcmp(name, "$finish") == 0)
+      return draw_stask_finish(proc, stmt);
    else {
       error("No VHDL translation for system task %s", name);
       return 0;

tgt-vhdl/vhdl_syntax.cc

@@ -542,6 +542,12 @@ void vhdl_cassign_stmt::emit(std::ofstream &of, int level) const
    of << ";";
 }
 
+void vhdl_assert_stmt::emit(std::ofstream &of, int level) const
+{
+   of << "assert false ";  // TODO: Allow arbitrary expression 
+   of << " report \"" << reason_ << "\" severity failure;";
+}
+
 vhdl_unaryop_expr::~vhdl_unaryop_expr()
 {
    delete operand_;

tgt-vhdl/vhdl_syntax.hh

@@ -251,6 +251,17 @@ public:
 };
 
 
+class vhdl_assert_stmt : public vhdl_seq_stmt {
+public:
+   vhdl_assert_stmt(const char *reason)
+      : reason_(reason) {}
+
+   void emit(std::ofstream &of, int level) const;
+private:
+   std::string reason_;
+};
+
+
 /*
  * A procedure call. Which is a statement, unlike a function
  * call which is an expression.