Fix part select of width-1 vector

Signals of width 1 are declared in VHDL as std_logic, as this
is the usual way to represent them. Unfortunately, we cannot
distinguish between

reg [0:0] a;

and

reg a;

This patch avoids trying to slice a std_logic so a[0] is equivalent to a.

tgt-vhdl/lpm.cc

@@ -115,7 +115,9 @@ static vhdl_expr *part_select_vp_lpm_to_expr(vhdl_scope *scope, ivl_lpm_t lpm)
    if (NULL == off)
       return NULL;
 
-   selfrom->set_slice(off, ivl_lpm_width(lpm) - 1);
+   if (selfrom->get_type()->get_width() > 1)
+      selfrom->set_slice(off, ivl_lpm_width(lpm) - 1);
+   
    return selfrom;
 }
 

tgt-vhdl/stmt.cc

@@ -139,7 +139,7 @@ static vhdl_var_ref *make_assign_lhs(ivl_lval_t lval, vhdl_scope *scope)
    if (base) {
       if (decl->get_type()->get_name() == VHDL_TYPE_ARRAY)
          lval_ref->set_slice(base, 0);
-      else
+      else if (ivl_signal_width(sig) > 1)
          lval_ref->set_slice(base, lval_width - 1);
    }