Add regression test for issue #1184.

This checks the temporary fix of outputing a suitable "sorry" message.
This commit is contained in:
Martin Whitaker 2024-12-31 17:15:19 +00:00
parent 84848e8e04
commit f3abd94e9b
5 changed files with 71 additions and 0 deletions

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@ -0,0 +1 @@
sorry: multi-bit module path delays are currently not fully supported.

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1 00 xx
3 00 00
4 11 00
5 11 11
7 10 11
9 10 10

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module dut(input wire [1:0] i, output wire [1:0] o);
assign o = i;
specify
specparam tRISE = 1;
specparam tFALL = 2;
(i => o) = (tRISE, tFALL);
endspecify
endmodule
module test();
reg [1:0] i;
wire [1:0] o;
dut dut(i, o);
reg failed = 0;
initial begin
#1 $monitor("%0t %b %b", $time, i, o);
i = 2'b00;
#0 if (o !== 2'bxx) failed = 1;
#1; #0 if (o !== 2'bxx) failed = 1;
#1; #0 if (o !== 2'b00) failed = 1;
#1; #0 if (o !== 2'b00) failed = 1;
i = 2'b11;
#0 if (o !== 2'b00) failed = 1;
#1; #0 if (o !== 2'b11) failed = 1;
#1; #0 if (o !== 2'b11) failed = 1;
#1; #0 if (o !== 2'b11) failed = 1;
i = 2'b10;
#0 if (o !== 2'b11) failed = 1;
#1; #0 if (o !== 2'b11) failed = 1;
#1; #0 if (o !== 2'b10) failed = 1;
#1; #0 if (o !== 2'b10) failed = 1;
i = 2'b01;
#0 if (o !== 2'b10) failed = 1;
#1; #0 if (o !== 2'b11) failed = 1;
#1; #0 if (o !== 2'b01) failed = 1;
#1; #0 if (o !== 2'b01) failed = 1;
#1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule

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@ -63,6 +63,7 @@ br_gh1163 vvp_tests/br_gh1163.json
br_gh1180a vvp_tests/br_gh1180a.json
br_gh1180b vvp_tests/br_gh1180b.json
br_gh1181 vvp_tests/br_gh1181.json
br_gh1184 vvp_tests/br_gh1184.json
ca_time_real` vvp_tests/ca_time_real.json
case1 vvp_tests/case1.json
case2 vvp_tests/case2.json

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{
"type" : "EF",
"source" : "br_gh1184.v",
"gold" : "br_gh1184",
"iverilog-args" : [ "-gspecify" ]
}