Add regression tests for mixed procedural/continuous assignments.
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Martin Whitaker
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ivltests/sv_mixed_assign_error1.v:10: error: Cannot perform procedural assignment to array 'q' because it is also continuously assigned.
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Elaboration failed
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ivltests/sv_mixed_assign_error2.v:15: error: Cannot perform procedural assignment to array word 'p['sd1]' because it is also continuously assigned.
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ivltests/sv_mixed_assign_error2.v:16: error: Cannot perform procedural assignment to array word 'p[i]' because it is also continuously assigned.
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ivltests/sv_mixed_assign_error2.v:17: error: Cannot perform procedural assignment to array word 'q['sd0]' because it is also continuously assigned.
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ivltests/sv_mixed_assign_error2.v:18: error: Cannot perform procedural assignment to array word 'q['sd1]' because it is also continuously assigned.
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4 error(s) during elaboration.
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ivltests/sv_mixed_assign_error3.v:10: error: Cannot perform procedural assignment to variable 'q' because it is also continuously assigned.
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Elaboration failed
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ivltests/sv_mixed_assign_error4.v:13: error: Cannot perform procedural assignment to part select 'v['sd3:'sd2]' because it is also continuously assigned.
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ivltests/sv_mixed_assign_error4.v:14: error: Cannot perform procedural assignment to part select 'v['sd5:'sd4]' because it is also continuously assigned.
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ivltests/sv_mixed_assign_error4.v:18: error: Cannot perform procedural assignment to part select 'v['sd2+:'sd2]' because it is also continuously assigned.
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ivltests/sv_mixed_assign_error4.v:19: error: Cannot perform procedural assignment to part select 'v['sd5-:'sd2]' because it is also continuously assigned.
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ivltests/sv_mixed_assign_error4.v:22: error: Cannot perform procedural assignment to part select 'v[lsb+:'sd2]' because it is also continuously assigned.
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ivltests/sv_mixed_assign_error4.v:23: error: Cannot perform procedural assignment to part select 'v[msb-:'sd2]' because it is also continuously assigned.
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ivltests/sv_mixed_assign_error4.v:26: error: Cannot perform procedural assignment to bit select 'v['sd2]' because it is also continuously assigned.
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ivltests/sv_mixed_assign_error4.v:27: error: Cannot perform procedural assignment to bit select 'v['sd4]' because it is also continuously assigned.
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ivltests/sv_mixed_assign_error4.v:30: error: Cannot perform procedural assignment to bit select 'v[lsb]' because it is also continuously assigned.
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ivltests/sv_mixed_assign_error4.v:31: error: Cannot perform procedural assignment to bit select 'v[msb]' because it is also continuously assigned.
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10 error(s) during elaboration.
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// Check different words in an array word can be procedurally and continuously assigned.
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module test();
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logic [7:0] a[2:0];
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assign a[0] = 8'd1;
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reg failed = 0;
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initial begin
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a[1] = 8'd2;
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#0 $display("%b %b %b", a[0], a[1], a[2]);
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if (a[0] !== 8'd1 || a[1] !== 8'd2 || a[2] !== 8'bx) failed = 1;
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/*
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* IEEE 1800-2017 states that "A force or release statement shall not be
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* applied to a variable that is being assigned by a mixture of continuous
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* and procedural assignments.", but some other compilers allow this. It
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* looks to be more work to detect and report it as an error than to allow
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* it.
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*/
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force a[0] = 8'd3;
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#0 $display("%b %b %b", a[0], a[1], a[2]);
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if (a[0] !== 8'd3 || a[1] !== 8'd2 || a[2] !== 8'bx) failed = 1;
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force a[1] = 8'd4;
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#0 $display("%b %b %b", a[0], a[1], a[2]);
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if (a[0] !== 8'd3 || a[1] !== 8'd4 || a[2] !== 8'bx) failed = 1;
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release a[0];
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#0 $display("%b %b %b", a[0], a[1], a[2]);
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if (a[0] !== 8'd1 || a[1] !== 8'd4 || a[2] !== 8'bx) failed = 1;
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release a[1];
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#0 $display("%b %b %b", a[0], a[1], a[2]);
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if (a[0] !== 8'd1 || a[1] !== 8'd4 || a[2] !== 8'bx) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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// Check different parts of a variable can be procedurally and continuously assigned.
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module test();
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logic [11:0] v;
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assign v[7:4] = 4'd1;
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reg failed = 0;
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initial begin
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v[11:8] = 4'd2;
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#0 $display("%b", v);
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if (v !== 12'b00100001xxxx) failed = 1;
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/*
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* IEEE 1800-2017 states that "A force or release statement shall not be
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* applied to a variable that is being assigned by a mixture of continuous
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* and procedural assignments.", but some other compilers allow this. It
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* looks to be more work to detect and report it as an error than to allow
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* it.
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*/
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force v[7:4] = 8'd3;
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#0 $display("%b", v);
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if (v !== 12'b00100011xxxx) failed = 1;
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force v[11:8] = 8'd4;
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#0 $display("%b", v);
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if (v !== 12'b01000011xxxx) failed = 1;
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release v[7:4];
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#0 $display("%b", v);
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if (v !== 12'b01000001xxxx) failed = 1;
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release v[11:8];
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#0 $display("%b", v);
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if (v !== 12'b01000001xxxx) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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// Check entire array cannot be both procedurally and continuously assigned.
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module test();
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logic [7:0] p[1:0];
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logic [7:0] q[1:0];
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assign q = p;
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initial begin
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q = '{ 8'd0, 8'd0 };
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end
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endmodule
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// Check array word cannot be both procedurally and continuously assigned.
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module test();
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logic [7:0] p[1:0];
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logic [7:0] q[1:0];
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assign p[1] = 8'd2;
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assign q = p;
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integer i;
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initial begin
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p[0] = 8'd3;
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p[1] = 8'd4;
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p[i] = 8'd5;
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q[0] = 8'd6;
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q[1] = 8'd7;
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end
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endmodule
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// Check entire vector cannot be both procedurally and continuously assigned.
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module test();
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logic [7:0] p;
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logic [7:0] q;
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assign q = p;
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initial begin
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q = 8'd0;
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end
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endmodule
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// Check vector part cannot be both procedurally and continuously assigned.
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module test();
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logic [7:0] v;
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assign v[5:2] = 4'd0;
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integer lsb = 0;
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integer msb = 7;
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initial begin
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v[1:0] = 2'd1;
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v[3:2] = 2'd1;
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v[5:4] = 2'd1;
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v[7:6] = 2'd1;
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v[0 +: 2] = 2'd2;
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v[2 +: 2] = 2'd2;
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v[5 -: 2] = 2'd2;
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v[7 -: 2] = 2'd2;
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v[lsb +: 2] = 2'd3;
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v[msb -: 2] = 2'd3;
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v[0] = 1'b1;
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v[2] = 1'b1;
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v[4] = 1'b1;
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v[6] = 1'b1;
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v[lsb] = 1'b1;
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v[msb] = 1'b1;
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end
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endmodule
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@ -204,6 +204,12 @@ sv_foreach9 vvp_tests/sv_foreach9.json
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sv_foreach10 vvp_tests/sv_foreach10.json
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sv_interface vvp_tests/sv_interface.json
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sv_literals vvp_tests/sv_literals.json
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sv_mixed_assign1 vvp_tests/sv_mixed_assign1.json
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sv_mixed_assign2 vvp_tests/sv_mixed_assign2.json
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sv_mixed_assign_error1 vvp_tests/sv_mixed_assign_error1.json
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sv_mixed_assign_error2 vvp_tests/sv_mixed_assign_error2.json
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sv_mixed_assign_error3 vvp_tests/sv_mixed_assign_error3.json
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sv_mixed_assign_error4 vvp_tests/sv_mixed_assign_error4.json
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sv_module_port1 vvp_tests/sv_module_port1.json
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sv_module_port2 vvp_tests/sv_module_port2.json
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sv_module_port3 vvp_tests/sv_module_port3.json
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{
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"type" : "NI",
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"source" : "sv_mixed_assign1.v",
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"iverilog-args" : [ "-g2009" ]
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}
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{
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"type" : "NI",
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"source" : "sv_mixed_assign1.v",
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"iverilog-args" : [ "-g2009" ]
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}
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{
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"type" : "CE",
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"source" : "sv_mixed_assign_error1.v",
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"gold" : "sv_mixed_assign_error1",
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"iverilog-args" : [ "-g2009" ]
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}
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{
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"type" : "CE",
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"source" : "sv_mixed_assign_error1.v",
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"gold" : "sv_mixed_assign_error1",
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"iverilog-args" : [ "-g2009" ]
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}
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{
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"type" : "CE",
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"source" : "sv_mixed_assign_error1.v",
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"gold" : "sv_mixed_assign_error1",
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"iverilog-args" : [ "-g2009" ]
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}
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{
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"type" : "CE",
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"source" : "sv_mixed_assign_error1.v",
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"gold" : "sv_mixed_assign_error1",
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"iverilog-args" : [ "-g2009" ]
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}
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