Infrastructure for elaborating analog statements.
Put together the infrastructure for elaborating analog statements, including create the NetAnalogTop objects that hold analog statements and are in turn held by the design. While doing this, clean up the various unique initial/always enumerations to use the ivl_process_type_t type.
This commit is contained in:
parent
365960df9d
commit
5aa810dde7
20
AStatement.h
20
AStatement.h
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@ -20,11 +20,15 @@
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*/
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# include <map>
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# include "ivl_target.h"
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# include "StringHeap.h"
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# include "LineInfo.h"
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# include "PExpr.h"
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class PExpr;
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class NetAnalog;
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class NetScope;
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class Design;
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class AStatement : public LineInfo {
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@ -33,6 +37,11 @@ class AStatement : public LineInfo {
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virtual ~AStatement() =0;
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virtual void dump(ostream&out, unsigned ind) const;
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virtual NetAnalog* elaborate(Design*des, NetScope*scope) const;
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virtual void elaborate_scope(Design*des, NetScope*scope) const;
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virtual void elaborate_sig(Design*des, NetScope*scope) const;
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map<perm_string,PExpr*> attributes;
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private: // not implemented
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AStatement(const AStatement&);
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@ -65,20 +74,23 @@ class AContrib : public AStatement {
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class AProcess : public LineInfo {
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public:
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enum Type { PR_INITIAL, PR_ALWAYS };
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AProcess(Type t, AStatement*st)
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AProcess(ivl_process_type_t t, AStatement*st)
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: type_(t), statement_(st) { }
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~AProcess();
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bool elaborate(Design*des, NetScope*scope) const;
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ivl_process_type_t type() const { return type_; }
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AStatement*statement() { return statement_; }
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map<perm_string,PExpr*> attributes;
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// Dump the analog process
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void dump(ostream&out, unsigned ind) const;
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private:
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Type type_;
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ivl_process_type_t type_;
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AStatement*statement_;
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private: // not implemented
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@ -116,9 +116,10 @@ distclean: clean
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TT = t-dll.o t-dll-api.o t-dll-expr.o t-dll-proc.o
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FF = cprop.o nodangle.o synth.o synth2.o syn-rules.o
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O = main.o async.o design_dump.o discipline.o dup_expr.o elaborate.o elab_expr.o \
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O = main.o async.o design_dump.o discipline.o dup_expr.o \
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elaborate.o elab_expr.o elaborate_analog.o \
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elab_lval.o elab_net.o elab_pexpr.o elab_scope.o \
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elab_sig.o emit.o eval.o eval_attrib.o \
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elab_sig.o elab_sig_analog.o emit.o eval.o eval_attrib.o \
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eval_tree.o expr_synth.o functor.o lexor.o lexor_keyword.o link_const.o \
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load_module.o netlist.o netmisc.o net_assign.o \
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net_design.o net_event.o net_expr.o net_func.o \
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@ -20,6 +20,7 @@
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*/
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# include <string>
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# include "ivl_target.h"
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# include "svector.h"
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# include "StringHeap.h"
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# include "PDelays.h"
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@ -46,16 +47,14 @@ class NetScope;
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class PProcess : public LineInfo {
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public:
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enum Type { PR_INITIAL, PR_ALWAYS };
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PProcess(Type t, Statement*st)
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PProcess(ivl_process_type_t t, Statement*st)
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: type_(t), statement_(st) { }
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virtual ~PProcess();
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bool elaborate(Design*des, NetScope*scope) const;
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Type type() const { return type_; }
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ivl_process_type_t type() const { return type_; }
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Statement*statement() { return statement_; }
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map<perm_string,PExpr*> attributes;
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@ -63,7 +62,7 @@ class PProcess : public LineInfo {
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virtual void dump(ostream&out, unsigned ind) const;
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private:
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Type type_;
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ivl_process_type_t type_;
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Statement*statement_;
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};
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33
async.cc
33
async.cc
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2002-2008 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -16,9 +16,6 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: async.cc,v 1.7 2004/01/18 23:26:54 steve Exp $"
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#endif
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# include "config.h"
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@ -87,34 +84,8 @@ bool NetProc::is_asynchronous()
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bool NetProcTop::is_asynchronous()
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{
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if (type_ == NetProcTop::KINITIAL)
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if (type_ == IVL_PR_INITIAL)
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return false;
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return statement_->is_asynchronous();
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}
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/*
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* $Log: async.cc,v $
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* Revision 1.7 2004/01/18 23:26:54 steve
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* The is_combinational function really need not recurse.
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*
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* Revision 1.6 2003/12/20 00:33:39 steve
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* More thorough check that NetEvWait is asynchronous.
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*
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* Revision 1.5 2003/09/04 20:28:05 steve
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* Support time0 resolution of combinational threads.
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*
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* Revision 1.4 2002/08/18 22:07:16 steve
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* Detect temporaries in sequential block synthesis.
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*
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* Revision 1.3 2002/08/12 01:34:58 steve
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* conditional ident string using autoconfig.
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*
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* Revision 1.2 2002/07/04 00:24:16 steve
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* initial statements are not asynchronous.
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*
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* Revision 1.1 2002/06/30 02:21:31 steve
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* Add structure for asynchronous logic synthesis.
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*
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*/
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@ -702,11 +702,11 @@ void NetUDP::dump_node(ostream&o, unsigned ind) const
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void NetProcTop::dump(ostream&o, unsigned ind) const
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{
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switch (type_) {
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case NetProcTop::KINITIAL:
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case IVL_PR_INITIAL:
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o << "initial /* " << get_fileline() << " in "
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<< scope_path(scope_) << " */" << endl;
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break;
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case NetProcTop::KALWAYS:
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case IVL_PR_ALWAYS:
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o << "always /* " << get_fileline() << " in "
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<< scope_path(scope_) << " */" << endl;
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break;
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@ -40,6 +40,7 @@
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# include "PTask.h"
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# include "PWire.h"
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# include "Statement.h"
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# include "AStatement.h"
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# include "netlist.h"
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# include "util.h"
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# include <typeinfo>
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@ -1242,3 +1243,12 @@ void PWhile::elaborate_scope(Design*des, NetScope*scope) const
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if (statement_)
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statement_ -> elaborate_scope(des, scope);
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}
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/*
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* The base statement does not have sub-statements and does not
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* introduce any scope, so this is a no-op.
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*/
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void AStatement::elaborate_scope(Design*, NetScope*) const
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{
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}
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@ -0,0 +1,30 @@
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/*
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* Copyright (c) 2008 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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# include "config.h"
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# include "AStatement.h"
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# include <cstdlib>
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# include <iostream>
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void AStatement::elaborate_sig(Design*des, NetScope*scope) const
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{
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}
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20
elaborate.cc
20
elaborate.cc
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@ -3502,15 +3502,7 @@ bool PProcess::elaborate(Design*des, NetScope*scope) const
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return false;
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}
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NetProcTop*top=0;
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switch (type()) {
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case PProcess::PR_INITIAL:
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top = new NetProcTop(scope, NetProcTop::KINITIAL, cur);
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break;
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case PProcess::PR_ALWAYS:
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top = new NetProcTop(scope, NetProcTop::KALWAYS, cur);
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break;
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}
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NetProcTop*top=new NetProcTop(scope, type(), cur);
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ivl_assert(*this, top);
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// Evaluate the attributes for this process, if there
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@ -3535,7 +3527,7 @@ bool PProcess::elaborate(Design*des, NetScope*scope) const
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gets into its wait statement before non-combinational
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code is executed. */
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do {
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if (top->type() != NetProcTop::KALWAYS)
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if (top->type() != IVL_PR_ALWAYS)
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break;
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NetEvWait*st = dynamic_cast<NetEvWait*>(top->statement());
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@ -3958,6 +3950,12 @@ bool PScope::elaborate_behaviors_(Design*des, NetScope*scope) const
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result_flag &= (*st)->elaborate(des, scope);
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}
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for (list<AProcess*>::const_iterator st = analog_behaviors.begin()
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; st != analog_behaviors.end() ; st ++ ) {
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result_flag &= (*st)->elaborate(des, scope);
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}
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return result_flag;
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}
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@ -4045,7 +4043,7 @@ bool Design::check_always_delay() const
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* a runtime infinite loop will happen. If we possible have some
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* delay then print a warning that an infinite loop is possible.
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*/
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if (pr->type() == NetProcTop::KALWAYS) {
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if (pr->type() == IVL_PR_ALWAYS) {
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DelayType dly_type = pr->statement()->delay_type();
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if (dly_type == NO_DELAY || dly_type == ZERO_DELAY) {
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@ -0,0 +1,60 @@
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/*
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* Copyright (c) 2008 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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# include "config.h"
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# include "AStatement.h"
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# include "util.h"
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# include <typeinfo>
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NetAnalog* AStatement::elaborate(Design*des, NetScope*scope) const
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{
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cerr << get_fileline() << ": sorry: I don't yet know how to elaborate"
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<< " his kind of analog statement." << endl;
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cerr << get_fileline() << ": : typeid = " << typeid(*this).name() << endl;
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return 0;
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}
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bool AProcess::elaborate(Design*des, NetScope*scope) const
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{
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NetAnalog*statement = statement_->elaborate(des, scope);
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if (statement == 0)
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return false;
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NetAnalogTop*top = new NetAnalogTop(scope, type_, statement);
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// Evaluate the attributes for this process, if there
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// are any. These attributes are to be attached to the
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// NetProcTop object.
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struct attrib_list_t*attrib_list = 0;
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unsigned attrib_list_n = 0;
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attrib_list = evaluate_attributes(attributes, attrib_list_n, des, scope);
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for (unsigned adx = 0 ; adx < attrib_list_n ; adx += 1)
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top->attribute(attrib_list[adx].key,
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attrib_list[adx].val);
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delete[]attrib_list;
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top->set_line(*this);
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des->add_process(top);
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return true;
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}
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@ -36,7 +36,7 @@
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# include "ivl_assert.h"
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Design:: Design()
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: errors(0), nodes_(0), procs_(0), lcounter_(0)
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: errors(0), nodes_(0), procs_(0), aprocs_(0), lcounter_(0)
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{
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procs_idx_ = 0;
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des_precision_ = 0;
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@ -764,6 +764,11 @@ void Design::add_process(NetProcTop*pro)
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procs_ = pro;
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}
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void Design::add_process(NetAnalogTop*pro)
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{
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pro->next_ = aprocs_;
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aprocs_ = pro;
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}
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void Design::delete_process(NetProcTop*top)
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{
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assert(top);
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12
netlist.cc
12
netlist.cc
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@ -850,7 +850,7 @@ NetProc::~NetProc()
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{
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}
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NetProcTop::NetProcTop(NetScope*s, Type t, NetProc*st)
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NetProcTop::NetProcTop(NetScope*s, ivl_process_type_t t, NetProc*st)
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: type_(t), statement_(st), scope_(s)
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{
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}
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@ -875,6 +875,16 @@ NetScope* NetProcTop::scope()
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return scope_;
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}
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NetAnalogTop::NetAnalogTop(NetScope*scope, ivl_process_type_t t, NetAnalog*st)
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: type_(t), statement_(st), scope_(scope)
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{
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next_ = 0;
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}
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NetAnalogTop::~NetAnalogTop()
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{
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}
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const NetScope* NetProcTop::scope() const
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{
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return scope_;
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40
netlist.h
40
netlist.h
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@ -3044,12 +3044,10 @@ class NetWhile : public NetProc {
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class NetProcTop : public LineInfo, public Attrib {
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public:
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enum Type { KINITIAL, KALWAYS };
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NetProcTop(NetScope*s, Type t, class NetProc*st);
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NetProcTop(NetScope*s, ivl_process_type_t t, class NetProc*st);
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~NetProcTop();
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Type type() const { return type_; }
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ivl_process_type_t type() const { return type_; }
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NetProc*statement();
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const NetProc*statement() const;
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@ -3074,7 +3072,7 @@ class NetProcTop : public LineInfo, public Attrib {
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bool emit(struct target_t*tgt) const;
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private:
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const Type type_;
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const ivl_process_type_t type_;
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NetProc*const statement_;
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NetScope*scope_;
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@ -3082,6 +3080,35 @@ class NetProcTop : public LineInfo, public Attrib {
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NetProcTop*next_;
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};
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class NetAnalog : public LineInfo, public Attrib {
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};
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class NetAnalogTop : public LineInfo, public Attrib {
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public:
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NetAnalogTop(NetScope*scope, ivl_process_type_t t, NetAnalog*st);
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~NetAnalogTop();
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ivl_process_type_t type() const { return type_; }
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NetAnalog*statement();
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const NetAnalog*statement() const;
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NetScope*scope();
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const NetScope*scope() const;
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void dump(ostream&, unsigned ind) const;
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bool emit(struct target_t*tgt) const;
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private:
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const ivl_process_type_t type_;
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NetAnalog* statement_;
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NetScope*scope_;
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friend class Design;
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NetAnalogTop*next_;
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};
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/*
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* This class represents a binary operator, with the left and right
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* operands and a single character for the operator. The operator
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@ -3822,6 +3849,7 @@ class Design {
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// PROCESSES
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void add_process(NetProcTop*);
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void add_process(NetAnalogTop*);
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void delete_process(NetProcTop*);
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bool check_always_delay() const;
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@ -3853,6 +3881,8 @@ class Design {
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NetProcTop*procs_;
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NetProcTop*procs_idx_;
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NetAnalogTop*aprocs_;
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map<string,const char*> flags_;
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int des_precision_;
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6
parse.y
6
parse.y
|
|
@ -2093,16 +2093,16 @@ module_item
|
|||
/* Always and initial items are behavioral processes. */
|
||||
|
||||
| attribute_list_opt K_always statement
|
||||
{ PProcess*tmp = pform_make_behavior(PProcess::PR_ALWAYS, $3, $1);
|
||||
{ PProcess*tmp = pform_make_behavior(IVL_PR_ALWAYS, $3, $1);
|
||||
FILE_NAME(tmp, @2);
|
||||
}
|
||||
| attribute_list_opt K_initial statement
|
||||
{ PProcess*tmp = pform_make_behavior(PProcess::PR_INITIAL, $3, $1);
|
||||
{ PProcess*tmp = pform_make_behavior(IVL_PR_INITIAL, $3, $1);
|
||||
FILE_NAME(tmp, @2);
|
||||
}
|
||||
|
||||
| attribute_list_opt K_analog analog_statement
|
||||
{ pform_make_analog_behavior(@2, AProcess::PR_ALWAYS, $3); }
|
||||
{ pform_make_analog_behavior(@2, IVL_PR_ALWAYS, $3); }
|
||||
|
||||
/* The task declaration rule matches the task declaration
|
||||
header, then pushes the function scope. This causes the
|
||||
|
|
|
|||
4
pform.cc
4
pform.cc
|
|
@ -1304,7 +1304,7 @@ void pform_make_reginit(const struct vlltype&li,
|
|||
FILE_NAME(lval, li);
|
||||
PAssign*ass = new PAssign(lval, expr, true);
|
||||
FILE_NAME(ass, li);
|
||||
PProcess*top = new PProcess(PProcess::PR_INITIAL, ass);
|
||||
PProcess*top = new PProcess(IVL_PR_INITIAL, ass);
|
||||
FILE_NAME(top, li);
|
||||
|
||||
pform_put_behavior_in_scope(top);
|
||||
|
|
@ -1947,7 +1947,7 @@ svector<PWire*>* pform_make_udp_input_ports(list<perm_string>*names)
|
|||
return out;
|
||||
}
|
||||
|
||||
PProcess* pform_make_behavior(PProcess::Type type, Statement*st,
|
||||
PProcess* pform_make_behavior(ivl_process_type_t type, Statement*st,
|
||||
svector<named_pexpr_t*>*attr)
|
||||
{
|
||||
PProcess*pp = new PProcess(type, st);
|
||||
|
|
|
|||
4
pform.h
4
pform.h
|
|
@ -311,7 +311,7 @@ extern void pform_module_specify_path(PSpecPath*obj);
|
|||
* pform_make_behavior creates processes that are declared with always
|
||||
* or initial items.
|
||||
*/
|
||||
extern PProcess* pform_make_behavior(PProcess::Type, Statement*,
|
||||
extern PProcess* pform_make_behavior(ivl_process_type_t, Statement*,
|
||||
svector<named_pexpr_t*>*attr);
|
||||
|
||||
extern svector<PWire*>* pform_make_udp_input_ports(list<perm_string>*);
|
||||
|
|
@ -396,7 +396,7 @@ extern void pform_dump(ostream&out, const discipline_t*);
|
|||
/* ** pform_analog.cc
|
||||
*/
|
||||
extern void pform_make_analog_behavior(const struct vlltype&loc,
|
||||
AProcess::Type type, AStatement*st);
|
||||
ivl_process_type_t type, AStatement*st);
|
||||
|
||||
extern AStatement*pform_contribution_statement(const struct vlltype&loc,
|
||||
PExpr*lval, PExpr*rval);
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ AStatement* pform_contribution_statement(const struct vlltype&loc,
|
|||
return tmp;
|
||||
}
|
||||
|
||||
void pform_make_analog_behavior(const struct vlltype&loc, AProcess::Type pt,
|
||||
void pform_make_analog_behavior(const struct vlltype&loc, ivl_process_type_t pt,
|
||||
AStatement*statement)
|
||||
{
|
||||
AProcess*proc = new AProcess(pt, statement);
|
||||
|
|
|
|||
|
|
@ -135,6 +135,18 @@ ostream& operator<< (ostream&o, const pform_name_t&that)
|
|||
return o;
|
||||
}
|
||||
|
||||
std::ostream& operator << (std::ostream&out, ivl_process_type_t pt)
|
||||
{
|
||||
switch (pt) {
|
||||
case IVL_PR_INITIAL:
|
||||
out << "initial";
|
||||
break;
|
||||
case IVL_PR_ALWAYS:
|
||||
out << "always";
|
||||
break;
|
||||
}
|
||||
return out;
|
||||
}
|
||||
|
||||
std::ostream& operator << (std::ostream&out, ddomain_t dom)
|
||||
{
|
||||
|
|
@ -900,16 +912,8 @@ void PWhile::dump(ostream&out, unsigned ind) const
|
|||
|
||||
void PProcess::dump(ostream&out, unsigned ind) const
|
||||
{
|
||||
switch (type_) {
|
||||
case PProcess::PR_INITIAL:
|
||||
out << setw(ind) << "" << "initial";
|
||||
break;
|
||||
case PProcess::PR_ALWAYS:
|
||||
out << setw(ind) << "" << "always";
|
||||
break;
|
||||
}
|
||||
|
||||
out << " /* " << get_fileline() << " */" << endl;
|
||||
out << setw(ind) << "" << type_
|
||||
<< " /* " << get_fileline() << " */" << endl;
|
||||
|
||||
dump_attributes_map(out, attributes, ind+2);
|
||||
|
||||
|
|
@ -919,10 +923,10 @@ void PProcess::dump(ostream&out, unsigned ind) const
|
|||
void AProcess::dump(ostream&out, unsigned ind) const
|
||||
{
|
||||
switch (type_) {
|
||||
case AProcess::PR_INITIAL:
|
||||
case IVL_PR_INITIAL:
|
||||
out << setw(ind) << "" << "analog initial";
|
||||
break;
|
||||
case AProcess::PR_ALWAYS:
|
||||
case IVL_PR_ALWAYS:
|
||||
out << setw(ind) << "" << "analog";
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -335,7 +335,7 @@ static void syn_start_process(NetProcTop*t)
|
|||
last_ = first_;
|
||||
ptr_ = first_;
|
||||
|
||||
first_->token = (t->type() == NetProcTop::KALWAYS)? S_ALWAYS : S_INITIAL;
|
||||
first_->token = (t->type() == IVL_PR_ALWAYS)? S_ALWAYS : S_INITIAL;
|
||||
first_->top = t;
|
||||
first_->next_ = 0;
|
||||
|
||||
|
|
|
|||
22
sync.cc
22
sync.cc
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
|
||||
* Copyright (c) 2002-2008 Stephen Williams (steve@icarus.com)
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
|
|
@ -16,9 +16,6 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: sync.cc,v 1.3 2002/09/24 00:58:35 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "config.h"
|
||||
|
||||
|
|
@ -59,23 +56,8 @@ bool NetEvWait::is_synchronous()
|
|||
|
||||
bool NetProcTop::is_synchronous()
|
||||
{
|
||||
if (type_ == NetProcTop::KINITIAL)
|
||||
if (type_ == IVL_PR_INITIAL)
|
||||
return false;
|
||||
|
||||
return statement_->is_synchronous();
|
||||
}
|
||||
|
||||
/*
|
||||
* $Log: sync.cc,v $
|
||||
* Revision 1.3 2002/09/24 00:58:35 steve
|
||||
* More detailed check of process edge events.
|
||||
*
|
||||
* Revision 1.2 2002/09/16 21:55:06 steve
|
||||
* Reject multiple probes on synchronous logic.
|
||||
*
|
||||
* Revision 1.1 2002/09/16 00:30:33 steve
|
||||
* Add to synth2 support for synthesis of
|
||||
* synchronous logic. This includes DFF enables
|
||||
* modeled by if/then/else.
|
||||
*
|
||||
*/
|
||||
|
|
|
|||
4
synth.cc
4
synth.cc
|
|
@ -131,10 +131,10 @@ void synth_f::process(class Design*des, class NetProcTop*top)
|
|||
{
|
||||
top_ = top;
|
||||
switch (top->type()) {
|
||||
case NetProcTop::KALWAYS:
|
||||
case IVL_PR_ALWAYS:
|
||||
proc_always_(des);
|
||||
break;
|
||||
case NetProcTop::KINITIAL:
|
||||
case IVL_PR_INITIAL:
|
||||
proc_initial_(des);
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -39,16 +39,8 @@ bool dll_target::process(const NetProcTop*net)
|
|||
ivl_process_t obj = (struct ivl_process_s*)
|
||||
calloc(1, sizeof(struct ivl_process_s));
|
||||
|
||||
switch (net->type()) {
|
||||
case NetProcTop::KINITIAL:
|
||||
obj->type_ = IVL_PR_INITIAL;
|
||||
break;
|
||||
case NetProcTop::KALWAYS:
|
||||
obj->type_ = IVL_PR_ALWAYS;
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
}
|
||||
obj->type_ = net->type();
|
||||
|
||||
FILE_NAME(obj, net);
|
||||
|
||||
/* Save the scope of the process. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue