Fix resizing of constant bit vectors
Emitting a VHDL expression like Resize("01", 32) is ambiguous
between interpreting "01" as a Signed or an Unsigned. There's
no point actually outputting this as we can sign-extend the
constant value in the code generator, which is what this
patch does.
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parent
4394aff909
commit
a7cbb38248
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@ -222,7 +222,7 @@ vhdl_expr *vhdl_const_int::to_vector(vhdl_type_name_t name, int w)
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}
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int vhdl_const_bits::bits_to_int() const
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{
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{
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char msb = value_[value_.size() - 1];
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int result = 0, bit;
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for (int i = sizeof(int)*8 - 1; i >= 0; i--) {
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@ -248,6 +248,11 @@ vhdl_expr *vhdl_const_bits::to_std_logic()
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return new vhdl_const_bit(lsb);
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}
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char vhdl_const_bits::sign_bit() const
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{
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return signed_ ? value_[value_.length()-1] : '0';
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}
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vhdl_expr *vhdl_const_bits::to_vector(vhdl_type_name_t name, int w)
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{
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if (name == VHDL_TYPE_STD_LOGIC_VECTOR) {
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@ -256,7 +261,7 @@ vhdl_expr *vhdl_const_bits::to_vector(vhdl_type_name_t name, int w)
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}
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else if (name == VHDL_TYPE_SIGNED || name == VHDL_TYPE_UNSIGNED) {
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// Extend with sign bit
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value_.resize(w, value_[0]);
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value_.resize(w, sign_bit());
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return this;
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}
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else
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@ -268,6 +273,16 @@ vhdl_expr *vhdl_const_bits::to_integer()
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return new vhdl_const_int(bits_to_int());
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}
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vhdl_expr *vhdl_const_bits::resize(int w)
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{
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// Rather than generating a call to Resize, when can just sign-extend
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// the bits here. As well as looking better, this avoids any ambiguity
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// between which of the signed/unsigned versions of Resize to use.
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value_.resize(w, sign_bit());
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return this;
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}
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vhdl_expr *vhdl_const_bit::to_integer()
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{
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return new vhdl_const_int(bit_ == '1' ? 1 : 0);
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@ -175,8 +175,10 @@ public:
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vhdl_expr *to_integer();
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vhdl_expr *to_std_logic();
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vhdl_expr *to_vector(vhdl_type_name_t name, int w);
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vhdl_expr *resize(int w);
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private:
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int bits_to_int() const;
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char sign_bit() const;
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std::string value_;
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bool qualified_, signed_;
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