Use multimap in VHDL Component Instantiations

Port map aspects were held in std::maps. Because
of that, in case of multiple assignments to the same
port, some assignments were lost and in effect vhdlpp
produced correct verilog code from a buggy VHDL.

Std::map was replaced by std::multimap. Thanks to it
we can gather this multiple assignments and detect them
in the elaboration phase.

vhdlpp/architec.cc

@@ -71,7 +71,7 @@ ComponentInstantiation::ComponentInstantiation(perm_string i, perm_string c,
       while (! ports->empty()) {
 	    named_expr_t*cur = ports->front();
 	    ports->pop_front();
-	    port_map_[cur->name()] = cur->expr();
+	    port_map_.insert(make_pair(cur->name(), cur->expr()));
       }
 }
 

vhdlpp/architec.h

@@ -122,7 +122,7 @@ class ComponentInstantiation  : public Architecture::Statement {
       perm_string iname_;
       perm_string cname_;
 
-      std::map<perm_string,Expression*> port_map_;
+      std::multimap<perm_string,Expression*> port_map_;
 };
 
 class ProcessStatement : public Architecture::Statement {

vhdlpp/architec_elaborate.cc

@@ -56,7 +56,7 @@ int ComponentInstantiation::elaborate(Entity*ent, Architecture*arc)
 
       map<perm_string,const InterfacePort*> port_match;
 
-      for (map<perm_string,Expression*>::iterator cur = port_map_.begin()
+      for (multimap<perm_string,Expression*>::const_iterator cur = port_map_.begin()
 		 ; cur != port_map_.end() ; ++cur) {
 	    const InterfacePort*iport = base->find_port(cur->first);
 	    if (iport == 0) {
@@ -75,6 +75,15 @@ int ComponentInstantiation::elaborate(Entity*ent, Architecture*arc)
 		  cur->second->elaborate_expr(ent, arc, iport->type);
       }
 
+      //each formal (component's) port should be associated at most once
+      for(multimap<perm_string,Expression*>::const_iterator cur = port_map_.begin()
+          ; cur != port_map_.end() ; ++cur)
+        if(port_map_.count(cur->first) != 1) {
+          //at least one port is associated twice or more
+          cerr << cur->second->get_fileline() << ": error: At least one port is associated"
+          << " twice or more in a single component instantiation." << endl;
+          errors += 1;
+      }
       return errors;
 }
 

vhdlpp/architec_emit.cc

@@ -105,7 +105,7 @@ int ComponentInstantiation::emit(ostream&out, Entity*ent, Architecture*arc)
 
       out << cname_ << " " << iname_ << "(";
       const char*comma = "";
-      for (map<perm_string,Expression*>::iterator cur = port_map_.begin()
+      for (multimap<perm_string,Expression*>::iterator cur = port_map_.begin()
 		 ; cur != port_map_.end() ; ++cur) {
 	      // Skip unconnected ports
 	    if (cur->second == 0)