Add short section on VHDL to man page

driver/iverilog.man

@@ -223,6 +223,12 @@ mostly by EDIF format output. The Icarus Verilog fpga code generator
 can generate complete designs or EDIF macros that can in turn be
 imported into larger designs by other tools. The \fBfpga\fP target
 implies the synthesis \fB-S\fP flag.
+.TP 8
+.B vhdl
+This target produces a VHDL translation of the Verilog netlist. The
+output is a single file containing VHDL entities corresponding to 
+the modules in the Verilog source code. Note that only a subset of
+the Verilog language is supported.  See the wiki for more information.
 
 .SH "WARNING TYPES"
 These are the types of warnings that can be selected by the \fB-W\fP