Fix check for SV continuous assign to variable.

SystemVerilog allows a variable to be used as a variable OR
as an unresolved wire. The detection of this case was checking
the references to the affected value, instead of the l-value
references.
(cherry picked from commit cceeaa30f27260cd444015cb39b04353cb858768)

elab_net.cc

@@ -443,7 +443,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
 	   wire. */
       if (gn_var_can_be_uwire()
 	  && (sig->type() == NetNet::REG)
-	  && (sig->peek_eref() == 0) ) {
+	  && (sig->peek_lref() == 0) ) {
 	    sig->type(NetNet::UNRESOLVED_WIRE);
       }