Merge branch 'vhdl' of git@github.com:nickg/iverilog into vhdl

Conflicts:

	tgt-vhdl/vhdl_syntax.cc

tgt-vhdl/process.cc

@@ -158,7 +158,7 @@ static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc)
    // If this is an initial process, push signal initialisation
    // into the declarations
    if (ivl_process_type(proc) == IVL_PR_INITIAL)
-      vhdl_proc->set_initial(true);
+      vhdl_proc->get_scope()->set_initializing(true);
    
    ivl_statement_t stmt = ivl_process_stmt(proc);
    int rc = draw_stmt(vhdl_proc, vhdl_proc->get_container(), stmt);

tgt-vhdl/stmt.cc

@@ -129,6 +129,7 @@ static int draw_nbassign(vhdl_process *proc, stmt_container *container,
          return 1;
       vhdl_expr *rhs = rhs_raw->cast(decl->get_type());
 
+      // TODO: CORRECT THIS!!!
       // If this is an `inital' process and we haven't yet
       // generated a `wait' statement then this assignment
       // needs to be moved to the declaration. Otherwise the
@@ -139,8 +140,10 @@ static int draw_nbassign(vhdl_process *proc, stmt_container *container,
       // then use the uninitialized signal value.
       // The second test ensures that we only try to initialise
       // internal signals not ports
-      if (proc->is_initial() && ivl_signal_port(sig) == IVL_SIP_NONE
+      if (proc->get_scope()->initializing()
+          && ivl_signal_port(sig) == IVL_SIP_NONE
           && rhs->constant()) {
+
          decl->set_initial(rhs);
       }
       else {
@@ -185,8 +188,11 @@ static int draw_assign(vhdl_process *proc, stmt_container *container,
 
       // As with non-blocking assignment, push constant assignments
       // into the initialisation if we can
-      if (proc->is_initial() && ivl_signal_port(sig) == IVL_SIP_NONE
-          && rhs->constant() && !proc->get_scope()->have_declared(signame)) {
+      if (proc->get_scope()->initializing()
+          && ivl_signal_port(sig) == IVL_SIP_NONE
+          && rhs->constant()
+          && !proc->get_scope()->have_declared(signame)) {
+
          decl->set_initial(rhs);
 
          // This signal may be used e.g. in a loop test so we need
@@ -281,7 +287,8 @@ static int draw_delay(vhdl_process *proc, stmt_container *container,
    
    // Any further assignments occur after simulation time 0
    // so they cannot be used to initialize signal declarations
-   proc->set_initial(false);
+   // (if this scope is an initial process)
+   proc->get_scope()->set_initializing(false);
    
    return 0;
 }

tgt-vhdl/vhdl_syntax.cc

@@ -26,7 +26,7 @@
 #include <typeinfo>
 
 vhdl_scope::vhdl_scope()
-   : parent_(NULL)
+   : parent_(NULL), init_(false)
 {
 
 }
@@ -106,12 +106,6 @@ void vhdl_entity::emit(std::ofstream &of, int level) const
    arch_->emit(of, level);
 }
 
-vhdl_arch::vhdl_arch(const char *entity, const char *name)
-   : name_(name), entity_(entity)
-{
-   
-}
-
 vhdl_arch::~vhdl_arch()
 {
    delete_children<vhdl_conc_stmt>(stmts_);
@@ -140,12 +134,6 @@ void vhdl_arch::emit(std::ofstream &of, int level) const
    blank_line(of, level);  // Extra blank line after architectures;
 }
 
-vhdl_process::vhdl_process(const char *name)
-   : name_(name), initial_(false)
-{
-
-}
-
 void vhdl_process::add_sensitivity(const char *name)
 {
    sens_.push_back(name);

tgt-vhdl/vhdl_syntax.hh

@@ -517,6 +517,8 @@ private:
 
 /*
  * Contains a list of declarations in a hierarchy.
+ * A scope can be `initializing' where assignments automatically
+ * create initial values for declarations.
  */
 class vhdl_scope {
 public:
@@ -531,28 +533,29 @@ public:
    bool empty() const { return decls_.empty(); }
    const decl_list_t &get_decls() const { return decls_; }
    void set_parent(vhdl_scope *p) { parent_ = p; }
+
+   bool initializing() const { return init_; }
+   void set_initializing(bool i) { init_ = i; }
 private:
    decl_list_t decls_;
    vhdl_scope *parent_;
+   bool init_;
 };
 
 
 class vhdl_process : public vhdl_conc_stmt {
 public:
-   vhdl_process(const char *name = "");
+   vhdl_process(const char *name = "") : name_(name) {}
 
    void emit(std::ofstream &of, int level) const;
    stmt_container *get_container() { return &stmts_; }
    void add_sensitivity(const char *name);
    vhdl_scope *get_scope() { return &scope_; }
-   void set_initial(bool i) { initial_ = i; }
-   bool is_initial() const { return initial_; }
 private:
    stmt_container stmts_;
    vhdl_scope scope_;
    std::string name_;
    string_list_t sens_;
-   bool initial_;
 };
 
 
@@ -561,7 +564,8 @@ private:
  */
 class vhdl_arch : public vhdl_element {
 public:
-   vhdl_arch(const char *entity, const char *name);
+   vhdl_arch(const char *entity, const char *name)
+      : name_(name), entity_(entity) {}
    virtual ~vhdl_arch();
 
    void emit(std::ofstream &of, int level=0) const;