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Support default port values in port declarations lists 

Both Verilog (2005) and SystemVerilog support default port values for
variable output ports. SystemVerilog also supports default port values for
input ports. For port declaration lists it is possible to specify the
default value for port identifier.

E.g.

```
module M (
  input integer x, y = 1,
  output integer z, w = 2
) ...
```

Currently the parser only supports specifying the default value for the
first identifier in the list. Extend the parser to also allow to specify
the default value for identifiers in the list.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2022-09-13 10:09:18 +02:00
parent a9bd522fd3
commit a19a07254b
1 changed files with 17 additions and 1 deletions
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18
parse.y
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@ -4332,13 +4332,29 @@ list_of_port_declarations
tmp->push_back($3);
$$ = tmp;
}
| list_of_port_declarations ',' IDENTIFIER
| list_of_port_declarations ',' IDENTIFIER initializer_opt
{ Module::port_t*ptmp;
perm_string name = lex_strings.make($3);
ptmp = pform_module_port_reference(@3, name);
std::vector<Module::port_t*>*tmp = $1;
tmp->push_back(ptmp);
if ($4) {
switch (port_declaration_context.port_type) {
case NetNet::PINOUT:
yyerror(@4, "error: Default port value not allowed for inout ports.");
break;
case NetNet::PINPUT:
pform_requires_sv(@4, "Default port value");
ptmp->default_value = $4;
break;
case NetNet::POUTPUT:
pform_make_var_init(@3, name, $4);
break;
default:
break;
}
}
/* Get the port declaration details, the port type
and what not, from context data stored by the
last port_declaration rule. */