luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

vlog95: Emit if using signed and add the number of errors to the output 

In the starting comment say if the conversion was done with signed support.
If there were errors then add a comment at the end of the file that says
how many errors occurred and add a line after this that prevents the file
from running with out an error. This requires the user to see that errors
occurred and remove the offending line if they want to use the file anyway.
This commit is contained in:
Cary R 2013-02-15 19:21:11 -08:00
parent 8808cd9514
commit 51112131ad
1 changed files with 24 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
tgt-vlog95/vlog95.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2010-2012 Cary R. (cygcary@yahoo.com)
* Copyright (C) 2010-2013 Cary R. (cygcary@yahoo.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -30,7 +30,7 @@
static const char*version_string =
"Icarus Verilog VLOG95 Code Generator " VERSION " (" VERSION_TAG ")\n\n"
"Copyright (C) 2010-2012 Cary R. (cygcary@yahoo.com)\n\n"
"Copyright (C) 2010-2013 Cary R. (cygcary@yahoo.com)\n\n"
" This program is free software; you can redistribute it and/or modify\n"
" it under the terms of the GNU General Public License as published by\n"
" the Free Software Foundation; either version 2 of the License, or\n"
@ -175,8 +175,9 @@ int target_design(ivl_design_t des)
fprintf(vlog_out, " * 1364-1995 Verilog generated by Icarus Verilog "
"VLOG95 Code Generator,\n");
fprintf(vlog_out, " * Version: " VERSION " (" VERSION_TAG ")\n");
fprintf(vlog_out, " * Converted using %s delays.\n",
ivl_design_delay_sel(des));
fprintf(vlog_out, " * Converted using %s delays and %s signed support.\n",
ivl_design_delay_sel(des),
allow_signed ? "with" : "without");
fprintf(vlog_out, " */\n");
sim_precision = ivl_design_time_precision(des);
@ -193,6 +194,25 @@ int target_design(ivl_design_t des)
/* Emit any UDPs that are Icarus generated (D-FF). */
emit_icarus_generated_udps();
/* If there were errors then add this information to the output. */
if (vlog_errors) {
fprintf(vlog_out, "\n");
fprintf(vlog_out, "/*\n");
if (vlog_errors == 1) {
fprintf(vlog_out, " * There was 1 error during "
"translation.\n");
} else {
fprintf(vlog_out, " * There were %d errors during "
"translation.\n",
vlog_errors);
}
fprintf(vlog_out, " */\n");
/* Add something that makes the file invalid to make sure
* the user knows there were errors. */
fprintf(vlog_out, "<Add some text to make sure this file is not "
"valid Verilog>\n");
}
fclose(vlog_out);
/* A do nothing call to prevent warnings about this routine not