Store the currently active entity

tgt-vhdl/process.cc

@@ -31,6 +31,8 @@
  */
 static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc)
 {
+   set_active_entity(ent);
+   
    // Create a new process and store it in the entity's
    // architecture. This needs to be done first or the
    // parent link won't be valid (and draw_stmt needs this

tgt-vhdl/scope.cc

@@ -28,6 +28,19 @@
 static vhdl_expr *translate_logic(vhdl_scope *scope, ivl_net_logic_t log);
 static std::string make_safe_name(ivl_signal_t sig);
 
+static vhdl_entity *g_active_entity = NULL;
+
+vhdl_entity *get_active_entity()
+{
+   return g_active_entity;
+}
+
+void set_active_entity(vhdl_entity *ent)
+{
+   g_active_entity = ent;
+}
+
+
 /*
  * The types of VHDL object a nexus can be converted into.
  */
@@ -409,6 +422,8 @@ static vhdl_entity *create_entity_for(ivl_scope_t scope)
    // retain a 1-to-1 mapping of scope to VHDL element)
    vhdl_arch *arch = new vhdl_arch(tname, "FromVerilog");
    vhdl_entity *ent = new vhdl_entity(tname, derived_from, arch);
+
+   set_active_entity(ent);
    
    // Locate all the signals in this module and add them to
    // the architecture
@@ -558,6 +573,7 @@ static int draw_module(ivl_scope_t scope, ivl_scope_t parent)
    if (NULL == ent)
       ent = create_entity_for(scope);
    assert(ent);
+   set_active_entity(ent);
 
    // Is this module instantiated inside another?
    if (parent != NULL) {

tgt-vhdl/vhdl_target.h

@@ -26,7 +26,8 @@ void remember_entity(vhdl_entity *ent);
 vhdl_entity *find_entity(const string &tname);
 
 ivl_design_t get_vhdl_design();
-//vhdl_entity *get_active_entity();
+vhdl_entity *get_active_entity();
+void set_active_entity(vhdl_entity *ent);
 
 vhdl_var_ref *nexus_to_var_ref(vhdl_scope *arch_scope, ivl_nexus_t nexus);