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Add three tests to exercise interconnection delays in designs

This commit is contained in:
mole99 2023-08-17 14:37:40 +02:00
parent 37119b1504
commit 306e4cfa6b
13 changed files with 530 additions and 0 deletions
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9
ivtest/gold/sdf_interconnect1-vvp-stdout.gold Normal file
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SDF ERROR: ivltests/sdf_interconnect1.sdf:32: Unable to match ModPath in -> out in top.my_design_inst.buffer0
SDF ERROR: ivltests/sdf_interconnect1.sdf:42: Unable to match ModPath in -> out in top.my_design_inst.buffer1
SDF ERROR: ivltests/sdf_interconnect1.sdf:52: Unable to match ModPath in -> out in top.my_design_inst.buffer2
time=0 a=x b=x
time=5000 a=0 b=x
time=5080 a=0 b=0
time=15000 a=1 b=0
time=15080 a=1 b=1
ivltests/sdf_interconnect1.v:59: $finish called at 25000 (1ps)

9
ivtest/gold/sdf_interconnect2-vvp-stdout.gold Normal file
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SDF ERROR: ivltests/sdf_interconnect2.sdf:31: Unable to match ModPath in -> out in top.my_design_inst.buffer0
SDF ERROR: ivltests/sdf_interconnect2.sdf:41: Unable to match ModPath in -> out in top.my_design_inst.buffer1
SDF ERROR: ivltests/sdf_interconnect2.sdf:51: Unable to match ModPath in -> out in top.my_design_inst.buffer2
time=0 a=x b=x
time=5000 a=0 b=x
time=5010 a=0 b=0
time=15000 a=1 b=0
time=15030 a=1 b=1
ivltests/sdf_interconnect2.v:61: $finish called at 25000 (1ps)

24
ivtest/gold/sdf_interconnect3-vvp-stdout.gold Normal file
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SDF ERROR: ivltests/sdf_interconnect3.sdf:41: Unable to match ModPath in -> out in top.my_design_inst.buffer0
SDF ERROR: ivltests/sdf_interconnect3.sdf:51: Unable to match ModPath in -> out in top.my_design_inst.buffer1
SDF ERROR: ivltests/sdf_interconnect3.sdf:61: Unable to match ModPath in -> out in top.my_design_inst.buffer2
SDF ERROR: ivltests/sdf_interconnect3.sdf:71: Unable to match ModPath in -> out in top.my_design_inst.buffer3
time=0 a=x b=x c=x d=x
time=10000 a=0 b=0 c=0 d=x
time=10060 a=0 b=0 c=0 d=0
time=20000 a=1 b=0 c=0 d=0
time=20060 a=1 b=0 c=0 d=1
time=30000 a=0 b=1 c=0 d=1
time=30050 a=0 b=1 c=0 d=0
time=40000 a=1 b=1 c=0 d=0
time=40060 a=1 b=1 c=0 d=1
time=50000 a=0 b=0 c=1 d=1
time=50040 a=0 b=0 c=1 d=0
time=50050 a=0 b=0 c=1 d=1
time=50060 a=0 b=0 c=1 d=0
time=60000 a=1 b=0 c=1 d=0
time=60060 a=1 b=0 c=1 d=1
time=70000 a=0 b=1 c=1 d=1
time=70050 a=0 b=1 c=1 d=0
time=80000 a=1 b=1 c=1 d=0
time=80060 a=1 b=1 c=1 d=1
ivltests/sdf_interconnect3.v:132: $finish called at 90000 (1ps)

56
ivtest/ivltests/sdf_interconnect1.sdf Normal file
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(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "test")
(DATE "Wed Mar 8 12:34:56 2023")
(VENDOR "No Vendor")
(PROGRAM "Human")
(VERSION "1.0.0")
(DIVIDER .)
(VOLTAGE 5.5:5.0:4.5)
(PROCESS "best=0.65:nom=1.0:worst=1.8")
(TEMPERATURE -25.0:25.0:85.0)
(TIMESCALE 1 ns)
(CELL
(CELLTYPE "my_design")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT a buffer0.in (0.010:0.020:0.030) (0.010:0.020:0.030))
(INTERCONNECT buffer0.out buffer1.in (0.010:0.020:0.030) (0.010:0.020:0.030))
(INTERCONNECT buffer1.out buffer2.in (0.010:0.020:0.030) (0.010:0.020:0.030))
(INTERCONNECT buffer2.out b (0.010:0.020:0.030) (0.010:0.020:0.030))
)
)
)
(CELL
(CELLTYPE "buffer")
(INSTANCE buffer0)
(DELAY
(ABSOLUTE
(IOPATH in out (0.1:0.2:0.3) (0.1:0.2:0.3))
)
)
)
(CELL
(CELLTYPE "buffer")
(INSTANCE buffer1)
(DELAY
(ABSOLUTE
(IOPATH in out (0.1:0.2:0.3) (0.1:0.2:0.3))
)
)
)
(CELL
(CELLTYPE "buffer")
(INSTANCE buffer2)
(DELAY
(ABSOLUTE
(IOPATH in out (0.1:0.2:0.3) (0.1:0.2:0.3))
)
)
)
)

68
ivtest/ivltests/sdf_interconnect1.v Normal file
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`timescale 1ns/1ps
/*
This design tests the interconnection delay
for three buffers in series
*/
module buffer (
input in,
output out
);
specify
(in => out) = (0.0:0.0:0.0);
endspecify
assign out = in;
endmodule
module my_design (
input a,
output b
);
wire w1, w2;
buffer buffer0 (
.in (a),
.out (w1)
);
buffer buffer1 (
.in (w1),
.out (w2)
);
buffer buffer2 (
.in (w2),
.out (b)
);
endmodule
module top;
initial begin
$sdf_annotate("ivltests/sdf_interconnect1.sdf", my_design_inst);
$monitor("time=%0t a=%h b=%h", $realtime, a, b);
end
reg a;
wire b;
initial begin
#5;
a <= 1'b0;
#10;
a <= 1'b1;
#10;
$finish;
end
my_design my_design_inst (
.a (a),
.b (b)
);
endmodule

55
ivtest/ivltests/sdf_interconnect2.sdf Normal file
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@ -0,0 +1,55 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "test")
(DATE "Wed Mar 8 12:34:56 2023")
(VENDOR "No Vendor")
(PROGRAM "Human")
(VERSION "1.0.0")
(DIVIDER .)
(VOLTAGE 5.5:5.0:4.5)
(PROCESS "best=0.65:nom=1.0:worst=1.8")
(TEMPERATURE -25.0:25.0:85.0)
(TIMESCALE 1 ns)
(CELL
(CELLTYPE "my_design")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT a buffer0.in (0.000:0.010:0.000) (0.000:0.010:0.000))
(INTERCONNECT a buffer1.in (0.000:0.020:0.000) (0.000:0.020:0.000))
(INTERCONNECT a buffer2.in (0.000:0.030:0.000) (0.000:0.030:0.000))
)
)
)
(CELL
(CELLTYPE "buffer")
(INSTANCE buffer0)
(DELAY
(ABSOLUTE
(IOPATH in out (0.000:0.100:0.000) (0.000:0.100:0.000))
)
)
)
(CELL
(CELLTYPE "buffer")
(INSTANCE buffer1)
(DELAY
(ABSOLUTE
(IOPATH in out (0.000:0.200:0.000) (0.000:0.200:0.000))
)
)
)
(CELL
(CELLTYPE "buffer")
(INSTANCE buffer2)
(DELAY
(ABSOLUTE
(IOPATH in out (0.000:0.300:0.000) (0.000:0.300:0.000))
)
)
)
)

70
ivtest/ivltests/sdf_interconnect2.v Normal file
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`timescale 1ns/1ps
/*
This design tests the interconnection delay
for three buffers in parallel
*/
module buffer (
input in,
output out
);
specify
(in => out) = (0.0:0.0:0.0);
endspecify
assign out = in;
endmodule
module my_design (
input a,
output b
);
wire w1, w2, w3;
buffer buffer0 (
.in (a),
.out (w1)
);
buffer buffer1 (
.in (a),
.out (w2)
);
buffer buffer2 (
.in (a),
.out (w3)
);
assign b = w1 & w2 & w3;
endmodule
module top;
initial begin
$sdf_annotate("ivltests/sdf_interconnect2.sdf", my_design_inst);
$monitor("time=%0t a=%h b=%h", $realtime, a, b);
end
reg a;
wire b;
initial begin
#5;
a <= 1'b0;
#10;
a <= 1'b1;
#10;
$finish;
end
my_design my_design_inst (
.a (a),
.b (b)
);
endmodule

75
ivtest/ivltests/sdf_interconnect3.sdf Normal file
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@ -0,0 +1,75 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "test")
(DATE "Wed Mar 8 12:34:56 2023")
(VENDOR "No Vendor")
(PROGRAM "Human")
(VERSION "1.0.0")
(DIVIDER .)
(VOLTAGE 5.5:5.0:4.5)
(PROCESS "best=0.65:nom=1.0:worst=1.8")
(TEMPERATURE -25.0:25.0:85.0)
(TIMESCALE 1 ns)
(CELL
(CELLTYPE "my_design")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT a buffer0.in (0.000:0.010:0.000) (0.000:0.010:0.000))
(INTERCONNECT b my_xor0.a (0.000:0.010:0.000) (0.000:0.010:0.000))
(INTERCONNECT c my_xor0.b (0.000:0.010:0.000) (0.000:0.010:0.000))
(INTERCONNECT buffer0.out my_xor1.a (0.000:0.010:0.000) (0.000:0.010:0.000))
(INTERCONNECT b my_xor1.b (0.000:0.010:0.000) (0.000:0.010:0.000))
(INTERCONNECT my_xor0.out buffer1.in (0.000:0.010:0.000) (0.000:0.010:0.000))
(INTERCONNECT my_xor1.out my_xor2.a (0.000:0.010:0.000) (0.000:0.010:0.000))
(INTERCONNECT buffer1.out my_xor2.b (0.000:0.010:0.000) (0.000:0.010:0.000))
(INTERCONNECT c buffer2.in (0.000:0.010:0.000) (0.000:0.010:0.000))
(INTERCONNECT my_xor2.out my_xor3.a (0.000:0.010:0.000) (0.000:0.010:0.000))
(INTERCONNECT buffer2.out my_xor3.b (0.000:0.010:0.000) (0.000:0.010:0.000))
(INTERCONNECT my_xor3.out buffer3.in (0.000:0.010:0.000) (0.000:0.010:0.000))
(INTERCONNECT buffer3.out d (0.000:0.010:0.000) (0.000:0.010:0.000))
)
)
)
(CELL
(CELLTYPE "buffer")
(INSTANCE buffer0)
(DELAY
(ABSOLUTE
(IOPATH in out (0.1:0.2:0.3) (0.1:0.2:0.3))
)
)
)
(CELL
(CELLTYPE "buffer")
(INSTANCE buffer1)
(DELAY
(ABSOLUTE
(IOPATH in out (0.1:0.2:0.3) (0.1:0.2:0.3))
)
)
)
(CELL
(CELLTYPE "buffer")
(INSTANCE buffer2)
(DELAY
(ABSOLUTE
(IOPATH in out (0.1:0.2:0.3) (0.1:0.2:0.3))
)
)
)
(CELL
(CELLTYPE "buffer")
(INSTANCE buffer3)
(DELAY
(ABSOLUTE
(IOPATH in out (0.1:0.2:0.3) (0.1:0.2:0.3))
)
)
)
)

143
ivtest/ivltests/sdf_interconnect3.v Normal file
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`timescale 1ns/1ps
/*
This design tests the interconnection delays
for a circuit of various buffers and xors
*/
module my_xor (
input a,
input b,
output out
);
specify
(a => out) = (0.0:0.0:0.0);
(b => out) = (0.0:0.0:0.0);
endspecify
assign out = a ^ b;
endmodule
module buffer (
input in,
output out
);
specify
(in => out) = (0.0:0.0:0.0);
endspecify
assign out = in;
endmodule
module my_design (
input a,
input b,
input c,
output d
);
wire w1, w2, w3, w4, w5, w6, w7;
buffer buffer0 (
.in (a),
.out (w1)
);
my_xor my_xor0 (
.a (b),
.b (c),
.out (w2)
);
my_xor my_xor1 (
.a (w1),
.b (b),
.out (w3)
);
buffer buffer1 (
.in (w2),
.out (w4)
);
my_xor my_xor2 (
.a (w3),
.b (w4),
.out (w5)
);
buffer buffer2 (
.in (c),
.out (w6)
);
my_xor my_xor3 (
.a (w5),
.b (w6),
.out (w7)
);
buffer buffer3 (
.in (w7),
.out (d)
);
endmodule
module top;
initial begin
$sdf_annotate("ivltests/sdf_interconnect3.sdf", my_design_inst);
$monitor("time=%0t a=%h b=%h c=%h d=%h", $realtime, a, b, c, d);
end
reg a, b, c;
wire d;
initial begin
#10;
a <= 1'b0;
b <= 1'b0;
c <= 1'b0;
#10;
a <= 1'b1;
b <= 1'b0;
c <= 1'b0;
#10;
a <= 1'b0;
b <= 1'b1;
c <= 1'b0;
#10;
a <= 1'b1;
b <= 1'b1;
c <= 1'b0;
#10;
a <= 1'b0;
b <= 1'b0;
c <= 1'b1;
#10;
a <= 1'b1;
b <= 1'b0;
c <= 1'b1;
#10;
a <= 1'b0;
b <= 1'b1;
c <= 1'b1;
#10;
a <= 1'b1;
b <= 1'b1;
c <= 1'b1;
#10;
$finish;
end
my_design my_design_inst (
.a (a),
.b (b),
.c (c),
.d (d)
);
endmodule

3
ivtest/regress-vvp.list
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@ -94,3 +94,6 @@ task_return_fail1 vvp_tests/task_return_fail1.json
task_return_fail2 vvp_tests/task_return_fail2.json
timing_check_syntax vvp_tests/timing_check_syntax.json
timing_check_delayed_signals vvp_tests/timing_check_delayed_signals.json
sdf_interconnect1 vvp_tests/sdf_interconnect1.json
sdf_interconnect2 vvp_tests/sdf_interconnect2.json
sdf_interconnect3 vvp_tests/sdf_interconnect3.json

6
ivtest/vvp_tests/sdf_interconnect1.json Normal file
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{
"type" : "normal",
"source" : "sdf_interconnect1.v",
"iverilog-args" : [ "-Ttyp", "-ginterconnect" ],
"gold" : "sdf_interconnect1"
}

6
ivtest/vvp_tests/sdf_interconnect2.json Normal file
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{
"type" : "normal",
"source" : "sdf_interconnect2.v",
"iverilog-args" : [ "-Ttyp", "-ginterconnect" ],
"gold" : "sdf_interconnect2"
}

6
ivtest/vvp_tests/sdf_interconnect3.json Normal file
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{
"type" : "normal",
"source" : "sdf_interconnect3.v",
"iverilog-args" : [ "-Ttyp", "-ginterconnect" ],
"gold" : "sdf_interconnect3"
}