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Add regression test for explicit cast to packed array and packed struct 

These test verify that explicit cast to packed array and packed struct
types are supported and executed correctly.

The tests are based on the test for integer casts. Just the type of the
variables was changed to packed array and packed struct respectively.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2022-01-17 09:47:54 +01:00
parent 1858c6a313
commit 5fc1976496
4 changed files with 91 additions and 0 deletions
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43
ivtest/ivltests/sv_cast_packed_array.v Normal file
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@ -0,0 +1,43 @@
// This tests SystemVerilog casting support
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
// Extended by Maciej Suminski
// Copied and modified by Martin Whitaker
// Copied and modified again by Lars-Peter Clausen
module test();
typedef logic [7:0] pa08;
typedef pa08 [1:0] pa16;
typedef pa16 [1:0] pa32;
typedef pa32 [1:0] pa64;
// variables used in casting
pa08 var_08;
pa16 var_16;
pa32 var_32;
pa64 var_64;
real var_real;
// error counter
bit err = 0;
initial begin
var_08 = pa08'(4'h5); if (var_08 !== 8'h05) begin $display("FAILED -- var_08 = 'h%0h != 8'h05", var_08); err=1; end
var_16 = pa16'(var_08); if (var_16 !== 16'h05) begin $display("FAILED -- var_16 = 'h%0h != 16'h05", var_16); err=1; end
var_32 = pa32'(var_16); if (var_32 !== 32'h05) begin $display("FAILED -- var_32 = 'h%0h != 32'h05", var_32); err=1; end
var_64 = pa64'(var_32); if (var_64 !== 64'h05) begin $display("FAILED -- var_64 = 'h%0h != 64'h05", var_64); err=1; end
var_real = 13.4; var_08 = pa08'(var_real); if (var_08 !== 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end
var_real = 14.5; var_16 = pa16'(var_real); if (var_16 !== 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end
var_real = 15.6; var_32 = pa32'(var_real); if (var_32 !== 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end
var_real = -15.6; var_64 = pa64'(var_real); if (var_64 !== -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end
var_08 = pa08'(4'hf); if (var_08 !== 8'h0f) begin $display("FAILED -- var_08 = 'h%0h != 8'h0f", var_08); err=1; end
var_16 = pa08'(16'h0f0f); if (var_16 !== 16'h0f) begin $display("FAILED -- var_16 = 'h%0h != 16'h0f", var_16); err=1; end
if (!err) $display("PASSED");
end
endmodule // test

45
ivtest/ivltests/sv_cast_packed_struct.v Normal file
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@ -0,0 +1,45 @@
// This tests SystemVerilog casting support
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
// Extended by Maciej Suminski
// Copied and modified by Martin Whitaker
// Copied and modified again by Lars-Peter Clausen
module test();
typedef struct packed signed { logic [7:0] x; } s08;
typedef struct packed signed { logic [15:0] x; } s16;
typedef struct packed signed { int x; } s32;
typedef struct packed signed { int x; shortint y; byte z; logic [7:0] w; } s64;
// variables used in casting
s08 var_08;
s16 var_16;
s32 var_32;
s64 var_64;
real var_real;
// error counter
bit err = 0;
initial begin
var_08 = s08'(4'sh5); if (var_08 !== 8'sh05) begin $display("FAILED -- var_08 = 'h%0h != 8'h05", var_08); err=1; end
var_16 = s16'(var_08); if (var_16 !== 16'sh05) begin $display("FAILED -- var_16 = 'h%0h != 16'h05", var_16); err=1; end
var_32 = s32'(var_16); if (var_32 !== 32'sh05) begin $display("FAILED -- var_32 = 'h%0h != 32'h05", var_32); err=1; end
var_64 = s64'(var_32); if (var_64 !== 64'sh05) begin $display("FAILED -- var_64 = 'h%0h != 64'h05", var_64); err=1; end
var_real = 13.4; var_08 = s08'(var_real); if (var_08 !== 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end
var_real = 14.5; var_16 = s16'(var_real); if (var_16 !== 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end
var_real = 15.6; var_32 = s32'(var_real); if (var_32 !== 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end
var_real = -15.6; var_64 = s64'(var_real); if (var_64 !== -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end
var_08 = s08'(4'hf); if (var_08 !== 8'sh0f) begin $display("FAILED -- var_08 = 'h%0h != 8'h0f", var_08); err=1; end
var_08 = s08'(4'shf); if (var_08 !== 8'shff) begin $display("FAILED -- var_08 = 'h%0h != 8'hff", var_08); err=1; end
var_16 = s08'(16'h0f0f); if (var_16 !== 16'sh0f) begin $display("FAILED -- var_16 = 'h%0h != 16'h0f", var_16); err=1; end
var_16 = s08'(4'shf) + 'd0; if (var_16 !== 16'shff) begin $display("FAILED -- var_16 = 'h%0h != 16'hff", var_16); err=1; end
if (!err) $display("PASSED");
end
endmodule // test

2
ivtest/regress-sv.list
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@ -390,6 +390,8 @@ sv-constants normal,-g2005-sv ivltests
sv_array_assign_pattern2 normal,-g2009 ivltests
sv_cast_integer normal,-g2005-sv ivltests
sv_cast_integer2 normal,-g2005-sv ivltests
sv_cast_packed_array normal,-g2005-sv ivltests
sv_cast_packed_struct normal,-g2005-sv ivltests
sv_cast_string normal,-g2005-sv ivltests
sv_class1 normal,-g2009 ivltests
sv_class2 normal,-g2009 ivltests

1
ivtest/regress-vlog95.list
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@ -118,6 +118,7 @@ cast_real_signed CE,-pallowsigned=1 ivltests
cast_real_unsigned CE ivltests
sv_cast_integer normal,-g2005-sv,-pallowsigned=1 ivltests
sv_cast_integer2 normal,-g2005-sv,-pallowsigned=1 ivltests
sv_cast_packed_struct normal,-g2005-sv,-pallowsigned=1 ivltests
sv_cast_string CE ivltests
clog2 CE ivltests # Also big int
delayed_sfunc CE ivltests