Reorganize architecture debug methods.

vhdlpp/Makefile.in

@@ -62,8 +62,9 @@ M = StringHeap.o LineInfo.o
 O = main.o architec.o architec_elaborate.o compiler.o entity.o entity_elaborate.o \
     expression.o package.o scope.o sequential.o vsignal.o vtype.o vtype_elaborate.o \
     lexor.o lexor_keyword.o parse.o \
-    parse_misc.o library.o vhdlreal.o vhdlint.o debug.o \
+    parse_misc.o library.o vhdlreal.o vhdlint.o \
     architec_emit.o entity_emit.o expression_emit.o vtype_emit.o \
+    debug.o architec_debug.o \
     $M
 
 all: dep vhdlpp@EXEEXT@

vhdlpp/architec.h

@@ -128,6 +128,9 @@ class ProcessStatement : public Architecture::Statement {
       ProcessStatement(perm_string iname);
       ~ProcessStatement();
 
+      virtual int elaborate(Entity*ent, Architecture*arc);
+      virtual void dump(ostream&out, int indent =0) const;
+
     private:
       perm_string iname_;
 

vhdlpp/architec_debug.cc

@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2011 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+# include  "architec.h"
+# include  "expression.h"
+# include  <fstream>
+# include  <iomanip>
+# include  <typeinfo>
+
+void Architecture::dump(ostream&out, perm_string of_entity, int indent) const
+{
+      out << setw(indent) << "" << "architecture " << name_
+	  << " of entity " << of_entity
+	  << " file=" << get_fileline() << endl;
+
+      dump_scope(out);
+
+      for (list<Architecture::Statement*>::const_iterator cur = statements_.begin()
+		 ; cur != statements_.end() ; ++cur) {
+	    (*cur)->dump(out, indent+3);
+      }
+}
+
+void Architecture::Statement::dump(ostream&out, int indent) const
+{
+      out << setw(indent) << "" << "Architecture::Statement at file=" << get_fileline() << endl;
+}
+
+void ComponentInstantiation::dump(ostream&out, int indent) const
+{
+      out << setw(indent) << "" << "Component Instantiation file=" << get_fileline() << endl;
+
+      for (map<perm_string,Expression*>::const_iterator cur = port_map_.begin()
+		 ; cur != port_map_.end() ; ++cur) {
+	    out << setw(indent+2) <<""<< cur->first << " => ..." << endl;
+	    cur->second->dump(out, indent+6);
+      }
+
+}
+
+void SignalAssignment::dump(ostream&out, int indent) const
+{
+      out << setw(indent) << "" << "SignalAssignment file=" << get_fileline() << endl;
+      lval_->dump(out, indent+1);
+      out << setw(indent+2) << "" << "<= <expr>..." << endl;
+
+      for (list<Expression*>::const_iterator cur = rval_.begin()
+		 ; cur != rval_.end() ; ++cur) {
+	    (*cur)->dump(out, indent+2);
+      }
+}
+
+void ProcessStatement::dump(ostream&out, int indent) const
+{
+      out << setw(indent) << "" << "ProcessStatement name_=" << iname_
+	  << " file=" << get_fileline() << endl;
+}

vhdlpp/architec_elaborate.cc

@@ -68,3 +68,8 @@ int ComponentInstantiation::elaborate(Entity*ent, Architecture*arc)
 
       return errors;
 }
+
+int ProcessStatement::elaborate(Entity*ent, Architecture*arc)
+{
+      return 0;
+}

vhdlpp/debug.cc

@@ -122,25 +122,6 @@ void Entity::dump(ostream&out, int indent) const
       }
 }
 
-void Architecture::dump(ostream&out, perm_string of_entity, int indent) const
-{
-      out << setw(indent) << "" << "architecture " << name_
-	  << " of entity " << of_entity
-	  << " file=" << get_fileline() << endl;
-
-      dump_scope(out);
-
-      for (list<Architecture::Statement*>::const_iterator cur = statements_.begin()
-		 ; cur != statements_.end() ; ++cur) {
-	    (*cur)->dump(out, indent+3);
-      }
-}
-
-void Architecture::Statement::dump(ostream&out, int indent) const
-{
-      out << setw(indent) << "" << "Architecture::Statement at file=" << get_fileline() << endl;
-}
-
 void Signal::dump(ostream&out, int indent) const
 {
       out << setw(indent) << "" << "signal " << name_ << " is ";
@@ -151,30 +132,6 @@ void Signal::dump(ostream&out, int indent) const
       out << endl;
 }
 
-void SignalAssignment::dump(ostream&out, int indent) const
-{
-      out << setw(indent) << "" << "SignalAssignment file=" << get_fileline() << endl;
-      lval_->dump(out, indent+1);
-      out << setw(indent+2) << "" << "<= <expr>..." << endl;
-
-      for (list<Expression*>::const_iterator cur = rval_.begin()
-		 ; cur != rval_.end() ; ++cur) {
-	    (*cur)->dump(out, indent+2);
-      }
-}
-
-void ComponentInstantiation::dump(ostream&out, int indent) const
-{
-      out << setw(indent) << "" << "Component Instantiation file=" << get_fileline() << endl;
-
-      for (map<perm_string,Expression*>::const_iterator cur = port_map_.begin()
-		 ; cur != port_map_.end() ; ++cur) {
-	    out << setw(indent+2) <<""<< cur->first << " => ..." << endl;
-	    cur->second->dump(out, indent+6);
-      }
-
-}
-
 void Expression::dump(ostream&out, int indent) const
 {
       out << setw(indent) << "" << "Expression [" << typeid(*this).name() << "]"