vhdlpp: Stricter array type matching

Arrays type match if they have a common parent, instead of the
element type. Now (un)signed & std_logic_vector types do not match,
as it should be in VHDL.

vhdlpp/vtype.h

@@ -253,6 +253,8 @@ class VTypeArray : public VType {
 	// To handle subtypes
       inline void set_parent_type(const VTypeArray*parent) { parent_ = parent; }
 
+      const VTypeArray*get_parent_type() const { return parent_; }
+
 	// Wherever it is possible, replaces range lsb & msb expressions with
 	// constant integers.
       void evaluate_ranges(ScopeBase*scope);

vhdlpp/vtype_match.cc

@@ -70,7 +70,15 @@ bool VTypeArray::type_match(const VType*that) const
 
       // Check if both arrays are of the same size
       if(const VTypeArray*arr = dynamic_cast<const VTypeArray*>(that)) {
-          if(!element_type()->type_match(arr->element_type()))
+          const VTypeArray*this_parent = this;
+          while(const VTypeArray*tmp = this_parent->get_parent_type())
+              this_parent = tmp;
+
+          const VTypeArray*that_parent = arr;
+          while(const VTypeArray*tmp = that_parent->get_parent_type())
+              that_parent = tmp;
+
+          if(this_parent != that_parent)
               return false;
 
           int this_width = get_width(NULL);