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Catch case where component name and instance differ only in case 

This causes an error in VHDL (which is case-insensitive). This 
patch simply appends _Inst to the instance name if it detects this.
This commit is contained in:
Nick Gasson 2008-08-22 20:20:17 +01:00
parent fae7ab2418
commit 63a1e25129
1 changed files with 3 additions and 2 deletions
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5
tgt-vhdl/scope.cc
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@ -752,14 +752,15 @@ static int draw_hierarchy(ivl_scope_t scope, void *_parent)
assert(parent_arch != NULL);
// Create a forward declaration for it
if (!parent_arch->get_scope()->have_declared(ent->get_name())) {
vhdl_scope *parent_scope = parent_arch->get_scope();
if (!parent_scope->have_declared(ent->get_name())) {
vhdl_decl *comp_decl = vhdl_component_decl::component_decl_for(ent);
parent_arch->get_scope()->add_decl(comp_decl);
}
// And an instantiation statement
string inst_name(ivl_scope_basename(scope));
if (inst_name == ent->get_name()) {
if (inst_name == ent->get_name() || parent_scope->have_declared(inst_name)) {
// Cannot have instance name the same as type in VHDL
inst_name += "_Inst";
}