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Netlist boolean expressions generate gate vectors.

This commit is contained in:
steve 2005-01-29 18:46:18 +00:00
parent 0609c5f18c
commit 609b6a7baa
3 changed files with 64 additions and 26 deletions
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46
elab_net.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: elab_net.cc,v 1.147 2005/01/29 16:46:22 steve Exp $"
#ident "$Id: elab_net.cc,v 1.148 2005/01/29 18:46:18 steve Exp $"
#endif
# include "config.h"
@ -276,23 +276,23 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, NetScope*scope,
return 0;
}
if (lsig->pin_count() < rsig->pin_count())
lsig = pad_to_width(des, lsig, rsig->pin_count());
if (rsig->pin_count() < lsig->pin_count())
rsig = pad_to_width(des, rsig, lsig->pin_count());
if (lsig->vector_width() < rsig->vector_width())
lsig = pad_to_width(des, lsig, rsig->vector_width());
if (rsig->vector_width() < lsig->vector_width())
rsig = pad_to_width(des, rsig, lsig->vector_width());
if (lsig->pin_count() != rsig->pin_count()) {
cerr << get_line() << ": internal error: lsig pin count ("
<< lsig->pin_count() << ") != rsig pin count ("
<< rsig->pin_count() << ")." << endl;
if (lsig->vector_width() != rsig->vector_width()) {
cerr << get_line() << ": internal error: lsig width ("
<< lsig->vector_width() << ") != rsig pin width ("
<< rsig->vector_width() << ")." << endl;
des->errors += 1;
return 0;
}
assert(lsig->pin_count() == rsig->pin_count());
assert(lsig->vector_width() == rsig->vector_width());
NetNet*osig = new NetNet(scope, scope->local_symbol(), NetNet::WIRE,
lsig->pin_count());
lsig->vector_width());
osig->local_flag(true);
NetLogic::TYPE gtype=NetLogic::AND;
@ -306,17 +306,16 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, NetScope*scope,
default: assert(0);
}
for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) {
NetLogic*gate = new NetLogic(scope, scope->local_symbol(),
3, gtype, 1);
connect(gate->pin(1), lsig->pin(idx));
connect(gate->pin(2), rsig->pin(idx));
connect(gate->pin(0), osig->pin(idx));
gate->rise_time(rise);
gate->fall_time(fall);
gate->decay_time(decay);
des->add_node(gate);
}
NetLogic*gate = new NetLogic(scope, scope->local_symbol(),
3, gtype, osig->vector_width());
gate->set_line(*this);
connect(gate->pin(0), osig->pin(0));
connect(gate->pin(1), lsig->pin(0));
connect(gate->pin(2), rsig->pin(0));
gate->rise_time(rise);
gate->fall_time(fall);
gate->decay_time(decay);
des->add_node(gate);
return osig;
}
@ -2452,6 +2451,9 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
/*
* $Log: elab_net.cc,v $
* Revision 1.148 2005/01/29 18:46:18 steve
* Netlist boolean expressions generate gate vectors.
*
* Revision 1.147 2005/01/29 16:46:22 steve
* Elaborate parameter reference to desired width without concats.
*

11
ivl_target.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: ivl_target.h,v 1.136 2005/01/29 16:47:20 steve Exp $"
#ident "$Id: ivl_target.h,v 1.137 2005/01/29 18:46:18 steve Exp $"
#endif
#ifdef __cplusplus
@ -644,6 +644,12 @@ extern ivl_memory_t ivl_expr_memory(ivl_expr_t net);
* ivl_logic_attr_val returns the value of the attribute.
*
* SEMANTIC NOTES
* The ivl_logic_width applies to all the pins of a logic device. If a
* logic device has width, that means that it is actually an array of
* logic devices tha each process a bit slice of the
* inputs/output. That implies that the widths of all the inputs and
* the output must be identical.
*
* The ivl_logic_width and ivl_logic_pins are *not* related. A logic
* device has a number of pins that is the number of inputs to a logic
* array of identical gates, and the ivl_logic_width, is the width of
@ -1464,6 +1470,9 @@ _END_DECL
/*
* $Log: ivl_target.h,v $
* Revision 1.137 2005/01/29 18:46:18 steve
* Netlist boolean expressions generate gate vectors.
*
* Revision 1.136 2005/01/29 16:47:20 steve
* Clarify width of nexus.
*

33
tgt-stub/stub.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: stub.c,v 1.103 2005/01/29 16:47:52 steve Exp $"
#ident "$Id: stub.c,v 1.104 2005/01/29 18:46:18 steve Exp $"
#endif
# include "config.h"
@ -794,6 +794,11 @@ static void show_signal(ivl_signal_t net)
}
/*
* All logic gates have inputs and outputs that match exactly in
* width. For example, and AND gate with 4 bit inputs generates a 4
* bit output, and all the inputs are 4 bits.
*/
static void show_logic(ivl_net_logic_t net)
{
unsigned npins, idx;
@ -852,14 +857,33 @@ static void show_logic(ivl_net_logic_t net)
for (idx = 1 ; idx < npins ; idx += 1) {
ivl_nexus_t nex = ivl_logic_pin(net,idx);
if (nex == 0)
if (nex == 0) {
fprintf(out, ", <HiZ>");
else
} else {
fprintf(out, ", %s", ivl_nexus_name(nex));
if (ivl_logic_width(net) != width_of_nexus(nex)) {
fprintf(stderr,
"ERROR: Logic pin %u width mismatch.",
idx);
fprintf(stderr,
" Expect width=%u, nexus width=%u\n",
ivl_logic_width(net), width_of_nexus(nex));
stub_errors += 1;
}
}
}
fprintf(out, "); <width=%u>\n", ivl_logic_width(net));
if (ivl_logic_width(net) != width_of_nexus(ivl_logic_pin(net,0))) {
fprintf(stderr, "ERROR: Logic output pin width mismatch.");
fprintf(stderr, " Expect width=%u, nexus width=%u\n",
ivl_logic_width(net),
width_of_nexus(ivl_logic_pin(net,0)));
stub_errors += 1;
}
npins = ivl_logic_attr_cnt(net);
for (idx = 0 ; idx < npins ; idx += 1) {
ivl_attribute_t cur = ivl_logic_attr_val(net,idx);
@ -974,6 +998,9 @@ int target_design(ivl_design_t des)
/*
* $Log: stub.c,v $
* Revision 1.104 2005/01/29 18:46:18 steve
* Netlist boolean expressions generate gate vectors.
*
* Revision 1.103 2005/01/29 16:47:52 steve
* Check width of constant attached to nexus.
*