ivtest: pr1002: Avoid race condition
The pr1002 test has a always block with the `dataout` in its sensitivity list. It compares `dataout` to `expected_dataout`. Both `dataout` and `expected_dataout` depend on `datain` and are updated in the same cycle. This means there is no guarantee in which order they are updated and the always block might get scheduled before `expected_dataout` has been updated. This can lead to a test failure. To avoid this slightly change the test to use a task to perform the comparison and add an explicit delay before the task is executed so that all updates have a chance to be fully resolved Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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@ -8,29 +8,11 @@ assign dataout = datain >>> 2;
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reg test_failed;
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initial
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begin
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test_failed = 0;
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#1 datain = 14'h0FFF;
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#1 datain = 14'h0000;
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#1 datain = 14'h1FFF;
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#1 datain = 14'h1000;
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#1 datain = 14'h2FFF;
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#1 datain = 14'h2000;
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#1 datain = 14'h3FFF;
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#1 datain = 14'h3000;
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#2;
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if (test_failed)
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$display("TEST FAILED :-(");
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else
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$display("TEST PASSED :-)");
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end
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wire signed [15:0] expected_dataout;
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assign expected_dataout = ($signed({datain[13:2], 2'b0}) / 4) ;
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always @(dataout)
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task check_data;
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if (expected_dataout != dataout)
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begin
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$display("datain = %d dataout = %h expected = %h ... CHECK FAILED", datain, dataout, expected_dataout);
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@ -38,5 +20,32 @@ always @(dataout)
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end
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else
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$display("datain = %d dataout = %d expected = %d ... CHECK PASSED", datain, dataout, expected_dataout);
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endtask
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initial
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begin
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test_failed = 0;
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#1 datain = 14'h0FFF;
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#0 check_data; // #0 delay to allow the wire to resolve
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#1 datain = 14'h0000;
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#0 check_data;
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#1 datain = 14'h1FFF;
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#0 check_data;
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#1 datain = 14'h1000;
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#0 check_data;
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#1 datain = 14'h2FFF;
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#0 check_data;
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#1 datain = 14'h2000;
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#0 check_data;
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#1 datain = 14'h3FFF;
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#0 check_data;
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#1 datain = 14'h3000;
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#0 check_data;
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#2;
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if (test_failed)
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$display("TEST FAILED :-(");
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else
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$display("TEST PASSED :-)");
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end
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endmodule // top
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