Handle empty class item declarations in parser

The SystemVerilog grammar explicitly allows an empty class item
declaration. The empty class item declaration is just a semicolon and has
no effect.

E.g. the following is legal
```
class C
  int x;;;
endclass
```

Add support to the parser to accept empty class item declarations.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

parse.y

@@ -979,6 +979,9 @@ class_item /* IEEE1800-2005: A.1.8 */
 
   | parameter_declaration
 
+    /* Empty class item */
+  | ';'
+
   | error ';'
       { yyerror(@2, "error: invalid class item.");
 	yyerrok;