Save the type name if an InterfacePort object.
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parent
5a6d07ff9f
commit
d72f7ea249
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@ -56,7 +56,8 @@ static void dump_design_entity(ostream&out, Entity*obj)
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; cur != obj->ports.end() ; ++cur) {
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InterfacePort*item = *cur;
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out << setw(6) << "" << item->name
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<< " : " << item->mode << endl;
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<< " : " << item->mode
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<< ", type=" << item->type_name << endl;
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}
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}
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}
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@ -27,8 +27,12 @@ typedef enum { PORT_NONE=0, PORT_IN, PORT_OUT } port_mode_t;
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class InterfacePort {
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public:
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// Port direction from the source code.
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port_mode_t mode;
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// Name of the port from the source code
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perm_string name;
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// Name of interface type as given in the source code.
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perm_string type_name;
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};
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class Entity {
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@ -54,6 +54,16 @@ int Entity::elaborate()
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; cur != ports.end() ; ++cur) {
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InterfacePort*port = *cur;
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// FIXME: this is a stub. This port handling code
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// currently only supports std_logic signal tyes,
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// so just assert that the user asked for std_logic.
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if (port->type_name != "std_logic") {
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cerr << "sorry: VHDL only supports std_logic ports."
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<< " Expecting std_logic, but got \""
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<< port->type_name << "\"" << endl;
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errors += 1;
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}
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if (sep) cout << sep;
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else sep = ", ";
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@ -172,6 +172,7 @@ interface_element
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{ InterfacePort*tmp = new InterfacePort;
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tmp->mode = $3;
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tmp->name = lex_strings.make($1);
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tmp->type_name = lex_strings.make($4);
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delete[]$1;
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delete[]$4;
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$$ = tmp;
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@ -180,7 +181,7 @@ interface_element
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interface_list
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: interface_list ';' interface_element
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{ std:list<InterfacePort*>*tmp = $1;
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{ std::list<InterfacePort*>*tmp = $1;
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tmp->push_back($3);
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$$ = tmp;
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}
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