Fix synthesis of signal and part select to keep signed/unsigned type.
If a signal has been cast to a different type, synthesis needs to reflect the expression type, not the base signal type. If a part select selects the entire signal, unless otherwise cast, the expression is unsigned, regardless of the base signal type. This fixes the additional issues reported in issue #1099.
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@ -1259,8 +1259,21 @@ NetNet* NetESelect::synthesize(Design *des, NetScope*scope, NetExpr*root)
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// padding.) If this was for an actual part select that at
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// this point the output vector_width is exactly right, and we
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// are done.
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if (sub->vector_width() == expr_width())
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return sub;
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if (sub->vector_width() == expr_width()) {
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if (sub->get_signed() == has_sign())
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return sub;
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// If the signal and expression type don't match, we
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// need to add an intermediate signal to reflect that.
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auto tmp_vec = new netvector_t(sub->data_type(), sub->vector_width() - 1, 0);
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NetNet*tmp = new NetNet(scope, scope->local_symbol(), NetNet::IMPLICIT,
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tmp_vec);
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tmp->set_line(*this);
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tmp->local_flag(true);
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connect(sub->pin(0), tmp->pin(0));
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return tmp;
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}
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netvector_t*net_vec = new netvector_t(expr_type(), expr_width()-1, 0);
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net_vec->set_signed(has_sign());
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@ -1423,8 +1436,21 @@ NetNet* NetESignal::synthesize(Design*des, NetScope*scope, NetExpr*root)
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return tmp;
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}
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if (word_ == 0)
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return net_;
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if (word_ == 0) {
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if (net_->get_signed() == has_sign())
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return net_;
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// If the signal has been cast to a different type, we
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// need to add an intermediate signal to reflect that.
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auto tmp_vec = new netvector_t(net_->data_type(), net_->vector_width() - 1, 0);
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NetNet*tmp = new NetNet(scope, scope->local_symbol(), NetNet::IMPLICIT,
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tmp_vec);
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tmp->set_line(*this);
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tmp->local_flag(true);
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connect(net_->pin(0), tmp->pin(0));
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return tmp;
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}
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netvector_t*tmp_vec = new netvector_t(net_->data_type(),
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net_->vector_width()-1, 0);
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