VHDL: Add initial support for non-constant casex/z label expressions.
This patch adds support for concatenation/repetition, signals and part and bit select of signals for casez/x expression labels. These along with the original constants can be mixed in almost any order. Only constant selects are currently supported.
This commit is contained in:
Cary R
Stephen Williams
parent
8cd50c163b
commit
eea7693539
341
tgt-vhdl/stmt.cc
341
tgt-vhdl/stmt.cc
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@ -25,6 +25,7 @@
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#include <cassert>
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#include <sstream>
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#include <typeinfo>
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#include <limits>
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/*
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* VHDL has no real equivalent of Verilog's $finish task. The
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@ -656,9 +657,294 @@ static int draw_case(vhdl_procedural *proc, stmt_container *container,
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}
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/*
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* A casex statement cannot be directly translated to a VHDL case
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* Check to see if the given number (expression) can be represented
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* accurately in a long value.
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*/
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static bool number_is_long(ivl_expr_t expr)
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{
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ivl_expr_type_t type = ivl_expr_type(expr);
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assert(type == IVL_EX_NUMBER || type == IVL_EX_ULONG);
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// Make sure the ULONG can be represented correctly in a long.
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if (type == IVL_EX_ULONG) {
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unsigned long val = ivl_expr_uvalue(expr);
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if (val > numeric_limits<long>::max()) return false;
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return true;
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}
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// Check to see if the number actually fits in a long.
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unsigned nbits = ivl_expr_width(expr);
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if (nbits >= 8*sizeof(long)) {
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const char*bits = ivl_expr_bits(expr);
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char pad_bit = bits[nbits-1];
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for (unsigned idx = 8*sizeof(long); idx < nbits; idx++) {
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if (bits[idx] != pad_bit) return false;
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}
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}
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return true;
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}
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/*
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* Return the given number (expression) as a signed long value.
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*
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* Make sure to call number_is_long() first to verify that the number
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* can be represented accurately in a long value.
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*/
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static long get_number_as_long(ivl_expr_t expr)
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{
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long imm = 0;
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switch (ivl_expr_type(expr)) {
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case IVL_EX_ULONG:
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imm = ivl_expr_uvalue(expr);
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break;
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case IVL_EX_NUMBER: {
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const char*bits = ivl_expr_bits(expr);
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unsigned nbits = ivl_expr_width(expr);
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if (nbits > 8*sizeof(long)) nbits = 8*sizeof(long);
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for (unsigned idx = 0; idx < nbits; idx++) {
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switch (bits[idx]) {
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case '0':
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break;
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case '1':
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imm |= 1L << idx;
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break;
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default:
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assert(0);
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}
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if (ivl_expr_signed(expr) && bits[nbits-1] == '1' &&
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nbits < 8*sizeof(long)) imm |= -1L << nbits;
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}
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break;
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}
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default:
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assert(0);
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}
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return imm;
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}
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/*
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* Build a check against a constant 'x'. This is for an out of range
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* or undefined select.
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*/
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static void check_against_x(vhdl_binop_expr *all, vhdl_var_ref *test,
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ivl_expr_t expr, unsigned width, unsigned base,
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bool is_casez)
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{
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if (is_casez) {
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// For a casez we need to check the 'x'.
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for (unsigned i = 0; i < ivl_expr_width(expr); i++) {
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// Get the current test bit.
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vhdl_type *type = vhdl_type::nunsigned(width);
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vhdl_var_ref *ref = new vhdl_var_ref(test->get_name().c_str(), type);
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ref->set_slice(new vhdl_const_int(i+base));
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// Compare the bit against 'x'.
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vhdl_binop_expr *cmp =
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new vhdl_binop_expr(VHDL_BINOP_EQ, vhdl_type::boolean());
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cmp->add_expr(ref);
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cmp->add_expr(new vhdl_const_bit('x'));
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all->add_expr(cmp);
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}
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} else {
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// For a casex 'x' is a don't care, so just put 'true'.
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all->add_expr(new vhdl_const_bool(true));
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}
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}
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/*
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* Build the test signal to constant bits check.
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*/
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static void process_number(vhdl_binop_expr *all, vhdl_var_ref *test,
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ivl_expr_t expr, unsigned width, unsigned base,
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bool is_casez)
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{
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const char *bits = ivl_expr_bits(expr);
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bool just_dont_care = true;
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for (unsigned i = 0; i < ivl_expr_width(expr); i++) {
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switch (bits[i]) {
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case 'x':
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if (is_casez) break;
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case '?':
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case 'z':
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continue; // Ignore these.
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}
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// Get the current test bit.
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vhdl_type *type = vhdl_type::nunsigned(width);
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vhdl_var_ref *ref = new vhdl_var_ref(test->get_name().c_str(), type);
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ref->set_slice(new vhdl_const_int(i+base));
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// Compare the bit against the value.
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vhdl_binop_expr *cmp =
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new vhdl_binop_expr(VHDL_BINOP_EQ, vhdl_type::boolean());
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cmp->add_expr(ref);
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cmp->add_expr(new vhdl_const_bit(bits[i]));
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all->add_expr(cmp);
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just_dont_care = false;
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}
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// If there are no bits comparisons then just put a True
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if (just_dont_care) {
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all->add_expr(new vhdl_const_bool(true));
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}
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}
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/*
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* Build the test signal to label signal check.
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*/
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static bool process_signal(vhdl_binop_expr *all, vhdl_var_ref *test,
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ivl_expr_t expr, unsigned width, unsigned base,
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bool is_casez, unsigned swid, long sbase)
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{
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// If the word or dimensions are not zero then we have an array.
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if (ivl_expr_oper1(expr) != 0 ||
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ivl_signal_dimensions(ivl_expr_signal(expr)) != 0) {
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error("Sorry, array selects are not currently allowed in this "
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"context.");
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return true;
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}
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unsigned ewid = ivl_expr_width(expr);
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for (unsigned i = 0; i < swid; i++) {
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// Generate a comparison for this bit position
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vhdl_binop_expr *cmp;
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vhdl_type *type;
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// Check if this is an out of bounds access. If this is a casez
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// then check against a constant 'x' for the out of bound bits
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// otherwise skip the check (casex).
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if (i + sbase >= ewid || i + sbase < 0) {
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if (is_casez) {
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// Get the current test bit.
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type = vhdl_type::nunsigned(width);
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vhdl_var_ref *ref = new vhdl_var_ref(test->get_name().c_str(),
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type);
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ref->set_slice(new vhdl_const_int(i+base));
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// Compare the bit against 'x'.
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cmp = new vhdl_binop_expr(VHDL_BINOP_EQ, vhdl_type::boolean());
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cmp->add_expr(ref);
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cmp->add_expr(new vhdl_const_bit('x'));
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all->add_expr(cmp);
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continue;
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} else {
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// The compiler replaces a completely out of range select
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// with a constant so we know there will be at least one
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// valid bit here. We don't need a just_font_care test.
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continue;
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}
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}
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vhdl_binop_expr *sub_expr =
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new vhdl_binop_expr(VHDL_BINOP_OR, vhdl_type::boolean());
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// Get the current expression bit.
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type = vhdl_type::nunsigned(ivl_expr_width(expr));
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vhdl_var_ref *bit = new vhdl_var_ref(ivl_expr_name(expr), type);
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bit->set_slice(new vhdl_const_int(i+sbase));
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// Check if the expression bit is 'z'.
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cmp = new vhdl_binop_expr(VHDL_BINOP_EQ, vhdl_type::boolean());
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cmp->add_expr(bit);
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cmp->add_expr(new vhdl_const_bit('z'));
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sub_expr->add_expr(cmp);
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// If this is a casex statement check if the expression bit is 'x'.
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if (!is_casez) {
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cmp = new vhdl_binop_expr(VHDL_BINOP_EQ, vhdl_type::boolean());
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cmp->add_expr(bit);
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cmp->add_expr(new vhdl_const_bit('x'));
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sub_expr->add_expr(cmp);
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}
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// Get the current test bit.
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type = vhdl_type::nunsigned(width);
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vhdl_var_ref *ref = new vhdl_var_ref(test->get_name().c_str(), type);
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ref->set_slice(new vhdl_const_int(i+base));
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// Next check if the test and expression bits are equal.
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cmp = new vhdl_binop_expr(VHDL_BINOP_EQ, vhdl_type::boolean());
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cmp->add_expr(ref);
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cmp->add_expr(bit);
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sub_expr->add_expr(cmp);
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all->add_expr(sub_expr);
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}
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return false;
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}
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/*
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* These are the constructs that we allow in a casex/z label
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* expression. Returns true on failure.
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*/
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static bool process_expr_bits(vhdl_binop_expr *all, vhdl_var_ref *test,
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ivl_expr_t expr, unsigned width, unsigned base,
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bool is_casez)
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{
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assert(ivl_expr_width(expr)+base <= width);
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switch (ivl_expr_type(expr)) {
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case IVL_EX_CONCAT:
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// Loop repeat number of times processing each sub element.
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for (unsigned repeat = 0; repeat < ivl_expr_repeat(expr); repeat++) {
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unsigned nparms = ivl_expr_parms(expr) - 1;
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for (unsigned parm = 0; parm <= nparms; parm++) {
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ivl_expr_t pexpr = ivl_expr_parm(expr, nparms-parm);
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if (process_expr_bits(all, test, pexpr, width, base, is_casez))
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return true;
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base += ivl_expr_width(pexpr);
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}
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}
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break;
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case IVL_EX_NUMBER:
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process_number(all, test, expr, width, base, is_casez);
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break;
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case IVL_EX_SIGNAL:
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if (process_signal(all, test, expr, width, base, is_casez,
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ivl_expr_width(expr), 0)) return true;
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break;
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case IVL_EX_SELECT: {
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ivl_expr_t bexpr = ivl_expr_oper2(expr);
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if (ivl_expr_type(bexpr) != IVL_EX_NUMBER &&
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ivl_expr_type(bexpr) != IVL_EX_ULONG) {
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error("Sorry, only constant bit/part selects are currently allowed "
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"in this context.");
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return true;
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}
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// If the number is out of bounds or an 'x' then check against 'x'.
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if (!number_is_long(bexpr)) {
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check_against_x(all, test, expr, width, base, is_casez);
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} else if (process_signal(all, test, ivl_expr_oper1(expr), width, base,
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is_casez, ivl_expr_width(expr),
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get_number_as_long(bexpr))) return true;
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break;
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}
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default:
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error("Sorry, expression type %d is not currently supported.",
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ivl_expr_type(expr));
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return true;
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break;
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}
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return false;
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}
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/*
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* A casex/z statement cannot be directly translated to a VHDL case
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* statement as VHDL does not treat the don't-care bit as special.
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* The solution here is to generate an if statement from the casex
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* The solution here is to generate an if statement from the casex/z
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* which compares only the non-don't-care bit positions.
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*/
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int draw_casezx(vhdl_procedural *proc, stmt_container *container,
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@ -671,53 +957,22 @@ int draw_casezx(vhdl_procedural *proc, stmt_container *container,
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vhdl_if_stmt *result = NULL;
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int nbranches = ivl_stmt_case_count(stmt);
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bool is_casez = ivl_statement_type(stmt) == IVL_ST_CASEZ;
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for (int i = 0; i < nbranches; i++) {
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stmt_container *where = NULL;
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ivl_expr_t net = ivl_stmt_case_expr(stmt, i);
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if (net) {
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// The net must be a constant value otherwise we can't
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// generate the terms for the comparison expression
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if (ivl_expr_type(net) != IVL_EX_NUMBER) {
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error("Sorry, only casex statements with constant labels can "
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"be translated to VHDL");
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return 1;
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}
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const char *bits = ivl_expr_bits(net);
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vhdl_binop_expr *all =
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new vhdl_binop_expr(VHDL_BINOP_AND, vhdl_type::boolean());
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bool just_dont_care = true;
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for (unsigned i = 0; i < ivl_expr_width(net); i++) {
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switch (bits[i]) {
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case 'x':
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if (ivl_statement_type(stmt) == IVL_ST_CASEZ) break;
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case '?':
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case 'z':
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// Ignore it
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continue;
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}
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// Generate a comparison for this bit position
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vhdl_binop_expr *cmp =
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new vhdl_binop_expr(VHDL_BINOP_EQ, vhdl_type::boolean());
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vhdl_type *type = vhdl_type::nunsigned(ivl_expr_width(net));
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vhdl_var_ref *lhs =
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new vhdl_var_ref(test->get_name().c_str(), type);
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lhs->set_slice(new vhdl_const_int(i));
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cmp->add_expr(lhs);
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cmp->add_expr(new vhdl_const_bit(bits[i]));
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all->add_expr(cmp);
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just_dont_care = false;
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}
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// If there are no bits comparisons then just put a True
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if (just_dont_care) {
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all->add_expr(new vhdl_const_bool(true));
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// The net must be something we can generate a comparison for.
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if (process_expr_bits(all, test, net, ivl_expr_width(net), 0,
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is_casez)) {
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error("%s:%d: Sorry, only case%s statements with simple "
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"expression labels can be translated to VHDL",
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ivl_stmt_file(stmt), ivl_stmt_lineno(stmt),
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(is_casez ? "z" : "x"));
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return 1;
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}
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if (result)
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@ -743,7 +998,7 @@ int draw_casezx(vhdl_procedural *proc, stmt_container *container,
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// as this may not be obvious
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ostringstream ss;
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ss << "Generated from case"
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<< (ivl_statement_type(stmt) == IVL_ST_CASEX ? 'x' : 'z')
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<< (is_casez ? 'z' : 'x')
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<< " statement at " << ivl_stmt_file(stmt) << ":" << ivl_stmt_lineno(stmt);
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result->set_comment(ss.str());
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