Add extra regression tests for multiple drivers on uwires.

ivtest/gold/uwire_fail2-iverilog-stderr.gold

@@ -0,0 +1,3 @@
+ivltests/uwire_fail2.v:8: error: Unresolved wire 'w' cannot have multiple drivers.
+ivltests/uwire_fail2.v:9: error: Unresolved wire 'w' cannot have multiple drivers.
+2 error(s) during elaboration.

ivtest/gold/uwire_fail3-iverilog-stderr.gold

@@ -0,0 +1,3 @@
+ivltests/uwire_fail3.v:9: error: Unresolved wire 'w' cannot have multiple drivers.
+ivltests/uwire_fail3.v:10: error: Unresolved wire 'w' cannot have multiple drivers.
+2 error(s) during elaboration.

ivtest/gold/uwire_fail4-iverilog-stderr.gold

@@ -0,0 +1,3 @@
+ivltests/uwire_fail4.v:9: error: Unresolved wire 'w' cannot have multiple drivers.
+ivltests/uwire_fail4.v:10: error: Unresolved wire 'w' cannot have multiple drivers.
+2 error(s) during elaboration.

ivtest/ivltests/uwire_fail2.v

@@ -0,0 +1,13 @@
+// NOTE: The expected results for this test will depend on the order in
+// which the compiler elaborates the statements.
+module top;
+  uwire [7:0] w;
+
+  assign w[5:2] = 4'd0;
+  assign w[1:0] = 2'd1;
+  assign w[3:2] = 2'd1;
+  assign w[5:4] = 2'd1;
+  assign w[7:6] = 2'd1;
+
+  initial $display("Failed: this should be a compile time error!");
+endmodule

ivtest/ivltests/uwire_fail3.v

@@ -0,0 +1,14 @@
+// NOTE: The expected results for this test will depend on the order in
+// which the compiler elaborates the statements.
+module top;
+  uwire [3:0] w;
+
+  assign w[1] = 1'b0;
+  assign w[2] = 1'b1;
+  assign w[0] = 1'b1;
+  assign w[1] = 1'b1;
+  assign w[2] = 1'b1;
+  assign w[3] = 1'b1;
+
+  initial $display("Failed: this should be a compile time error!");
+endmodule

ivtest/ivltests/uwire_fail4.v

@@ -0,0 +1,14 @@
+// NOTE: The expected results for this test will depend on the order in
+// which the compiler elaborates the statements.
+module top;
+  uwire [3:0] w[3:0];
+
+  assign w[1] = 4'd0;
+  assign w[2] = 4'd1;
+  assign w[0] = 4'd2;
+  assign w[1] = 4'd3;
+  assign w[2] = 4'd4;
+  assign w[3] = 4'd5;
+
+  initial $display("Failed: this should be a compile time error!");
+endmodule

ivtest/regress-vvp.list

@@ -219,6 +219,8 @@ test_va_math			vvp_tests/test_va_math.json
 test_vams_math			vvp_tests/test_vams_math.json
 timing_check_syntax		vvp_tests/timing_check_syntax.json
 timing_check_delayed_signals	vvp_tests/timing_check_delayed_signals.json
+uwire_fail2			vvp_tests/uwire_fail2.json
+uwire_fail3			vvp_tests/uwire_fail3.json
 value_range1			vvp_tests/value_range1.json
 value_range2			vvp_tests/value_range2.json
 value_range3			vvp_tests/value_range3.json

ivtest/vvp_tests/uwire_fail2.json

@@ -0,0 +1,5 @@
+{
+    "type" : "CE",
+    "source" : "uwire_fail2.v",
+    "gold" : "uwire_fail2"
+}

ivtest/vvp_tests/uwire_fail3.json

@@ -0,0 +1,5 @@
+{
+    "type" : "CE",
+    "source" : "uwire_fail3.v",
+    "gold" : "uwire_fail3"
+}

ivtest/vvp_tests/uwire_fail4.json

@@ -0,0 +1,5 @@
+{
+    "type" : "CE",
+    "source" : "uwire_fail4.v",
+    "gold" : "uwire_fail4"
+}