Allow optional VHPI $finish implementation

tgt-vhdl/stmt.cc

@@ -110,11 +110,24 @@ static int draw_stask_display(vhdl_process *proc, stmt_container *container,
  * the simulator. This isn't great, as the simulator will
  * return a failure exit code when in fact it completed
  * successfully.
+ *
+ * An alternative is to use the VHPI interface supported by
+ * some VHDL simulators and implement the $finish funcitonality
+ * in C. This function can be enabled with the flag
+ * -puse-vhpi-finish=1. 
  */
 static int draw_stask_finish(vhdl_process *proc, stmt_container *container,
                              ivl_statement_t stmt)
 {
-   container->add_stmt(new vhdl_assert_stmt("SIMULATION FINISHED"));
+   const char *use_vhpi = ivl_design_flag(get_vhdl_design(), "use-vhpi-finish");
+   if (strcmp(use_vhpi, "1") == 0) {
+      proc->get_parent()->get_parent()->requires_package("work.Verilog_Support");
+      container->add_stmt(new vhdl_pcall_stmt("work.Verilog_Support.Finish"));
+   }
+   else {
+      container->add_stmt(new vhdl_assert_stmt("SIMULATION FINISHED"));
+   }
+   
    return 0;
 }
 

tgt-vhdl/vhdl.cc

@@ -48,6 +48,7 @@ typedef std::map<ivl_signal_t, signal_defn_t> signal_defn_map_t;
 static int g_errors = 0;  // Total number of errors encountered
 static entity_list_t g_entities;  // All entities to emit
 static signal_defn_map_t g_known_signals;
+static ivl_design_t g_design;
 
 
 /*
@@ -124,6 +125,10 @@ const std::string &get_renamed_signal(ivl_signal_t sig)
    return g_known_signals[sig].renamed;
 }
 
+ivl_design_t get_vhdl_design()
+{
+   return g_design;
+}
 
 extern "C" int target_design(ivl_design_t des)
 {
@@ -131,6 +136,8 @@ extern "C" int target_design(ivl_design_t des)
    unsigned int nroots;
    ivl_design_roots(des, &roots, &nroots);
 
+   g_design = des;
+
    for (unsigned int i = 0; i < nroots; i++)
       draw_scope(roots[i], NULL);
 

tgt-vhdl/vhdl_syntax.cc

@@ -495,7 +495,8 @@ void vhdl_expr_list::emit(std::ofstream &of, int level) const
 void vhdl_pcall_stmt::emit(std::ofstream &of, int level) const
 {
    of << name_;
-   exprs_.emit(of, level);
+   if (!exprs_.empty())
+      exprs_.emit(of, level);
    of << ";";
 }
 

tgt-vhdl/vhdl_syntax.hh

@@ -147,6 +147,7 @@ public:
    ~vhdl_expr_list();
    
    void emit(std::ofstream &of, int level) const;
+   bool empty() const { return exprs_.empty(); }
    void add_expr(vhdl_expr *e);
 private:
    std::list<vhdl_expr*> exprs_;

tgt-vhdl/vhdl_target.h

@@ -22,6 +22,8 @@ vhdl_expr *translate_expr(ivl_expr_t e);
 void remember_entity(vhdl_entity *ent);
 vhdl_entity *find_entity(const std::string &tname);
 
+ivl_design_t get_vhdl_design();
+
 vhdl_var_ref *nexus_to_var_ref(vhdl_arch *arch, ivl_nexus_t nexus);
 
 void remember_signal(ivl_signal_t sig, const vhdl_entity *ent);

tgt-vhdl/vhpi/finish.c

@@ -0,0 +1,6 @@
+#include <stdlib.h>
+
+void finish(void)
+{
+   exit(0);
+}

tgt-vhdl/vhpi/verilog_support.vhd

@@ -0,0 +1,15 @@
+--
+-- VHPI support routines for VHDL output.
+--
+
+package Verilog_Support is
+  procedure finish;
+  attribute foreign of finish : procedure is "VHPIDIRECT finish";
+end Verilog_Support;
+
+package body Verilog_Support is
+  procedure finish is
+  begin
+    assert false severity failure;
+  end finish;
+end Verilog_Support;