Support SystemVerilog types for non-ansi task port declarations
Tasks and functions support two types of port declarations. Either ANSI style, in parenthesis after the task name, or non-ANSI style, as declaration statements in the task body. In the current implementation SystemVerilog types are only accept for ANSI style port declarations, while non-ANSI style only accept Verilog types (reg, integer, time, real). Add support for SystemVerilog data types for non-ansi style ports. This also makes the parsing rules simpler since we can use `data_type` to match all data types and don't need a explicit rule for each supported data type. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen
parent
cc0a8c8dd2
commit
c631ff2483
55
parse.y
55
parse.y
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@ -590,7 +590,7 @@ static void current_function_set_statement(const YYLTYPE&loc, std::vector<Statem
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%type <number> number pos_neg_number
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%type <flag> signing unsigned_signed_opt signed_unsigned_opt
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%type <flag> import_export
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%type <flag> K_genvar_opt K_reg_opt K_static_opt K_virtual_opt
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%type <flag> K_genvar_opt K_static_opt K_virtual_opt
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%type <flag> udp_reg_opt edge_operator
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%type <drive> drive_strength drive_strength_opt dr_strength0 dr_strength1
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%type <letter> udp_input_sym udp_output_sym
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@ -2104,13 +2104,6 @@ random_qualifier /* IEEE1800-2005 A.1.8 */
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| K_randc { $$ = property_qualifier_t::make_randc(); }
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;
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/* real and realtime are exactly the same so save some code
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* with a common matching rule. */
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real_or_realtime
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: K_real
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| K_realtime
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;
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signing /* IEEE1800-2005: A.2.2.1 */
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: K_signed { $$ = true; }
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| K_unsigned { $$ = false; }
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@ -2353,50 +2346,9 @@ task_declaration /* IEEE1800-2005: A.2.7 */
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tf_port_declaration /* IEEE1800-2005: A.2.7 */
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: port_direction K_reg_opt unsigned_signed_opt dimensions_opt list_of_identifiers ';'
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{ std::vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1,
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$2 ? IVL_VT_LOGIC :
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IVL_VT_NO_TYPE,
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$3, $4, $5);
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$$ = tmp;
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: port_direction data_type_or_implicit list_of_identifiers ';'
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{ $$ = pform_make_task_ports(@1, $1, $2, $3, true);
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}
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/* When the port is an integer, infer a signed vector of the integer
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shape. Generate a range ([31:0]) to make it work. */
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| port_direction K_integer list_of_identifiers ';'
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{ std::list<pform_range_t>*range_stub = make_range_from_width(integer_width);
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vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1, IVL_VT_LOGIC, true,
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range_stub, $3, true);
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$$ = tmp;
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}
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/* Ports can be time with a width of [63:0] (unsigned). */
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| port_direction K_time list_of_identifiers ';'
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{ std::list<pform_range_t>*range_stub = make_range_from_width(64);
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vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1, IVL_VT_LOGIC, false,
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range_stub, $3);
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$$ = tmp;
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}
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/* Ports can be real or realtime. */
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| port_direction real_or_realtime list_of_identifiers ';'
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{ std::vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1, IVL_VT_REAL, true,
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0, $3);
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$$ = tmp;
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}
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/* Ports can be string. */
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| port_direction K_string list_of_identifiers ';'
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{ std::vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1, IVL_VT_STRING, true,
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0, $3);
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$$ = tmp;
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}
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;
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@ -7244,6 +7196,5 @@ unique_priority
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collect those rules here. */
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K_genvar_opt : K_genvar { $$ = true; } | { $$ = false; } ;
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K_reg_opt : K_reg { $$ = true; } | { $$ = false; } ;
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K_static_opt : K_static { $$ = true; } | { $$ = false; } ;
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K_virtual_opt : K_virtual { $$ = true; } | { $$ = false; } ;
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23
pform.cc
23
pform.cc
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@ -2923,13 +2923,13 @@ void pform_makewire(const struct vlltype&li,
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* constraints as those of tasks, so this works fine. Functions have
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* no output or inout ports.
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*/
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vector<pform_tf_port_t>*pform_make_task_ports(const struct vlltype&loc,
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NetNet::PortType pt,
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ivl_variable_type_t vtype,
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bool signed_flag,
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list<pform_range_t>*range,
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list<perm_string>*names,
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bool isint)
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static vector<pform_tf_port_t>*pform_make_task_ports(const struct vlltype&loc,
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NetNet::PortType pt,
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ivl_variable_type_t vtype,
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bool signed_flag,
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list<pform_range_t>*range,
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list<perm_string>*names,
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bool isint = false)
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{
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assert(pt != NetNet::PIMPLICIT && pt != NetNet::NOT_A_PORT);
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assert(names);
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@ -2999,7 +2999,8 @@ static vector<pform_tf_port_t>*do_make_task_ports(const struct vlltype&loc,
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vector<pform_tf_port_t>*pform_make_task_ports(const struct vlltype&loc,
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NetNet::PortType pt,
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data_type_t*vtype,
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list<perm_string>*names)
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list<perm_string>*names,
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bool allow_implicit)
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{
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vector<pform_tf_port_t>*ret = NULL;
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std::list<pform_range_t>*unpacked_dims = NULL;
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@ -3017,7 +3018,11 @@ vector<pform_tf_port_t>*pform_make_task_ports(const struct vlltype&loc,
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}
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if (vector_type_t*vec_type = dynamic_cast<vector_type_t*> (vtype)) {
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ret = pform_make_task_ports(loc, pt, vec_type->base_type,
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ivl_variable_type_t base_type = vec_type->base_type;
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if (allow_implicit && vec_type->implicit_flag)
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base_type = IVL_VT_NO_TYPE;
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ret = pform_make_task_ports(loc, pt, base_type,
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vec_type->signed_flag,
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copy_range(vec_type->pdims.get()),
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names, vec_type->integer_flag);
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13
pform.h
13
pform.h
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@ -492,20 +492,11 @@ extern void pform_make_pgassign_list(std::list<PExpr*>*alist,
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struct str_pair_t str,
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const char* fn, unsigned lineno);
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/* Given a port type and a list of names, make a list of wires that
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can be used as task port information. */
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extern std::vector<pform_tf_port_t>*pform_make_task_ports(const struct vlltype&loc,
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NetNet::PortType pt,
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ivl_variable_type_t vtype,
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bool signed_flag,
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std::list<pform_range_t>*range,
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std::list<perm_string>*names,
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bool isint = false);
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extern std::vector<pform_tf_port_t>*pform_make_task_ports(const struct vlltype&loc,
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NetNet::PortType pt,
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data_type_t*vtype,
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std::list<perm_string>*names);
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std::list<perm_string>*names,
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bool allow_implicit = false);
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/*
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* The parser uses this function to convert a unary
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