Add conversion from std_logic to (un)signed types
Implemented using the expression (0 => X, others => '0')
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@ -83,6 +83,15 @@ vhdl_expr *vhdl_expr::cast(const vhdl_type *to)
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return conv;
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}
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else if ((to->get_name() == VHDL_TYPE_UNSIGNED
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|| to->get_name() == VHDL_TYPE_SIGNED) &&
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type_->get_name() == VHDL_TYPE_STD_LOGIC) {
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vhdl_bit_spec_expr *bs =
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new vhdl_bit_spec_expr(new vhdl_type(*to), new vhdl_const_bit('0'));
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bs->add_bit(0, this);
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return bs;
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}
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else if (to->get_name() == VHDL_TYPE_STD_LOGIC &&
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type_->get_name() == VHDL_TYPE_BOOLEAN) {
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require_support_function(SF_BOOLEAN_TO_LOGIC);
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@ -735,6 +735,37 @@ void vhdl_binop_expr::emit(std::ostream &of, int level) const
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of << ")";
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}
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vhdl_bit_spec_expr::~vhdl_bit_spec_expr()
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{
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delete others_;
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std::list<bit_map>::iterator it;
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for (it = bits_.begin(); it != bits_.end(); ++it)
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delete (*it).e;
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}
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void vhdl_bit_spec_expr::add_bit(int bit, vhdl_expr *e)
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{
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bit_map bm = { bit, e };
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bits_.push_back(bm);
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}
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void vhdl_bit_spec_expr::emit(std::ostream &of, int level) const
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{
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of << "(";
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std::list<bit_map>::const_iterator it;
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for (it = bits_.begin(); it != bits_.end(); ++it) {
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of << (*it).bit << " => ";
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(*it).e->emit(of, level);
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of << ", ";
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}
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of << "others => ";
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others_->emit(of, level);
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of << ")";
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}
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vhdl_case_branch::~vhdl_case_branch()
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{
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delete when_;
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@ -129,6 +129,27 @@ private:
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};
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/*
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* An expression like (0 => '1', 2 => '0', others => 'Z')
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*/
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class vhdl_bit_spec_expr : public vhdl_expr {
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public:
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vhdl_bit_spec_expr(vhdl_type *type, vhdl_expr *others)
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: vhdl_expr(type), others_(others) {}
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~vhdl_bit_spec_expr();
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void add_bit(int bit, vhdl_expr *e);
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void emit(std::ostream &of, int level) const;
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private:
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vhdl_expr *others_;
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struct bit_map {
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int bit;
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vhdl_expr *e;
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};
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std::list<bit_map> bits_;
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};
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class vhdl_const_string : public vhdl_expr {
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public:
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vhdl_const_string(const char *value)
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