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Code generator for architectures. 

Separate elaboration from code generation in the Entity, and add
to Architectures a code generator to handle some simple cases. At
this point we have the basic structure for the VHDL compiler.
This commit is contained in:
Stephen Williams 2011-01-31 11:16:14 -08:00
parent 769159d053
commit 798ead9345
9 changed files with 284 additions and 43 deletions
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4
vhdlpp/Makefile.in
View File

@ -60,7 +60,9 @@ LIBS = @LIBS@ @EXTRALIBS@
M = StringHeap.o LineInfo.o
O = main.o architec.o compiler.o entity.o entity_elaborate.o \
expression.o lexor.o lexor_keyword.o parse.o vhdlreal.o vhdlint.o debug.o $M
expression.o lexor.o lexor_keyword.o parse.o vhdlreal.o vhdlint.o debug.o \
architec_emit.o entity_emit.o expression_emit.o \
$M
all: dep vhdlpp@EXEEXT@

10
vhdlpp/architec.h
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@ -23,6 +23,7 @@
# include "LineInfo.h"
# include <list>
class Entity;
class Expression;
/*
@ -41,6 +42,7 @@ class Architecture : public LineInfo {
Statement();
virtual ~Statement() =0;
virtual int emit(ostream&out, Entity*ent, Architecture*arc);
virtual void dump(ostream&out) const;
private:
@ -56,6 +58,13 @@ class Architecture : public LineInfo {
perm_string get_name() const { return name_; }
// Emit this architecture to the given out file in the context
// of the specified entity. This method is used by the
// elaborate code to display generated code to the specified
// output.
int emit(ostream&out, Entity*entity);
// The dump method writes a debug display to the given output.
void dump(ostream&out, perm_string of_entity) const;
private:
@ -76,6 +85,7 @@ class SignalAssignment : public Architecture::Statement {
SignalAssignment(perm_string target_name, std::list<Expression*>&rval);
~SignalAssignment();
int emit(ostream&out, Entity*entity, Architecture*arc);
virtual void dump(ostream&out) const;
private:

62
vhdlpp/architec_emit.cc Normal file
View File

@ -0,0 +1,62 @@
/*
* Copyright (c) 2011 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "architec.h"
# include "entity.h"
# include "expression.h"
# include <iostream>
# include <typeinfo>
# include <cassert>
int Architecture::emit(ostream&out, Entity*entity)
{
int errors = 0;
for (list<Architecture::Statement*>::iterator cur = statements_.begin()
; cur != statements_.end() ; ++cur) {
errors += (*cur)->emit(out, entity, this);
}
return errors;
}
int Architecture::Statement::emit(ostream&out, Entity*, Architecture*)
{
out << " // " << get_fileline() << ": internal error: "
<< "I don't know how to emit this statement! "
<< "type=" << typeid(*this).name() << endl;
return 1;
}
int SignalAssignment::emit(ostream&out, Entity*ent, Architecture*arc)
{
int errors = 0;
assert(rval_.size() == 1);
Expression*rval = rval_.front();
out << "// " << get_fileline() << endl;
out << "assign " << target_name_ << " = ";
errors += rval->emit(out, ent, arc);
out << ";" << endl;
return errors;
}

5
vhdlpp/entity.h
View File

@ -56,6 +56,7 @@ class Entity : public LineInfo {
Architecture* add_architecture(Architecture*);
int elaborate();
int emit(ostream&out);
void dump(ostream&out) const;
@ -66,6 +67,8 @@ class Entity : public LineInfo {
perm_string name_;
std::map<perm_string,Architecture*>arch_;
Architecture*bind_arch_;
};
/*
@ -80,6 +83,8 @@ extern std::map<perm_string,Entity*> design_entities;
*/
extern int elaborate_entities(void);
extern int emit_entities(void);
/*
* Use this function to dump a description of the design entities to a
* file. This is for debug, not for any useful purpose.

62
vhdlpp/entity_elaborate.cc
View File

@ -19,6 +19,7 @@
# include "entity.h"
# include "compiler.h"
# include "architec.h"
# include <iostream>
# include <fstream>
# include <iomanip>
@ -44,47 +45,32 @@ int Entity::elaborate()
if (verbose_flag)
cerr << "Elaborate entity " << name_ << "..." << endl;
cout << "module " << name_;
// If there are ports, emit them.
if (ports.size() > 0) {
cout << "(";
const char*sep = 0;
for (vector<InterfacePort*>::iterator cur = ports.begin()
; cur != ports.end() ; ++cur) {
InterfacePort*port = *cur;
// FIXME: this is a stub. This port handling code
// currently only supports std_logic signal tyes,
// so just assert that the user asked for std_logic.
if (port->type_name != "std_logic") {
cerr << "sorry: VHDL only supports std_logic ports."
<< " Expecting std_logic, but got \""
<< port->type_name << "\"" << endl;
errors += 1;
}
if (sep) cout << sep;
else sep = ", ";
switch (port->mode) {
case PORT_NONE: // Should not happen
cout << "NO_PORT " << port->name;
break;
case PORT_IN:
cout << "input " << port->name;
break;
case PORT_OUT:
cout << "output " << port->name;
break;
}
}
cout << ")";
if (arch_.size() == 0) {
cerr << get_fileline() << ": error: "
<< "No architectures to choose from for entity " << name_
<< "." << endl;
return 1;
}
cout << ";" << endl;
cout << "endmodule" << endl;
if (arch_.size() > 1) {
cerr << get_fileline() << ": sorry: "
<< "Too many architectures for entity " << name_
<< ". Architectures are:" << endl;
for (map<perm_string,Architecture*>::const_iterator cur = arch_.begin()
; cur != arch_.end() ; ++cur) {
cerr << get_fileline() << ": : " << cur->first
<< " at " << cur->second->get_fileline() << endl;
}
errors += 1;
}
bind_arch_ = arch_.begin()->second;
if (verbose_flag)
cerr << "For entity " << get_name()
<< ", choosing architecture " << bind_arch_->get_name()
<< "." << endl;
return errors;
}

87
vhdlpp/entity_emit.cc Normal file
View File

@ -0,0 +1,87 @@
/*
* Copyright (c) 2011 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "entity.h"
# include "architec.h"
# include <iostream>
# include <fstream>
# include <iomanip>
int emit_entities(void)
{
int errors = 0;
for (map<perm_string,Entity*>::iterator cur = design_entities.begin()
; cur != design_entities.end() ; ++cur) {
errors += cur->second->emit(cout);
}
return errors;
}
int Entity::emit(ostream&out)
{
int errors = 0;
out << "module " << name_;
// If there are ports, emit them.
if (ports.size() > 0) {
out << "(";
const char*sep = 0;
for (vector<InterfacePort*>::iterator cur = ports.begin()
; cur != ports.end() ; ++cur) {
InterfacePort*port = *cur;
// FIXME: this is a stub. This port handling code
// currently only supports std_logic signal tyes,
// so just assert that the user asked for std_logic.
if (port->type_name != "std_logic") {
cerr << "sorry: VHDL only supports std_logic ports."
<< " Expecting std_logic, but got \""
<< port->type_name << "\"" << endl;
errors += 1;
}
if (sep) out << sep;
else sep = ", ";
switch (port->mode) {
case PORT_NONE: // Should not happen
out << "NO_PORT " << port->name;
break;
case PORT_IN:
out << "input " << port->name;
break;
case PORT_OUT:
out << "output " << port->name;
break;
}
}
cout << ")";
}
out << ";" << endl;
errors += bind_arch_->emit(out, this);
out << "endmodule" << endl;
return errors;
}

11
vhdlpp/expression.h
View File

@ -22,6 +22,9 @@
# include "StringHeap.h"
# include "LineInfo.h"
class Entity;
class Architecture;
/*
* The Expression class represents parsed expressions from the parsed
* VHDL input. The Expression class is a virtual class that holds more
@ -33,6 +36,12 @@ class Expression : public LineInfo {
Expression();
virtual ~Expression() =0;
// The emit virtual method is called bu architecture emit to
// output the generated code for the expression. The derived
// class fills in the details of what exactly happend.
virtual int emit(ostream&out, Entity*ent, Architecture*arc);
// Debug dump of the expression.
virtual void dump(ostream&out, int indent) const;
private:
@ -51,6 +60,7 @@ class ExpLogical : public Expression {
ExpLogical(ExpLogical::fun_t ty, Expression*op1, Expression*op2);
~ExpLogical();
int emit(ostream&out, Entity*ent, Architecture*arc);
void dump(ostream&out, int indent) const;
private:
@ -69,6 +79,7 @@ class ExpName : public Expression {
ExpName(perm_string nn);
~ExpName();
int emit(ostream&out, Entity*ent, Architecture*arc);
void dump(ostream&out, int indent) const;
private:

72
vhdlpp/expression_emit.cc Normal file
View File

@ -0,0 +1,72 @@
/*
* Copyright (c) 2011 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "expression.h"
# include <typeinfo>
# include <iostream>
using namespace std;
int Expression::emit(ostream&out, Entity*, Architecture*)
{
out << " /* " << get_fileline() << ": internal error: "
<< "I don't know how to emit this expression! "
<< "type=" << typeid(*this).name() << " */ ";
return 1;
}
int ExpLogical::emit(ostream&out, Entity*ent, Architecture*arc)
{
int errors = 0;
errors += operand1_->emit(out, ent, arc);
switch (fun_) {
case AND:
out << " & ";
break;
case OR:
out << " | ";
break;
case XOR:
out << " ^ ";
break;
case NAND:
out << " ~& ";
break;
case NOR:
out << " ~| ";
break;
case XNOR:
out << " ~^ ";
break;
}
errors += operand2_->emit(out, ent, arc);
return errors;
}
int ExpName::emit(ostream&out, Entity*, Architecture*)
{
int errors = 0;
out << name_;
return errors;
}

14
vhdlpp/main.cc
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@ -115,13 +115,19 @@ int main(int argc, char*argv[])
if (dump_design_entities_path)
dump_design_entities(dump_design_entities_path);
int elaborate_errors = 0;
elaborate_errors = elaborate_entities();
if (elaborate_errors > 0) {
fprintf(stderr, "%d errors elaborating design.\n", elaborate_errors);
int errors = 0;
errors = elaborate_entities();
if (errors > 0) {
fprintf(stderr, "%d errors elaborating design.\n", errors);
return 3;
}
errors = emit_entities();
if (errors > 0) {
fprintf(stderr, "%d errors emitting design.\n", errors);
return 4;
}
lex_strings.cleanup();
return 0;
}