Force instruction that can be indexed.
This commit is contained in:
steve
parent
0e044d6684
commit
2b8fd28a95
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: codes.h,v 1.76 2005/09/17 04:01:01 steve Exp $"
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#ident "$Id: codes.h,v 1.77 2005/11/26 17:16:05 steve Exp $"
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#endif
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@ -73,6 +73,7 @@ extern bool of_DIV_WR(vthread_t thr, vvp_code_t code);
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extern bool of_END(vthread_t thr, vvp_code_t code);
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extern bool of_FORCE_LINK(vthread_t thr, vvp_code_t code);
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extern bool of_FORCE_V(vthread_t thr, vvp_code_t code);
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extern bool of_FORCE_X0(vthread_t thr, vvp_code_t code);
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extern bool of_FORK(vthread_t thr, vvp_code_t code);
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extern bool of_INV(vthread_t thr, vvp_code_t code);
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extern bool of_IX_ADD(vthread_t thr, vvp_code_t code);
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@ -178,6 +179,9 @@ extern vvp_code_t codespace_null(void);
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/*
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* $Log: codes.h,v $
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* Revision 1.77 2005/11/26 17:16:05 steve
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* Force instruction that can be indexed.
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*
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* Revision 1.76 2005/09/17 04:01:01 steve
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* Add the load/v.p instruction.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: compile.cc,v 1.214 2005/10/12 17:23:15 steve Exp $"
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#ident "$Id: compile.cc,v 1.215 2005/11/26 17:16:05 steve Exp $"
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#endif
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# include "arith.h"
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@ -118,6 +118,7 @@ const static struct opcode_table_s opcode_table[] = {
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{ "%end", of_END, 0, {OA_NONE, OA_NONE, OA_NONE} },
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{ "%force/link",of_FORCE_LINK,2,{OA_FUNC_PTR,OA_FUNC_PTR2,OA_NONE} },
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{ "%force/v",of_FORCE_V,3, {OA_FUNC_PTR, OA_BIT1, OA_BIT2} },
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{ "%force/x0",of_FORCE_X0,3,{OA_FUNC_PTR, OA_BIT1, OA_BIT2} },
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{ "%inv", of_INV, 2, {OA_BIT1, OA_BIT2, OA_NONE} },
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{ "%ix/add", of_IX_ADD, 2, {OA_BIT1, OA_NUMBER, OA_NONE} },
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{ "%ix/get", of_IX_GET, 3, {OA_BIT1, OA_BIT2, OA_NUMBER} },
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@ -1481,6 +1482,9 @@ void compile_param_string(char*label, char*name, char*str, char*value)
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/*
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* $Log: compile.cc,v $
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* Revision 1.215 2005/11/26 17:16:05 steve
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* Force instruction that can be indexed.
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*
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* Revision 1.214 2005/10/12 17:23:15 steve
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* Add alias nodes.
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*
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@ -1,7 +1,7 @@
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/*
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* Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com)
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*
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* $Id: opcodes.txt,v 1.68 2005/09/19 21:45:37 steve Exp $
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* $Id: opcodes.txt,v 1.69 2005/11/26 17:16:05 steve Exp $
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*/
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@ -263,6 +263,14 @@ functor instead of the normal assign port (port-0), so the signal
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responds differently. See "VARIABLE STATEMENTS" and "NET STATEMENTS"
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in the README.txt file.
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* %force/x0 <label>, <bit>, <wid>
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Force a constant value to part target variable. This is similar to
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%set/x instruction, but it uses the force port (port-2) of the signal
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functor instead of the normal assign port (port-0), so the signal
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responds differently. See "VARIABLE STATEMENTS" and "NET STATEMENTS"
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in the README.txt file.
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* %fork <code-label>, <scope-label>
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This instruction is similar to %jmp, except that it creates a new
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: vthread.cc,v 1.149 2005/11/25 17:55:26 steve Exp $"
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#ident "$Id: vthread.cc,v 1.150 2005/11/26 17:16:05 steve Exp $"
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#endif
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# include "config.h"
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@ -1566,6 +1566,45 @@ bool of_FORCE_V(vthread_t thr, vvp_code_t cp)
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return true;
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}
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bool of_FORCE_X0(vthread_t thr, vvp_code_t cp)
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{
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vvp_net_t*net = cp->net;
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unsigned bit = cp->bit_idx[0];
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unsigned wid = cp->bit_idx[1];
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// Implicitly, we get the base into the target vector from the
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// X0 register.
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long index = thr->words[0].w_int;
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vvp_fun_signal_vec*sig = dynamic_cast<vvp_fun_signal_vec*> (net->fun);
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if (index < 0 && (wid <= (unsigned)-index))
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return true;
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if (index >= (long)sig->size())
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return true;
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if (index < 0) {
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wid -= (unsigned) -index;
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index = 0;
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}
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if (index+wid > sig->size())
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wid = sig->size() - index;
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vvp_vector4_t bit_vec(wid);
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for (unsigned idx = 0 ; idx < wid ; idx += 1) {
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vvp_bit4_t bit_val = thr_get_bit(thr, bit);
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bit_vec.set_bit(idx, bit_val);
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if (bit >= 4)
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bit += 1;
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}
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vvp_net_ptr_t ptr (net, 2);
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vvp_send_vec4_pv(ptr, bit_vec, index, wid, sig->size());
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return true;
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}
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/*
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* The %fork instruction causes a new child to be created and pushed
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* in front of any existing child. This causes the new child to be the
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@ -2827,7 +2866,7 @@ bool of_SET_X0(vthread_t thr, vvp_code_t cp)
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// X0 register.
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long index = thr->words[0].w_int;
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vvp_fun_signal*sig = dynamic_cast<vvp_fun_signal*> (net->fun);
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vvp_fun_signal_vec*sig = dynamic_cast<vvp_fun_signal_vec*> (net->fun);
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if (index < 0 && (wid <= (unsigned)-index))
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return true;
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@ -3189,6 +3228,9 @@ bool of_JOIN_UFUNC(vthread_t thr, vvp_code_t cp)
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/*
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* $Log: vthread.cc,v $
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* Revision 1.150 2005/11/26 17:16:05 steve
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* Force instruction that can be indexed.
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*
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* Revision 1.149 2005/11/25 17:55:26 steve
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* Put vec8 and vec4 nets into seperate net classes.
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*
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124
vvp/vvp_net.cc
124
vvp/vvp_net.cc
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@ -16,7 +16,7 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ident "$Id: vvp_net.cc,v 1.48 2005/11/25 17:55:26 steve Exp $"
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#ident "$Id: vvp_net.cc,v 1.49 2005/11/26 17:16:05 steve Exp $"
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# include "config.h"
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# include "vvp_net.h"
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@ -632,6 +632,17 @@ vvp_vector2_t::vvp_vector2_t(unsigned long v, unsigned wid)
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vec_[idx] = 0;
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}
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vvp_vector2_t::vvp_vector2_t(vvp_vector2_t::fill_t fill, unsigned wid)
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{
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wid_ = wid;
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const unsigned bits_per_word = 8 * sizeof(vec_[0]);
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const unsigned words = (wid_ + bits_per_word-1) / bits_per_word;
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vec_ = new unsigned long[words];
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for (unsigned idx = 0 ; idx < words ; idx += 1)
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vec_[idx] = fill? -1 : 0;
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}
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vvp_vector2_t::vvp_vector2_t(const vvp_vector4_t&that)
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{
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wid_ = that.size();
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@ -892,6 +903,20 @@ int vvp_vector2_t::value(unsigned idx) const
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return 0;
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}
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void vvp_vector2_t::set_bit(unsigned idx, int bit)
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{
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assert(idx < wid_);
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const unsigned bits_per_word = 8 * sizeof(vec_[0]);
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unsigned addr = idx/bits_per_word;
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unsigned long mask = idx%bits_per_word;
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if (bit)
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vec_[addr] |= 1UL << mask;
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else
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vec_[addr] &= ~(1UL << mask);
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}
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bool vvp_vector2_t::is_NaN() const
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{
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return wid_ == 0;
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@ -1290,7 +1315,6 @@ vvp_fun_signal_base::vvp_fun_signal_base()
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{
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needs_init_ = true;
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continuous_assign_active_ = false;
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force_active_ = false;
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force_link = 0;
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}
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@ -1350,12 +1374,15 @@ void vvp_fun_signal::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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switch (ptr.port()) {
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case 0: // Normal input (feed from net, or set from process)
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/* If continuous assign is active, then this is a var
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and the continuous assigned values overrides any
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normal input. So process input only if continuous
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assignment is not active. */
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if (!continuous_assign_active_) {
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if (needs_init_ || !bits4_.eeq(bit)) {
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bits4_ = bit;
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needs_init_ = false;
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vvp_send_vec4(ptr.ptr()->out, bit);
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run_vpi_callbacks();
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calculate_output_(ptr);
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}
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}
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break;
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@ -1363,8 +1390,7 @@ void vvp_fun_signal::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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case 1: // Continuous assign value
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continuous_assign_active_ = true;
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bits4_ = bit;
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vvp_send_vec4(ptr.ptr()->out, bits4_);
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run_vpi_callbacks();
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calculate_output_(ptr);
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break;
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case 2: // Force value
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@ -1376,9 +1402,8 @@ void vvp_fun_signal::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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else
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force_ = bit;
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force_active_ = true;
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vvp_send_vec4(ptr.ptr()->out, force_);
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run_vpi_callbacks();
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force_mask_ = vvp_vector2_t(vvp_vector2_t::FILL1, size());
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calculate_output_(ptr);
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break;
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default:
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@ -1402,17 +1427,50 @@ void vvp_fun_signal::recv_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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bits4_.set_bit(base+idx, bit.value(idx));
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}
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needs_init_ = false;
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vvp_send_vec4(ptr.ptr()->out, bits4_);
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run_vpi_callbacks();
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calculate_output_(ptr);
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}
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break;
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case 2: // Force value
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if (force_mask_.size() == 0)
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force_mask_ = vvp_vector2_t(vvp_vector2_t::FILL0, size());
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if (force_.size() == 0)
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force_ = vvp_vector4_t(vwid, BIT4_Z);
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for (unsigned idx = 0 ; idx < wid ; idx += 1) {
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force_mask_.set_bit(base+idx, 1);
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force_.set_bit(base+idx, bit.value(idx));
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}
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calculate_output_(ptr);
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break;
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default:
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assert(0);
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break;
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}
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}
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void vvp_fun_signal::calculate_output_(vvp_net_ptr_t ptr)
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{
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if (force_mask_.size()) {
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assert(bits4_.size() == force_mask_.size());
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assert(bits4_.size() == force_.size());
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vvp_vector4_t bits (bits4_);
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for (unsigned idx = 0 ; idx < bits.size() ; idx += 1) {
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if (force_mask_.value(idx))
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bits.set_bit(idx, force_.value(idx));
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}
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vvp_send_vec4(ptr.ptr()->out, bits);
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} else {
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vvp_send_vec4(ptr.ptr()->out, bits4_);
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}
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run_vpi_callbacks();
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}
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void vvp_fun_signal::recv_vec8(vvp_net_ptr_t ptr, vvp_vector8_t bit)
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{
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recv_vec4(ptr, reduce4(bit));
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@ -1421,7 +1479,7 @@ void vvp_fun_signal::recv_vec8(vvp_net_ptr_t ptr, vvp_vector8_t bit)
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void vvp_fun_signal::release(vvp_net_ptr_t ptr, bool net)
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{
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force_active_ = false;
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force_mask_ = vvp_vector2_t();
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if (net) {
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vvp_send_vec4(ptr.ptr()->out, bits4_);
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run_vpi_callbacks();
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@ -1432,7 +1490,7 @@ void vvp_fun_signal::release(vvp_net_ptr_t ptr, bool net)
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unsigned vvp_fun_signal::size() const
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{
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if (force_active_)
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if (force_mask_.size())
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return force_.size();
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else
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return bits4_.size();
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@ -1440,7 +1498,7 @@ unsigned vvp_fun_signal::size() const
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vvp_bit4_t vvp_fun_signal::value(unsigned idx) const
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{
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if (force_active_)
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if (force_mask_.size() && force_mask_.value(idx))
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return force_.value(idx);
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else
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return bits4_.value(idx);
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@ -1448,7 +1506,7 @@ vvp_bit4_t vvp_fun_signal::value(unsigned idx) const
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vvp_scalar_t vvp_fun_signal::scalar_value(unsigned idx) const
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{
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if (force_active_)
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if (force_mask_.size() && force_mask_.value(idx))
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return vvp_scalar_t(force_.value(idx), 6, 6);
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else
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return vvp_scalar_t(bits4_.value(idx), 6, 6);
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@ -1456,10 +1514,19 @@ vvp_scalar_t vvp_fun_signal::scalar_value(unsigned idx) const
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vvp_vector4_t vvp_fun_signal::vec4_value() const
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{
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if (force_active_)
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return force_;
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else
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if (force_mask_.size()) {
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assert(bits4_.size() == force_mask_.size());
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assert(bits4_.size() == force_.size());
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vvp_vector4_t bits (bits4_);
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for (unsigned idx = 0 ; idx < bits.size() ; idx += 1) {
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if (force_mask_.value(idx))
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bits.set_bit(idx, force_.value(idx));
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}
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return bits;
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} else {
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return bits4_;
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}
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}
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vvp_fun_signal8::vvp_fun_signal8(unsigned wid)
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@ -1502,7 +1569,7 @@ void vvp_fun_signal8::recv_vec8(vvp_net_ptr_t ptr, vvp_vector8_t bit)
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else
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force_ = bit;
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force_active_ = true;
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force_mask_ = vvp_vector2_t(vvp_vector2_t::FILL1, size());
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vvp_send_vec8(ptr.ptr()->out, force_);
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run_vpi_callbacks();
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break;
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@ -1515,7 +1582,7 @@ void vvp_fun_signal8::recv_vec8(vvp_net_ptr_t ptr, vvp_vector8_t bit)
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void vvp_fun_signal8::release(vvp_net_ptr_t ptr, bool net)
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{
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force_active_ = false;
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force_mask_ = vvp_vector2_t();
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if (net) {
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vvp_send_vec8(ptr.ptr()->out, bits8_);
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run_vpi_callbacks();
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@ -1526,7 +1593,7 @@ void vvp_fun_signal8::release(vvp_net_ptr_t ptr, bool net)
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unsigned vvp_fun_signal8::size() const
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{
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if (force_active_)
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if (force_mask_.size())
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return force_.size();
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else
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return bits8_.size();
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@ -1534,7 +1601,7 @@ unsigned vvp_fun_signal8::size() const
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vvp_bit4_t vvp_fun_signal8::value(unsigned idx) const
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{
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if (force_active_)
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if (force_mask_.size() && force_mask_.value(idx))
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return force_.value(idx).value();
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else
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return bits8_.value(idx).value();
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@ -1542,7 +1609,7 @@ vvp_bit4_t vvp_fun_signal8::value(unsigned idx) const
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vvp_vector4_t vvp_fun_signal8::vec4_value() const
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{
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if (force_active_)
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if (force_mask_.size())
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return reduce4(force_);
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else
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return reduce4(bits8_);
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@ -1550,7 +1617,7 @@ vvp_vector4_t vvp_fun_signal8::vec4_value() const
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vvp_scalar_t vvp_fun_signal8::scalar_value(unsigned idx) const
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{
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if (force_active_)
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||||
if (force_mask_.size() && force_mask_.value(idx))
|
||||
return force_.value(idx);
|
||||
else
|
||||
return bits8_.value(idx);
|
||||
|
|
@ -1562,7 +1629,7 @@ vvp_fun_signal_real::vvp_fun_signal_real()
|
|||
|
||||
double vvp_fun_signal_real::real_value() const
|
||||
{
|
||||
if (force_active_)
|
||||
if (force_mask_.size())
|
||||
return force_;
|
||||
else
|
||||
return bits_;
|
||||
|
|
@ -1590,7 +1657,7 @@ void vvp_fun_signal_real::recv_real(vvp_net_ptr_t ptr, double bit)
|
|||
break;
|
||||
|
||||
case 2: // Force value
|
||||
force_active_ = true;
|
||||
force_mask_ = vvp_vector2_t(1, 1);
|
||||
force_ = bit;
|
||||
vvp_send_real(ptr.ptr()->out, bit);
|
||||
run_vpi_callbacks();
|
||||
|
|
@ -1604,7 +1671,7 @@ void vvp_fun_signal_real::recv_real(vvp_net_ptr_t ptr, double bit)
|
|||
|
||||
void vvp_fun_signal_real::release(vvp_net_ptr_t ptr, bool net)
|
||||
{
|
||||
force_active_ = false;
|
||||
force_mask_ = vvp_vector2_t();
|
||||
if (net) {
|
||||
vvp_send_real(ptr.ptr()->out, bits_);
|
||||
run_vpi_callbacks();
|
||||
|
|
@ -2073,6 +2140,9 @@ vvp_bit4_t compare_gtge_signed(const vvp_vector4_t&a,
|
|||
|
||||
/*
|
||||
* $Log: vvp_net.cc,v $
|
||||
* Revision 1.49 2005/11/26 17:16:05 steve
|
||||
* Force instruction that can be indexed.
|
||||
*
|
||||
* Revision 1.48 2005/11/25 17:55:26 steve
|
||||
* Put vec8 and vec4 nets into seperate net classes.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ident "$Id: vvp_net.h,v 1.48 2005/11/25 17:55:26 steve Exp $"
|
||||
#ident "$Id: vvp_net.h,v 1.49 2005/11/26 17:16:05 steve Exp $"
|
||||
|
||||
# include "config.h"
|
||||
# include <stddef.h>
|
||||
|
|
@ -276,6 +276,9 @@ class vvp_vector2_t {
|
|||
explicit vvp_vector2_t(const vvp_vector4_t&that);
|
||||
// Make from a native long and a specified width.
|
||||
vvp_vector2_t(unsigned long val, unsigned wid);
|
||||
// Make with the width, and filled with 1 or 0 bits.
|
||||
enum fill_t {FILL0, FILL1};
|
||||
vvp_vector2_t(fill_t fill, unsigned wid);
|
||||
~vvp_vector2_t();
|
||||
|
||||
vvp_vector2_t&operator += (const vvp_vector2_t&that);
|
||||
|
|
@ -287,6 +290,7 @@ class vvp_vector2_t {
|
|||
bool is_NaN() const;
|
||||
unsigned size() const;
|
||||
int value(unsigned idx) const;
|
||||
void set_bit(unsigned idx, int bit);
|
||||
|
||||
private:
|
||||
enum { BITS_PER_WORD = 8 * sizeof(unsigned long) };
|
||||
|
|
@ -777,7 +781,7 @@ class vvp_fun_signal_base : public vvp_net_fun_t, public vvp_vpi_callback {
|
|||
// This is true until at least one propagation happens.
|
||||
bool needs_init_;
|
||||
bool continuous_assign_active_;
|
||||
bool force_active_;
|
||||
vvp_vector2_t force_mask_;
|
||||
|
||||
void deassign();
|
||||
virtual void release(vvp_net_ptr_t ptr, bool net) =0;
|
||||
|
|
@ -821,6 +825,8 @@ class vvp_fun_signal : public vvp_fun_signal_vec {
|
|||
void get_value(struct t_vpi_value*value);
|
||||
|
||||
private:
|
||||
void calculate_output_(vvp_net_ptr_t ptr);
|
||||
|
||||
vvp_vector4_t bits4_;
|
||||
vvp_vector4_t force_;
|
||||
};
|
||||
|
|
@ -849,6 +855,8 @@ class vvp_fun_signal8 : public vvp_fun_signal_vec {
|
|||
void get_value(struct t_vpi_value*value);
|
||||
|
||||
private:
|
||||
void calculate_output_(vvp_net_ptr_t ptr);
|
||||
|
||||
vvp_vector8_t bits8_;
|
||||
vvp_vector8_t force_;
|
||||
};
|
||||
|
|
@ -997,6 +1005,9 @@ inline void vvp_send_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&val,
|
|||
|
||||
/*
|
||||
* $Log: vvp_net.h,v $
|
||||
* Revision 1.49 2005/11/26 17:16:05 steve
|
||||
* Force instruction that can be indexed.
|
||||
*
|
||||
* Revision 1.48 2005/11/25 17:55:26 steve
|
||||
* Put vec8 and vec4 nets into seperate net classes.
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue