Add regression tests for invalid module port declarations

Check that all kinds of invalid module port declarations, where the
declaration conflicts with previous declarations, are detected as errors.
They should not crash the application nor should they result in successful
elaboration.

The tests are created for corner cases that previously resulted in
incorrect behavior.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/module_nonansi_fail1.v

@@ -0,0 +1,7 @@
+// Check that declaring multiple non-ANSI module ports with the same name is an
+// error. Even if they both have an implicit type.
+
+module test(x);
+  input x;
+  input x;
+endmodule

ivtest/ivltests/module_nonansi_fail10.v

@@ -0,0 +1,7 @@
+// Check that declaring a non-ANSI module port with an explicit type for a
+// signal that was previously declared as a real variable is an error.
+
+module test(x);
+  real x;
+  output integer x;
+endmodule

ivtest/ivltests/module_nonansi_fail11.v

@@ -0,0 +1,9 @@
+// Check that declaring multiple non-ANSI module ports with an implicit type and
+// the same name is an error. Even if the signal was previously declared as a
+// net.
+
+module test(x);
+  wire x;
+  input x;
+  input x;
+endmodule

ivtest/ivltests/module_nonansi_fail12.v

@@ -0,0 +1,10 @@
+// Check that declaring multiple non-ANSI module ports with an implicit type and
+// the same name is an error. Even if the signal was previously declared as a
+// integer typed net.
+
+module test(x);
+  wire integer x;
+  input x;
+  input x;
+
+endmodule

ivtest/ivltests/module_nonansi_fail13.v

@@ -0,0 +1,8 @@
+// Check that declaring multiple non-ANSI module output ports with an explicit
+// type is an error. Even if the types are the same.
+
+module test(x);
+  output integer x;
+  output integer x;
+
+endmodule

ivtest/ivltests/module_nonansi_fail2.v

@@ -0,0 +1,8 @@
+// Check that declaring a net multiple times for a signal that was previously
+// declared as a non-ANSI module port is an error.
+
+module test(x);
+  input x;
+  wire x;
+  wire x;
+endmodule

ivtest/ivltests/module_nonansi_fail3.v

@@ -0,0 +1,8 @@
+// Check that declaring a variable multiple times for a signal that was
+// previously declared as a non-ANSI module port is an error.
+
+module test(x);
+  output x;
+  reg x;
+  reg x;
+endmodule

ivtest/ivltests/module_nonansi_fail4.v

@@ -0,0 +1,8 @@
+// Check that declaring both a net and a variable for a signal that was
+// previously declared as a non-ANSI module port is an error.
+
+module test(x);
+  input x;
+  wire x;
+  reg x;
+endmodule

ivtest/ivltests/module_nonansi_fail5.v

@@ -0,0 +1,8 @@
+// Check that declaring an integer typed non-ANSI module port for signal that
+// was previously declared as a net is an error. Even if the types for both
+// declarations are the same.
+
+module test(x);
+  wire integer x;
+  input integer x;
+endmodule

ivtest/ivltests/module_nonansi_fail6.v

@@ -0,0 +1,8 @@
+// Check that declaring an integer typed net for a signal that was previously
+// declared as a non-ANSI module port is an error. Even if the types for both
+// declarations are the same.
+
+module test(x);
+  input integer x;
+  wire integer x;
+endmodule

ivtest/ivltests/module_nonansi_fail7.v

@@ -0,0 +1,8 @@
+// Check that declaring a real typed variable for a signal that was previously
+// declared as a non-ANSI module port is an error. Even if the types for both
+// declarations are the same.
+
+module test(x);
+  output real x;
+  real x;
+endmodule

ivtest/ivltests/module_nonansi_fail8.v

@@ -0,0 +1,8 @@
+// Check that declaring a real typed non-ANSI module port for a signal that was
+// previously declared as a variable is an error. Even if the types for both
+// declarations are the same.
+
+module test(x);
+  real x;
+  output real x;
+endmodule

ivtest/ivltests/module_nonansi_fail9.v

@@ -0,0 +1,7 @@
+// Check that declaring an integer typed variable for a signal that was previously
+// declared as a real typed non-ANSI module port is an error.
+
+module test(x);
+  output real x;
+  integer x;
+endmodule

ivtest/regress-vlg.list

@@ -654,6 +654,19 @@ module_inout_port_list_def CE			ivltests # inout ports do not support default va
 module_inout_port_type	CE			ivltests
 module_input_port_list_def CE			ivltests # input ports only support default values in SV
 module_input_port_type	CE			ivltests
+module_nonansi_fail1	CE			ivltests
+module_nonansi_fail2	CE			ivltests
+module_nonansi_fail3	CE			ivltests
+module_nonansi_fail4	CE			ivltests
+module_nonansi_fail5	CE			ivltests
+module_nonansi_fail6	CE			ivltests
+module_nonansi_fail7	CE			ivltests
+module_nonansi_fail8	CE			ivltests
+module_nonansi_fail9	CE			ivltests
+module_nonansi_fail10	CE			ivltests
+module_nonansi_fail11	CE			ivltests
+module_nonansi_fail12	CE			ivltests
+module_nonansi_fail13	CE			ivltests
 module_nonansi_integer1	normal			ivltests
 module_nonansi_integer2	normal			ivltests
 module_nonansi_integer_fail CE			ivltests