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vhdlpp: Allow assigning values to inout ports.

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This commit is contained in:
Maciej Suminski
2015-05-20 17:30:07 +02:00
parent bc83d2914a
commit 7aab315ce5
1 changed files with 2 additions and 2 deletions
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vhdlpp/expression_elaborate.cc
+2 -2
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@@ -112,7 +112,7 @@ int ExpName::elaborate_lval_(Entity*ent, ScopeBase*scope, bool is_sequ, ExpName*
const VType*found_type = 0;
if (const InterfacePort*cur = ent->find_port(name_)) {
if (cur->mode != PORT_OUT) {
if (cur->mode != PORT_OUT && cur->mode != PORT_INOUT) {
cerr << get_fileline() << ": error: Assignment to "
"input port " << name_ << "." << endl;
return errors + 1;
@@ -216,7 +216,7 @@ int ExpName::elaborate_lval(Entity*ent, ScopeBase*scope, bool is_sequ)
const VType*found_type = 0;
if (const InterfacePort*cur = ent->find_port(name_)) {
if (cur->mode != PORT_OUT) {
if (cur->mode != PORT_OUT && cur->mode != PORT_INOUT) {
cerr << get_fileline() << ": error: Assignment to "
"input port " << name_ << "." << endl;
return errors += 1;