luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

vec4 implementations of real ternary and vec4 to real casts.

This commit is contained in:
Stephen Williams 2014-01-21 12:02:59 -08:00
parent 0121fbc88c
commit 54346d7095
4 changed files with 29 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
tgt-vvp/eval_real.c
View File

@ -348,35 +348,27 @@ static void draw_ternary_real(ivl_expr_t expr)
ivl_expr_t true_ex = ivl_expr_oper2(expr);
ivl_expr_t false_ex = ivl_expr_oper3(expr);
struct vector_info tst;
unsigned lab_true = local_count++;
unsigned lab_out = local_count++;
int cond_flag = allocate_flag();
/* Evaluate the ternary condition. */
tst = draw_eval_expr(cond, STUFF_OK_XZ|STUFF_OK_RO);
if ((tst.base >= 4) && (tst.wid > 1)) {
struct vector_info tmp;
draw_eval_vec4(cond, STUFF_OK_XZ|STUFF_OK_RO);
if (ivl_expr_width(cond) > 1)
fprintf(vvp_out, " %%or/r;\n");
fprintf(vvp_out, " %%or/r %u, %u, %u;\n",
tst.base, tst.base, tst.wid);
fprintf(vvp_out, " %%flag_set/vec4 %d;\n", cond_flag);
tmp = tst;
tmp.base += 1;
tmp.wid -= 1;
clr_vector(tmp);
tst.wid = 1;
}
/* Evaluate the true expression second. */
fprintf(vvp_out, " %%jmp/1 T_%u.%u, %u;\n",
thread_count, lab_true, tst.base);
fprintf(vvp_out, " %%jmp/1 T_%u.%u, %d;\n",
thread_count, lab_true, cond_flag);
/* Evaluate the false expression. */
draw_eval_real(false_ex);
fprintf(vvp_out, " %%jmp/0 T_%u.%u, %u; End of false expr.\n",
thread_count, lab_out, tst.base);
fprintf(vvp_out, " %%jmp/0 T_%u.%u, %d; End of false expr.\n",
thread_count, lab_out, cond_flag);
/* If the conditional is undefined then blend the real words. */
draw_eval_real(true_ex);
@ -391,7 +383,7 @@ static void draw_ternary_real(ivl_expr_t expr)
/* This is the out label. */
fprintf(vvp_out, "T_%u.%u ;\n", thread_count, lab_out);
clr_vector(tst);
clr_flag(cond_flag);
}
static void increment(ivl_expr_t e, bool pre)
@ -431,13 +423,11 @@ static void draw_unary_real(ivl_expr_t expr)
sube = ivl_expr_oper1(expr);
if (ivl_expr_opcode(expr) == 'r') { /* Cast an integer value to a real. */
struct vector_info res;
const char *suffix = "";
assert(ivl_expr_value(sube) != IVL_VT_REAL);
res = draw_eval_expr(sube, 1);
draw_eval_vec4(sube, STUFF_OK_XZ);
if (ivl_expr_signed(sube)) suffix = "/s";
fprintf(vvp_out, " %%cvt/rv%s %u, %u;\n", suffix, res.base, res.wid);
clr_vector(res);
fprintf(vvp_out, " %%cvt/rv%s;\n", suffix);
return;
}

4
vvp/compile.cc
View File

@ -133,8 +133,8 @@ static const struct opcode_table_s opcode_table[] = {
{ "%concati/str",of_CONCATI_STR,1,{OA_STRING,OA_NONE, OA_NONE} },
{ "%cvt/rs", of_CVT_RS, 1, {OA_BIT1, OA_NONE, OA_NONE} },
{ "%cvt/ru", of_CVT_RU, 1, {OA_BIT1, OA_NONE, OA_NONE} },
{ "%cvt/rv", of_CVT_RV, 2, {OA_BIT1, OA_BIT2, OA_NONE} },
{ "%cvt/rv/s", of_CVT_RV_S,2, {OA_BIT1, OA_BIT2, OA_NONE} },
{ "%cvt/rv", of_CVT_RV, 0, {OA_NONE, OA_NONE, OA_NONE} },
{ "%cvt/rv/s", of_CVT_RV_S,0, {OA_NONE, OA_NONE, OA_NONE} },
{ "%cvt/sr", of_CVT_SR, 1, {OA_BIT1, OA_NONE, OA_NONE} },
{ "%cvt/ur", of_CVT_UR, 1, {OA_BIT1, OA_NONE, OA_NONE} },
{ "%cvt/vr", of_CVT_VR, 1, {OA_NUMBER, OA_NONE, OA_NONE} },

8
vvp/opcodes.txt
View File

@ -986,12 +986,10 @@ truth table:
The results is then pushed onto the vec4 stack. The inputs and the
output are all the same width.
* %or/r <dst>, <src>, <wid>
This is a reduction version of the %or opcode. The <src> is a vector,
and the <dst> is a writable scalar. The <dst> gets the value of the
or of all the bits of the src vector.
* %or/r
This is a reduction version of the %or opcode. Pop a single value from
the vec4 stack, perform the reduction or and return the result to the stack.
* %pad <dst>, <src>, <wid> (XXXX Old version)

28
vvp/vthread.cc
View File

@ -2223,33 +2223,27 @@ bool of_CVT_RU(vthread_t thr, vvp_code_t cp)
return true;
}
bool of_CVT_RV(vthread_t thr, vvp_code_t cp)
/*
* %cvt/rv
*/
bool of_CVT_RV(vthread_t thr, vvp_code_t)
{
#if 0
unsigned base = cp->bit_idx[0];
unsigned wid = cp->bit_idx[1];
vvp_vector4_t vector = vthread_bits_to_vector(thr, base, wid);
double val;
vector4_to_value(vector, val, false);
vvp_vector4_t val4 = thr->pop_vec4();
vector4_to_value(val4, val, false);
thr->push_real(val);
#else
fprintf(stderr, "XXXX NOT IMPLEMENTED: %%cvt/rv ...\n");
#endif
return true;
}
/*
* %cvt/rv/s
*/
bool of_CVT_RV_S(vthread_t thr, vvp_code_t cp)
{
#if 0
unsigned base = cp->bit_idx[0];
unsigned wid = cp->bit_idx[1];
vvp_vector4_t vector = vthread_bits_to_vector(thr, base, wid);
double val;
vector4_to_value(vector, val, true);
vvp_vector4_t val4 = thr->pop_vec4();
vector4_to_value(val4, val, true);
thr->push_real(val);
#else
fprintf(stderr, "XXXX NOT IMPLEMENTED: %%cvt/rv/s ...\n");
#endif
return true;
}