Add regression tests for assignment operators on queue and darray elements

Check that assignment operators work as expected on queue and dynamic array
elements.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2025-01-03 12:28:42 -08:00
parent 7c970e91b9
commit 9f8a8959a7
6 changed files with 183 additions and 0 deletions

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@ -0,0 +1,86 @@
// Check that assignment operators are supported on dynamic array elements.
module test;
bit failed = 1'b0;
`define check(val, exp) do \
if (val !== exp) begin \
$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
failed = 1'b1; \
end \
while(0)
integer x[];
integer i;
initial begin
x = new[2];
// Static index
x[1] = 1;
x[1] += 5;
`check(x[1], 6);
x[1] -= 2;
`check(x[1], 4);
x[1] *= 25;
`check(x[1], 100);
x[1] /= 5;
`check(x[1], 20);
x[1] %= 3;
`check(x[1], 2);
x[1] = 'haa;
x[1] &= 'h33;
`check(x[1], 'h22);
x[1] |= 'h11;
`check(x[1], 'h33);
x[1] ^= 'h22;
`check(x[1], 'h11);
x[1] <<= 3;
`check(x[1], 'h88);
x[1] <<<= 1;
`check(x[1], 'h110);
x[1] >>= 2;
`check(x[1], 'h44);
x[1] >>>= 1;
`check(x[1], 'h22);
// Dynamic index
x[1] = 1;
i = 1;
x[i] += 5;
`check(x[i], 6);
x[i] -= 2;
`check(x[i], 4);
x[i] *= 25;
`check(x[i], 100);
x[i] /= 5;
`check(x[i], 20);
x[i] %= 3;
`check(x[i], 2);
x[i] = 'haa;
x[i] &= 'h33;
`check(x[i], 'h22);
x[i] |= 'h11;
`check(x[i], 'h33);
x[i] ^= 'h22;
`check(x[i], 'h11);
x[i] <<= 3;
`check(x[i], 'h88);
x[i] <<<= 1;
`check(x[i], 'h110);
x[i] >>= 2;
`check(x[i], 'h44);
x[i] >>>= 1;
`check(x[i], 'h22);
if (!failed) begin
$display("PASSED");
end
end
endmodule

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@ -0,0 +1,84 @@
// Check that assignment operators are supported on queue elements.
module test;
bit failed = 1'b0;
`define check(val, exp) do \
if (val !== exp) begin \
$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
failed = 1'b1; \
end \
while(0)
integer x[$];
integer i;
initial begin
x = '{0, 1};
// Static index
x[1] += 5;
`check(x[1], 6);
x[1] -= 2;
`check(x[1], 4);
x[1] *= 25;
`check(x[1], 100);
x[1] /= 5;
`check(x[1], 20);
x[1] %= 3;
`check(x[1], 2);
x[1] = 'haa;
x[1] &= 'h33;
`check(x[1], 'h22);
x[1] |= 'h11;
`check(x[1], 'h33);
x[1] ^= 'h22;
`check(x[1], 'h11);
x[1] <<= 3;
`check(x[1], 'h88);
x[1] <<<= 1;
`check(x[1], 'h110);
x[1] >>= 2;
`check(x[1], 'h44);
x[1] >>>= 1;
`check(x[1], 'h22);
// Dynamic index
x[1] = 1;
i = 1;
x[i] += 5;
`check(x[i], 6);
x[i] -= 2;
`check(x[i], 4);
x[i] *= 25;
`check(x[i], 100);
x[i] /= 5;
`check(x[i], 20);
x[i] %= 3;
`check(x[i], 2);
x[i] = 'haa;
x[i] &= 'h33;
`check(x[i], 'h22);
x[i] |= 'h11;
`check(x[i], 'h33);
x[i] ^= 'h22;
`check(x[i], 'h11);
x[i] <<= 3;
`check(x[i], 'h88);
x[i] <<<= 1;
`check(x[i], 'h110);
x[i] >>= 2;
`check(x[i], 'h44);
x[i] >>>= 1;
`check(x[i], 'h22);
if (!failed) begin
$display("PASSED");
end
end
endmodule

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@ -239,6 +239,7 @@ sv_const_fail6 vvp_tests/sv_const_fail6.json
sv_const_fail7 vvp_tests/sv_const_fail7.json
sv_const_fail8 vvp_tests/sv_const_fail8.json
sv_const_fail9 vvp_tests/sv_const_fail9.json
sv_darray_assign_op vvp_tests/sv_darray_assign_op.json
sv_default_port_value1 vvp_tests/sv_default_port_value1.json
sv_default_port_value2 vvp_tests/sv_default_port_value2.json
sv_default_port_value3 vvp_tests/sv_default_port_value3.json
@ -257,6 +258,7 @@ sv_module_port2 vvp_tests/sv_module_port2.json
sv_module_port3 vvp_tests/sv_module_port3.json
sv_module_port4 vvp_tests/sv_module_port4.json
sv_parameter_type vvp_tests/sv_parameter_type.json
sv_queue_assign_op vvp_tests/sv_queue_assign_op.json
sv_wildcard_import8 vvp_tests/sv_wildcard_import8.json
sdf_header vvp_tests/sdf_header.json
task_return1 vvp_tests/task_return1.json

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@ -0,0 +1,5 @@
{
"type" : "normal",
"source" : "sv_darray_assign_op.v",
"iverilog-args" : [ "-g2005-sv" ]
}

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@ -0,0 +1,5 @@
{
"type" : "normal",
"source" : "sv_queue_assign_op.v",
"iverilog-args" : [ "-g2005-sv" ]
}

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@ -1066,6 +1066,7 @@ static void show_stmt_assign_sig_darray_queue_mux(ivl_statement_t net)
case IVL_VT_STRING:
assert(ivl_stmt_opcode(net) == 0);
draw_eval_string(rval);
draw_eval_expr_into_integer(mux, 3);
break;
case IVL_VT_BOOL:
case IVL_VT_LOGIC: