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https://github.com/steveicarus/iverilog.git
synced 2026-09-05 16:56:06 +02:00
Give module port atom2 objects their proper widths.
These widths can be expressions as ranges, but must be present as this is how we identify them as the various types of ints.
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@@ -1920,17 +1920,18 @@ port_declaration
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| attribute_list_opt K_input atom2_type signed_unsigned_opt IDENTIFIER
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{ Module::port_t*ptmp;
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perm_string name = lex_strings.make($5);
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svector<PExpr*>*use_range = make_range_from_width($3);
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ptmp = pform_module_port_reference(name, @2.text,
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@2.first_line);
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pform_module_define_port(@2, name, NetNet::PINPUT,
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NetNet::UNRESOLVED_WIRE, IVL_VT_BOOL,
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$4, 0, $1);
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$4, use_range, $1);
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port_declaration_context.port_type = NetNet::PINPUT;
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port_declaration_context.port_net_type = NetNet::UNRESOLVED_WIRE;
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port_declaration_context.var_type = IVL_VT_BOOL;
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port_declaration_context.sign_flag = $4;
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delete port_declaration_context.range;
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port_declaration_context.range = 0;
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port_declaration_context.range = use_range;
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delete $1;
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delete[]$5;
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$$ = ptmp;
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@@ -2013,17 +2014,18 @@ port_declaration
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| attribute_list_opt K_output atom2_type signed_unsigned_opt IDENTIFIER
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{ Module::port_t*ptmp;
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perm_string name = lex_strings.make($5);
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svector<PExpr*>*use_range = make_range_from_width($3);
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ptmp = pform_module_port_reference(name, @2.text,
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@2.first_line);
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pform_module_define_port(@2, name, NetNet::POUTPUT,
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NetNet::IMPLICIT_REG, IVL_VT_BOOL,
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$4, 0, $1);
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$4, use_range, $1);
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port_declaration_context.port_type = NetNet::POUTPUT;
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port_declaration_context.port_net_type = NetNet::IMPLICIT_REG;
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port_declaration_context.var_type = IVL_VT_BOOL;
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port_declaration_context.sign_flag = $4;
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delete port_declaration_context.range;
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port_declaration_context.range = 0;
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port_declaration_context.range = use_range;
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delete $1;
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delete[]$5;
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$$ = ptmp;
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