Add regression test for automatic terms in assignment patterns

Check that automatic variables referenced through an assignment pattern in a
procedural `force` statement are rejected.

Signed-off-by: Lars-Peter Clausen <[email protected]>
This commit is contained in:
Lars-Peter Clausen
2026-06-30 18:25:52 -07:00
parent 9bff2399df
commit 9bbdb0da0e
3 changed files with 25 additions and 0 deletions
@@ -0,0 +1,19 @@
// Check that assignment patterns cannot reference automatic variables in
// procedural force statements.
module test;
reg [3:0] result;
task automatic t;
input [3:0] value;
begin
force result = '{value[3], value[2], value[1], value[0]};
end
endtask
initial begin
t(4'ha);
end
endmodule
+1
View File
@@ -259,6 +259,7 @@ sv_array_cassign9 vvp_tests/sv_array_cassign9.json
sv_array_cassign10 vvp_tests/sv_array_cassign10.json
sv_array_cassign_single vvp_tests/sv_array_cassign_single.json
sv_array_cassign_single_fail1 vvp_tests/sv_array_cassign_single_fail1.json
sv_assign_pattern_auto_force_fail vvp_tests/sv_assign_pattern_auto_force_fail.json
sv_automatic_2state vvp_tests/sv_automatic_2state.json
sv_bad_member_lval_proc_fail vvp_tests/sv_bad_member_lval_proc_fail.json
sv_byte_array_string1 vvp_tests/sv_byte_array_string1.json
@@ -0,0 +1,5 @@
{
"type" : "CE",
"source" : "sv_assign_pattern_auto_force_fail.v",
"iverilog-args" : [ "-g2005-sv" ]
}