Add regression test for omitting trailing ports in ordered list connection

Check that it is possible to omit trailing ports in a module ordered list
connection list.

Also check that an error is generated if too many ports are specified in a
ordered list connection.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2023-06-11 07:54:56 -07:00
parent b8eb21b3ac
commit 37f7308f80
5 changed files with 70 additions and 0 deletions

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@ -0,0 +1,35 @@
// Check that it is possible to omit trailing module ports in a ordered list
// connection if the trailing port has a default value.
module M (
output logic a,
input logic b,
input logic c = 1'b0,
input logic d = 1'b1
);
assign a = b ^ c ^ d;
endmodule
module test;
logic a, b, c;
logic x, y;
assign b = 1'b0;
assign c = 1'b1;
assign y = 1'b1;
M i_M1 (a, b, c);
M i_M2 (x, y);
initial begin
#1
if (a !== 1'b0 || x !== 1'b0) begin
$display("FAILED");
end else begin
$display("PASSED");
end
end
endmodule

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// Check that an error is reported when specifying too many ports in a ordered
// list connection.
module M (
output a,
input b
);
assign a = b;
endmodule
module test;
wire a, b, c;
assign b = 1'b0;
assign c = 1'b1;
M i_M (a, b, c); // Error, too many ports.
initial begin
$display("FAILED");
end
endmodule

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@ -26,6 +26,8 @@ dumpfile vvp_tests/dumpfile.json
final3 vvp_tests/final3.json
macro_str_esc vvp_tests/macro_str_esc.json
memsynth1 vvp_tests/memsynth1.json
module_ordered_list1 vvp_tests/module_ordered_list1.json
module_ordered_list2 vvp_tests/module_ordered_list2.json
module_port_array1 vvp_tests/module_port_array1.json
param-width vvp_tests/param-width.json
param-width-vlog95 vvp_tests/param-width-vlog95.json

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{
"type" : "normal",
"source" : "module_ordered_list1.v",
"iverilog-args" : [ "-g2005-sv" ]
}

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{
"type" : "CE",
"source" : "module_ordered_list2.v"
}