Bitwise AND

2008-06-21 15:05:48 +01:00 · 2008-06-21 15:05:48 +01:00 · 58f2f5007d
parent 0caf4fd9d0
commit 58f2f5007d
1 changed files with 2 additions and 0 deletions
--- a/tgt-vhdl/expr.cc
+++ b/tgt-vhdl/expr.cc
@ -165,6 +165,8 @@ static vhdl_expr *translate_binary(ivl_expr_t e)
                                   rhs->cast(&std_logic_vector), VHDL_BINOP_NEQ);
      else
         return translate_relation(lhs, rhs, VHDL_BINOP_NEQ);
+   case '&':    // Bitwise AND
+      return translate_numeric(lhs, rhs, VHDL_BINOP_AND);
   case 'o':
      return translate_relation(lhs, rhs, VHDL_BINOP_OR);
   default: