NetLatch class
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f176106c54
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c92b630728
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@ -688,6 +688,14 @@ void NetFF::dump_node(ostream&o, unsigned ind) const
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dump_obj_attr(o, ind+4);
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}
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void NetLatch::dump_node(ostream&o, unsigned ind) const
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{
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o << setw(ind) << "" << "LPM_LATCH: " << name()
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<< " scope=" << scope_path(scope()) << endl;
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dump_node_pins(o, ind+4);
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dump_obj_attr(o, ind+4);
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}
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void NetLiteral::dump_node(ostream&o, unsigned ind) const
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{
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o << setw(ind) << "" << "constant real " << real_
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6
emit.cc
6
emit.cc
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@ -123,6 +123,12 @@ bool NetFF::emit_node(struct target_t*tgt) const
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return true;
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}
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bool NetLatch::emit_node(struct target_t*tgt) const
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{
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tgt->lpm_latch(this);
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return true;
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}
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bool NetLiteral::emit_node(struct target_t*tgt) const
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{
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return tgt->net_literal(this);
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@ -78,6 +78,10 @@ void functor_t::lpm_ff(Design*, NetFF*)
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{
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}
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void functor_t::lpm_latch(Design*, NetLatch*)
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{
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}
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void functor_t::lpm_logic(Design*, NetLogic*)
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{
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}
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@ -219,6 +223,11 @@ void NetFF::functor_node(Design*des, functor_t*fun)
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fun->lpm_ff(des, this);
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}
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void NetLatch::functor_node(Design*des, functor_t*fun)
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{
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fun->lpm_latch(des, this);
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}
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void NetLiteral::functor_node(Design*des, functor_t*fun)
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{
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fun->lpm_literal(des, this);
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@ -75,6 +75,9 @@ struct functor_t {
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/* This method is called for each FF in the design. */
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virtual void lpm_ff(class Design*des, class NetFF*);
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/* This method is called for each LATCH in the design. */
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virtual void lpm_latch(class Design*des, class NetLatch*);
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/* Handle LPM combinational logic devices. */
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virtual void lpm_logic(class Design*des, class NetLogic*);
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54
netlist.cc
54
netlist.cc
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@ -1306,6 +1306,60 @@ const verinum& NetFF::sset_value() const
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return sset_value_;
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}
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/*
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* The NetLatch class represents an LPM_LATCH device. The pinout is assigned
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* like so:
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* 0 -- Enable
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* 1 -- Data
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* 2 -- Q
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*/
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NetLatch::NetLatch(NetScope*s, perm_string n, unsigned width__)
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: NetNode(s, n, 3), width_(width__)
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{
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pin_Enable().set_dir(Link::INPUT);
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pin_Data().set_dir(Link::INPUT);
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pin_Q().set_dir(Link::OUTPUT);
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}
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NetLatch::~NetLatch()
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{
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}
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unsigned NetLatch::width() const
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{
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return width_;
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}
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Link& NetLatch::pin_Enable()
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{
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return pin(0);
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}
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const Link& NetLatch::pin_Enable() const
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{
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return pin(0);
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}
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Link& NetLatch::pin_Data()
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{
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return pin(1);
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}
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const Link& NetLatch::pin_Data() const
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{
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return pin(1);
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}
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Link& NetLatch::pin_Q()
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{
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return pin(2);
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}
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const Link& NetLatch::pin_Q() const
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{
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return pin(2);
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}
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NetAbs::NetAbs(NetScope*s, perm_string n, unsigned w)
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: NetNode(s, n, 2), width_(w)
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29
netlist.h
29
netlist.h
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@ -1684,6 +1684,35 @@ class NetFF : public NetNode {
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verinum sset_value_;
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};
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/*
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* This class represents an LPM_LATCH device. There is no literal gate
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* type in Verilog that maps, but gates of this type can be inferred.
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*/
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class NetLatch : public NetNode {
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public:
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NetLatch(NetScope*s, perm_string n, unsigned vector_width);
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~NetLatch();
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unsigned width() const;
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Link& pin_Enable();
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Link& pin_Data();
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Link& pin_Q();
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const Link& pin_Enable() const;
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const Link& pin_Data() const;
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const Link& pin_Q() const;
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virtual void dump_node(ostream&, unsigned ind) const;
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virtual bool emit_node(struct target_t*) const;
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virtual void functor_node(Design*des, functor_t*fun);
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private:
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unsigned width_;
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};
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/*
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* This class implements a basic LPM_MULT combinational multiplier. It
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* is used as a structural representation of the * operator. The
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@ -183,6 +183,12 @@ void target_t::lpm_ff(const NetFF*)
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"Unhandled NetFF." << endl;
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}
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void target_t::lpm_latch(const NetLatch*)
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{
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cerr << "target (" << typeid(*this).name() << "): "
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"Unhandled NetLatch." << endl;
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}
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void target_t::lpm_mult(const NetMult*)
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{
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cerr << "target (" << typeid(*this).name() << "): "
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