luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Translate a BUFT device correctly in VHDL back end 

When the BUFT device was added to the compiler nothing was done to
support it in the VHDL translator. This patch rectifies that oversight.
This commit is contained in:
Cary R 2011-06-22 17:33:21 -07:00 committed by Stephen Williams
parent 85fd3a9005
commit bc8704e47d
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
tgt-vhdl/logic.cc
View File

@ -1,7 +1,7 @@
/*
* VHDL code generation for logic devices.
*
* Copyright (C) 2008-2009 Nick Gasson (nick@nickg.me.uk)
* Copyright (C) 2008-2011 Nick Gasson (nick@nickg.me.uk)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -247,6 +247,7 @@ static vhdl_expr *translate_logic_inputs(vhdl_scope *scope, ivl_net_logic_t log)
case IVL_LO_XNOR:
return inputs_to_expr(scope, VHDL_BINOP_XNOR, log);
case IVL_LO_BUF:
case IVL_LO_BUFT:
case IVL_LO_BUFZ:
return nexus_to_var_ref(scope, ivl_logic_pin(log, 1));
case IVL_LO_PULLUP: