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iverilog
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Switch blif test to support python3 and use common program name

This commit is contained in:
Cary R 2026-02-06 09:46:55 -08:00
parent 826672705e
commit 827e08f8d3
1 changed files with 5 additions and 5 deletions
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10
ivtest/blif_reg.py
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@ -51,7 +51,7 @@ def run_test(test):
if rc == 0:
# Use ABC to convert the .blif file to Verilog
abc_cmd = "abc -c 'read_blif tmp_blif.blif ; write_verilog tmp_blif.v' >> " + redirect
abc_cmd = "berkeley-abc -c 'read_blif tmp_blif.blif ; write_verilog tmp_blif.v' >> " + redirect
rc = subprocess.call(abc_cmd, shell=True);
if rc == 0:
@ -66,10 +66,10 @@ def run_test(test):
rc = 0 if output == "PASSED\n" else 1
if rc == 0:
print test, "PASSED"
print(test, "PASSED")
count_passed = count_passed + 1
else:
print test, "FAILED"
print(test, "FAILED")
count_failed = count_failed + 1
for tmp in ["tmp_blif.blif", "tmp_blif.v", "tmp_blif.vvp"]:
@ -82,5 +82,5 @@ count_failed = 0
for test in tests:
run_test(test)
print
print count_passed, "tests passed,", count_failed, "tests failed."
print()
print(count_passed, "tests passed,", count_failed, "tests failed.")