Factor out code for reporting mixed assignment conflicts.
This makes the error reporting uniform.
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9faf8d6b09
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2
PExpr.h
2
PExpr.h
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@ -423,6 +423,8 @@ class PEIdent : public PExpr {
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private:
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void report_mixed_assignment_conflict_(const char*category) const;
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NetAssign_ *elaborate_lval_array_(Design *des, NetScope *scope,
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bool is_force, NetNet *reg) const;
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NetAssign_ *elaborate_lval_var_(Design *des, NetScope *scope,
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43
elab_lval.cc
43
elab_lval.cc
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@ -70,6 +70,12 @@ using namespace std;
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* elaboration makes a single NetAssign_ and connects it up properly.
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*/
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void PEIdent::report_mixed_assignment_conflict_(const char*category) const
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{
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cerr << get_fileline() << ": error: Cannot perform procedural "
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"assignment to " << category << " '" << path_
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<< "' because it is also continuously assigned." << endl;
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}
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/*
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* The default interpretation of an l-value to a procedural assignment
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@ -333,9 +339,7 @@ NetAssign_*PEIdent::elaborate_lval_var_(Design *des, NetScope *scope,
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if (reg->type()==NetNet::UNRESOLVED_WIRE && !is_force) {
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ivl_assert(*this, reg->coerced_to_uwire());
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cerr << get_fileline() << ": error: Cannot perform "
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"procedural assignment to '" << reg->name()
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<< "' because it is also continuously assigned." << endl;
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report_mixed_assignment_conflict_("variable");
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des->errors += 1;
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return 0;
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}
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@ -363,9 +367,7 @@ NetAssign_*PEIdent::elaborate_lval_array_(Design *des, NetScope *,
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if (name_tail.index.empty()) {
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if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
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ivl_assert(*this, reg->coerced_to_uwire());
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cerr << get_fileline() << ": error: Cannot perform "
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"procedural assignment to array '" << reg->name()
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<< "' because it is also continuously assigned." << endl;
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report_mixed_assignment_conflict_("array");
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des->errors += 1;
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return 0;
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}
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@ -471,9 +473,7 @@ NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
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NetEConst*canon_const = dynamic_cast<NetEConst*>(canon_index);
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if (!canon_const || reg->test_part_driven(reg->vector_width() - 1, 0,
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canon_const->value().as_long())) {
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cerr << get_fileline() << ": error: Cannot perform "
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"procedural assignment to word in array '" << reg->name()
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<< "' because it is also continuously assigned." << endl;
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report_mixed_assignment_conflict_("array word");
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des->errors += 1;
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return 0;
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}
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@ -613,11 +613,12 @@ bool PEIdent::elaborate_lval_net_bit_(Design*des,
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ivl_assert(*this, rcl);
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if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
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ivl_assert(*this, reg->coerced_to_uwire());
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bool rct = reg->test_and_set_part_driver(loff+lwid-1, loff);
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if (rct) {
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cerr << get_fileline() << ": error: "
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<< "These bits are already driven." << endl;
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report_mixed_assignment_conflict_("slice");
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des->errors += 1;
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return false;
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}
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}
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@ -682,11 +683,12 @@ bool PEIdent::elaborate_lval_net_bit_(Design*des,
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}
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if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
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ivl_assert(*this, reg->coerced_to_uwire());
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bool rct = reg->test_and_set_part_driver(loff, loff);
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if (rct) {
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cerr << get_fileline() << ": error: "
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<< "Bit " << loff << " is already driven." << endl;
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report_mixed_assignment_conflict_("bit select");
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des->errors += 1;
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return false;
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}
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}
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@ -708,9 +710,8 @@ bool PEIdent::elaborate_lval_darray_bit_(Design*des,
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ivl_assert(*this, name_tail.index.size() == 1);
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if ((lv->sig()->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
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cerr << get_fileline() << ": error: "
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<< path_ << " Unable to darray word select unresolved wires."
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<< endl;
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ivl_assert(*this, lv->sig()->coerced_to_uwire());
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report_mixed_assignment_conflict_("darray word");
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des->errors += 1;
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return false;
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}
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@ -769,11 +770,10 @@ bool PEIdent::elaborate_lval_net_part_(Design*des,
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}
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if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
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ivl_assert(*this, reg->coerced_to_uwire());
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bool rct = reg->test_and_set_part_driver(msb, lsb);
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if (rct) {
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cerr << get_fileline() << ": error: "
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<< path_ << "Part select is double-driving unresolved wire."
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<< endl;
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report_mixed_assignment_conflict_("part select");
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des->errors += 1;
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return false;
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}
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@ -1544,9 +1544,8 @@ bool PEIdent::elaborate_lval_net_packed_member_(Design*des, NetScope*scope,
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}
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if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
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cerr << get_fileline() << ": error: "
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<< path_ << " Unable to member-select unresolved wires."
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<< endl;
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ivl_assert(*this, reg->coerced_to_uwire());
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report_mixed_assignment_conflict_("variable");
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des->errors += 1;
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return false;
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}
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