Support bufif for tri1 nets

tgt-vhdl/scope.cc

@@ -158,8 +158,21 @@ static void bufif_logic(vhdl_arch *arch, ivl_net_logic_t log, bool if0)
    vhdl_expr *on = new vhdl_const_bit(if0 ? '0' : '1');
    vhdl_expr *cmp = new vhdl_binop_expr(sel, VHDL_BINOP_EQ, on, NULL);
 
-   // TODO: This value needs to depend on the net type
-   vhdl_const_bit *z = new vhdl_const_bit('0');
+   ivl_signal_t sig = find_signal_named(lhs->get_name(), arch->get_scope());
+   char zbit;
+   switch (ivl_signal_type(sig)) {
+   case IVL_SIT_TRI0:
+      zbit = '0';
+      break;
+   case IVL_SIT_TRI1:
+      zbit = '1';
+      break;
+   case IVL_SIT_TRI:
+   default:
+      zbit = 'Z';
+   }
+   
+   vhdl_const_bit *z = new vhdl_const_bit(zbit);
    vhdl_cassign_stmt *cass = new vhdl_cassign_stmt(lhs, z);
    cass->add_condition(val, cmp);
 

tgt-vhdl/vhdl.cc

@@ -134,7 +134,9 @@ ivl_signal_t find_signal_named(const std::string &name, const vhdl_scope *scope)
 {
    signal_defn_map_t::const_iterator it;
    for (it = g_known_signals.begin(); it != g_known_signals.end(); ++it) {
-      if ((*it).second.scope == scope && (*it).second.renamed == name)
+      if (((*it).second.scope == scope
+           || (*it).second.scope == scope->get_parent())
+          && (*it).second.renamed == name)
          return (*it).first;
    }
    assert(false);

tgt-vhdl/vhdl_syntax.cc

@@ -57,7 +57,7 @@ bool vhdl_scope::have_declared(const std::string &name) const
    return get_decl(name) != NULL;
 }
 
-vhdl_scope *vhdl_scope::get_parent()
+vhdl_scope *vhdl_scope::get_parent() const
 {
    assert(parent_);
    return parent_;

tgt-vhdl/vhdl_syntax.hh

@@ -557,7 +557,7 @@ public:
    void add_decl(vhdl_decl *decl);
    vhdl_decl *get_decl(const std::string &name) const;
    bool have_declared(const std::string &name) const;
-   vhdl_scope *get_parent();
+   vhdl_scope *get_parent() const;
    
    bool empty() const { return decls_.empty(); }
    const decl_list_t &get_decls() const { return decls_; }