Remove debugging information from the output
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parent
632a265e14
commit
88dc9b6b63
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@ -49,8 +49,6 @@ static vhdl_var_ref *translate_signal(ivl_expr_t e)
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const vhdl_decl *decl = ent->get_arch()->get_decl(strip_var(renamed));
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assert(decl);
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std::cout << "ref: " << renamed << " width=" << decl->get_type()->get_width() << std::endl;
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vhdl_type *type = new vhdl_type(*decl->get_type());
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return new vhdl_var_ref(renamed, type);
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@ -142,11 +140,8 @@ static vhdl_expr *translate_binary(ivl_expr_t e)
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else
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opwidth = lwidth;
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std::cout << "lwidth=" << lwidth << " rwidth=" << rwidth << std::endl;
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// For === and !== we need to compare std_logic_vectors
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// rather than signeds
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int msb = ivl_expr_width(e) - 1;
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vhdl_type std_logic_vector(VHDL_TYPE_STD_LOGIC_VECTOR, opwidth-1, 0);
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bool vectorop =
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(lhs->get_type()->get_name() == VHDL_TYPE_SIGNED
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@ -462,10 +462,10 @@ vhdl_expr::~vhdl_expr()
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*/
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vhdl_expr *vhdl_expr::cast(const vhdl_type *to)
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{
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std::cout << "Cast: from=" << type_->get_string()
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<< " (" << type_->get_width() << ") "
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<< " to=" << to->get_string() << " ("
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<< to->get_width() << ")" << std::endl;
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//std::cout << "Cast: from=" << type_->get_string()
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// << " (" << type_->get_width() << ") "
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// << " to=" << to->get_string() << " ("
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// << to->get_width() << ")" << std::endl;
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if (to->get_name() == type_->get_name()) {
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if (to->get_width() == type_->get_width())
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@ -618,9 +618,6 @@ vhdl_const_bits::vhdl_const_bits(const char *value, int width, bool issigned)
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// Can't rely on value being NULL-terminated
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while (width--)
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value_.push_back(*value++);
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std::cout << (issigned ? "signed" : "unsigned") << " bits: "
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<< value_ << std::endl;
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}
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vhdl_expr *vhdl_const_bits::cast(const vhdl_type *to)
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